1*4882a593Smuzhiyun.. _amu_index: 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun======================================================= 4*4882a593SmuzhiyunActivity Monitors Unit (AMU) extension in AArch64 Linux 5*4882a593Smuzhiyun======================================================= 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunAuthor: Ionela Voinescu <ionela.voinescu@arm.com> 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunDate: 2019-09-10 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThis document briefly describes the provision of Activity Monitors Unit 12*4882a593Smuzhiyunsupport in AArch64 Linux. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunArchitecture overview 16*4882a593Smuzhiyun--------------------- 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunThe activity monitors extension is an optional extension introduced by the 19*4882a593SmuzhiyunARMv8.4 CPU architecture. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunThe activity monitors unit, implemented in each CPU, provides performance 22*4882a593Smuzhiyuncounters intended for system management use. The AMU extension provides a 23*4882a593Smuzhiyunsystem register interface to the counter registers and also supports an 24*4882a593Smuzhiyunoptional external memory-mapped interface. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunVersion 1 of the Activity Monitors architecture implements a counter group 27*4882a593Smuzhiyunof four fixed and architecturally defined 64-bit event counters. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun - CPU cycle counter: increments at the frequency of the CPU. 30*4882a593Smuzhiyun - Constant counter: increments at the fixed frequency of the system 31*4882a593Smuzhiyun clock. 32*4882a593Smuzhiyun - Instructions retired: increments with every architecturally executed 33*4882a593Smuzhiyun instruction. 34*4882a593Smuzhiyun - Memory stall cycles: counts instruction dispatch stall cycles caused by 35*4882a593Smuzhiyun misses in the last level cache within the clock domain. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunWhen in WFI or WFE these counters do not increment. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunThe Activity Monitors architecture provides space for up to 16 architected 40*4882a593Smuzhiyunevent counters. Future versions of the architecture may use this space to 41*4882a593Smuzhiyunimplement additional architected event counters. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunAdditionally, version 1 implements a counter group of up to 16 auxiliary 44*4882a593Smuzhiyun64-bit event counters. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunOn cold reset all counters reset to 0. 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunBasic support 50*4882a593Smuzhiyun------------- 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunThe kernel can safely run a mix of CPUs with and without support for the 53*4882a593Smuzhiyunactivity monitors extension. Therefore, when CONFIG_ARM64_AMU_EXTN is 54*4882a593Smuzhiyunselected we unconditionally enable the capability to allow any late CPU 55*4882a593Smuzhiyun(secondary or hotplugged) to detect and use the feature. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunWhen the feature is detected on a CPU, we flag the availability of the 58*4882a593Smuzhiyunfeature but this does not guarantee the correct functionality of the 59*4882a593Smuzhiyuncounters, only the presence of the extension. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunFirmware (code running at higher exception levels, e.g. arm-tf) support is 62*4882a593Smuzhiyunneeded to: 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun - Enable access for lower exception levels (EL2 and EL1) to the AMU 65*4882a593Smuzhiyun registers. 66*4882a593Smuzhiyun - Enable the counters. If not enabled these will read as 0. 67*4882a593Smuzhiyun - Save/restore the counters before/after the CPU is being put/brought up 68*4882a593Smuzhiyun from the 'off' power state. 69*4882a593Smuzhiyun 70*4882a593SmuzhiyunWhen using kernels that have this feature enabled but boot with broken 71*4882a593Smuzhiyunfirmware the user may experience panics or lockups when accessing the 72*4882a593Smuzhiyuncounter registers. Even if these symptoms are not observed, the values 73*4882a593Smuzhiyunreturned by the register reads might not correctly reflect reality. Most 74*4882a593Smuzhiyuncommonly, the counters will read as 0, indicating that they are not 75*4882a593Smuzhiyunenabled. 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunIf proper support is not provided in firmware it's best to disable 78*4882a593SmuzhiyunCONFIG_ARM64_AMU_EXTN. To be noted that for security reasons, this does not 79*4882a593Smuzhiyunbypass the setting of AMUSERENR_EL0 to trap accesses from EL0 (userspace) to 80*4882a593SmuzhiyunEL1 (kernel). Therefore, firmware should still ensure accesses to AMU registers 81*4882a593Smuzhiyunare not trapped in EL2/EL3. 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunThe fixed counters of AMUv1 are accessible though the following system 84*4882a593Smuzhiyunregister definitions: 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun - SYS_AMEVCNTR0_CORE_EL0 87*4882a593Smuzhiyun - SYS_AMEVCNTR0_CONST_EL0 88*4882a593Smuzhiyun - SYS_AMEVCNTR0_INST_RET_EL0 89*4882a593Smuzhiyun - SYS_AMEVCNTR0_MEM_STALL_EL0 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunAuxiliary platform specific counters can be accessed using 92*4882a593SmuzhiyunSYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15. 93*4882a593Smuzhiyun 94*4882a593SmuzhiyunDetails can be found in: arch/arm64/include/asm/sysreg.h. 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunUserspace access 98*4882a593Smuzhiyun---------------- 99*4882a593Smuzhiyun 100*4882a593SmuzhiyunCurrently, access from userspace to the AMU registers is disabled due to: 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun - Security reasons: they might expose information about code executed in 103*4882a593Smuzhiyun secure mode. 104*4882a593Smuzhiyun - Purpose: AMU counters are intended for system management use. 105*4882a593Smuzhiyun 106*4882a593SmuzhiyunAlso, the presence of the feature is not visible to userspace. 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun 109*4882a593SmuzhiyunVirtualization 110*4882a593Smuzhiyun-------------- 111*4882a593Smuzhiyun 112*4882a593SmuzhiyunCurrently, access from userspace (EL0) and kernelspace (EL1) on the KVM 113*4882a593Smuzhiyunguest side is disabled due to: 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun - Security reasons: they might expose information about code executed 116*4882a593Smuzhiyun by other guests or the host. 117*4882a593Smuzhiyun 118*4882a593SmuzhiyunAny attempt to access the AMU registers will result in an UNDEFINED 119*4882a593Smuzhiyunexception being injected into the guest. 120