1*4882a593Smuzhiyun======================= 2*4882a593SmuzhiyunS3C24XX CPUfreq support 3*4882a593Smuzhiyun======================= 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunIntroduction 6*4882a593Smuzhiyun------------ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun The S3C24XX series support a number of power saving systems, such as 9*4882a593Smuzhiyun the ability to change the core, memory and peripheral operating 10*4882a593Smuzhiyun frequencies. The core control is exported via the CPUFreq driver 11*4882a593Smuzhiyun which has a number of different manual or automatic controls over the 12*4882a593Smuzhiyun rate the core is running at. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun There are two forms of the driver depending on the specific CPU and 15*4882a593Smuzhiyun how the clocks are arranged. The first implementation used as single 16*4882a593Smuzhiyun PLL to feed the ARM, memory and peripherals via a series of dividers 17*4882a593Smuzhiyun and muxes and this is the implementation that is documented here. A 18*4882a593Smuzhiyun newer version where there is a separate PLL and clock divider for the 19*4882a593Smuzhiyun ARM core is available as a separate driver. 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunLayout 23*4882a593Smuzhiyun------ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun The code core manages the CPU specific drivers, any data that they 26*4882a593Smuzhiyun need to register and the interface to the generic drivers/cpufreq 27*4882a593Smuzhiyun system. Each CPU registers a driver to control the PLL, clock dividers 28*4882a593Smuzhiyun and anything else associated with it. Any board that wants to use this 29*4882a593Smuzhiyun framework needs to supply at least basic details of what is required. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun The core registers with drivers/cpufreq at init time if all the data 32*4882a593Smuzhiyun necessary has been supplied. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunCPU support 36*4882a593Smuzhiyun----------- 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun The support for each CPU depends on the facilities provided by the 39*4882a593Smuzhiyun SoC and the driver as each device has different PLL and clock chains 40*4882a593Smuzhiyun associated with it. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunSlow Mode 44*4882a593Smuzhiyun--------- 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun The SLOW mode where the PLL is turned off altogether and the 47*4882a593Smuzhiyun system is fed by the external crystal input is currently not 48*4882a593Smuzhiyun supported. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunsysfs 52*4882a593Smuzhiyun----- 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun The core code exports extra information via sysfs in the directory 55*4882a593Smuzhiyun devices/system/cpu/cpu0/arch-freq. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunBoard Support 59*4882a593Smuzhiyun------------- 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun Each board that wants to use the cpufreq code must register some basic 62*4882a593Smuzhiyun information with the core driver to provide information about what the 63*4882a593Smuzhiyun board requires and any restrictions being placed on it. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun The board needs to supply information about whether it needs the IO bank 66*4882a593Smuzhiyun timings changing, any maximum frequency limits and information about the 67*4882a593Smuzhiyun SDRAM refresh rate. 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunDocument Author 73*4882a593Smuzhiyun--------------- 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunBen Dooks, Copyright 2009 Simtec Electronics 76*4882a593SmuzhiyunLicensed under GPLv2 77