xref: /OK3568_Linux_fs/kernel/Documentation/arm/nwfpe/netwinder-fpe.rst (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun=============
2*4882a593SmuzhiyunCurrent State
3*4882a593Smuzhiyun=============
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunThe following describes the current state of the NetWinder's floating point
6*4882a593Smuzhiyunemulator.
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunIn the following nomenclature is used to describe the floating point
9*4882a593Smuzhiyuninstructions.  It follows the conventions in the ARM manual.
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun::
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun  <S|D|E> = <single|double|extended>, no default
14*4882a593Smuzhiyun  {P|M|Z} = {round to +infinity,round to -infinity,round to zero},
15*4882a593Smuzhiyun            default = round to nearest
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunNote: items enclosed in {} are optional.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunFloating Point Coprocessor Data Transfer Instructions (CPDT)
20*4882a593Smuzhiyun------------------------------------------------------------
21*4882a593Smuzhiyun
22*4882a593SmuzhiyunLDF/STF - load and store floating
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun<LDF|STF>{cond}<S|D|E> Fd, Rn
25*4882a593Smuzhiyun<LDF|STF>{cond}<S|D|E> Fd, [Rn, #<expression>]{!}
26*4882a593Smuzhiyun<LDF|STF>{cond}<S|D|E> Fd, [Rn], #<expression>
27*4882a593Smuzhiyun
28*4882a593SmuzhiyunThese instructions are fully implemented.
29*4882a593Smuzhiyun
30*4882a593SmuzhiyunLFM/SFM - load and store multiple floating
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunForm 1 syntax:
33*4882a593Smuzhiyun<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn]
34*4882a593Smuzhiyun<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn, #<expression>]{!}
35*4882a593Smuzhiyun<LFM|SFM>{cond}<S|D|E> Fd, <count>, [Rn], #<expression>
36*4882a593Smuzhiyun
37*4882a593SmuzhiyunForm 2 syntax:
38*4882a593Smuzhiyun<LFM|SFM>{cond}<FD,EA> Fd, <count>, [Rn]{!}
39*4882a593Smuzhiyun
40*4882a593SmuzhiyunThese instructions are fully implemented.  They store/load three words
41*4882a593Smuzhiyunfor each floating point register into the memory location given in the
42*4882a593Smuzhiyuninstruction.  The format in memory is unlikely to be compatible with
43*4882a593Smuzhiyunother implementations, in particular the actual hardware.  Specific
44*4882a593Smuzhiyunmention of this is made in the ARM manuals.
45*4882a593Smuzhiyun
46*4882a593SmuzhiyunFloating Point Coprocessor Register Transfer Instructions (CPRT)
47*4882a593Smuzhiyun----------------------------------------------------------------
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunConversions, read/write status/control register instructions
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunFLT{cond}<S,D,E>{P,M,Z} Fn, Rd          Convert integer to floating point
52*4882a593SmuzhiyunFIX{cond}{P,M,Z} Rd, Fn                 Convert floating point to integer
53*4882a593SmuzhiyunWFS{cond} Rd                            Write floating point status register
54*4882a593SmuzhiyunRFS{cond} Rd                            Read floating point status register
55*4882a593SmuzhiyunWFC{cond} Rd                            Write floating point control register
56*4882a593SmuzhiyunRFC{cond} Rd                            Read floating point control register
57*4882a593Smuzhiyun
58*4882a593SmuzhiyunFLT/FIX are fully implemented.
59*4882a593Smuzhiyun
60*4882a593SmuzhiyunRFS/WFS are fully implemented.
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunRFC/WFC are fully implemented.  RFC/WFC are supervisor only instructions, and
63*4882a593Smuzhiyunpresently check the CPU mode, and do an invalid instruction trap if not called
64*4882a593Smuzhiyunfrom supervisor mode.
65*4882a593Smuzhiyun
66*4882a593SmuzhiyunCompare instructions
67*4882a593Smuzhiyun
68*4882a593SmuzhiyunCMF{cond} Fn, Fm        Compare floating
69*4882a593SmuzhiyunCMFE{cond} Fn, Fm       Compare floating with exception
70*4882a593SmuzhiyunCNF{cond} Fn, Fm        Compare negated floating
71*4882a593SmuzhiyunCNFE{cond} Fn, Fm       Compare negated floating with exception
72*4882a593Smuzhiyun
73*4882a593SmuzhiyunThese are fully implemented.
74*4882a593Smuzhiyun
75*4882a593SmuzhiyunFloating Point Coprocessor Data Instructions (CPDT)
76*4882a593Smuzhiyun---------------------------------------------------
77*4882a593Smuzhiyun
78*4882a593SmuzhiyunDyadic operations:
79*4882a593Smuzhiyun
80*4882a593SmuzhiyunADF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - add
81*4882a593SmuzhiyunSUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - subtract
82*4882a593SmuzhiyunRSF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse subtract
83*4882a593SmuzhiyunMUF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - multiply
84*4882a593SmuzhiyunDVF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - divide
85*4882a593SmuzhiyunRDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse divide
86*4882a593Smuzhiyun
87*4882a593SmuzhiyunThese are fully implemented.
88*4882a593Smuzhiyun
89*4882a593SmuzhiyunFML{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast multiply
90*4882a593SmuzhiyunFDV{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast divide
91*4882a593SmuzhiyunFRD{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - fast reverse divide
92*4882a593Smuzhiyun
93*4882a593SmuzhiyunThese are fully implemented as well.  They use the same algorithm as the
94*4882a593Smuzhiyunnon-fast versions.  Hence, in this implementation their performance is
95*4882a593Smuzhiyunequivalent to the MUF/DVF/RDV instructions.  This is acceptable according
96*4882a593Smuzhiyunto the ARM manual.  The manual notes these are defined only for single
97*4882a593Smuzhiyunoperands, on the actual FPA11 hardware they do not work for double or
98*4882a593Smuzhiyunextended precision operands.  The emulator currently does not check
99*4882a593Smuzhiyunthe requested permissions conditions, and performs the requested operation.
100*4882a593Smuzhiyun
101*4882a593SmuzhiyunRMF{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - IEEE remainder
102*4882a593Smuzhiyun
103*4882a593SmuzhiyunThis is fully implemented.
104*4882a593Smuzhiyun
105*4882a593SmuzhiyunMonadic operations:
106*4882a593Smuzhiyun
107*4882a593SmuzhiyunMVF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move
108*4882a593SmuzhiyunMNF{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - move negated
109*4882a593Smuzhiyun
110*4882a593SmuzhiyunThese are fully implemented.
111*4882a593Smuzhiyun
112*4882a593SmuzhiyunABS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - absolute value
113*4882a593SmuzhiyunSQT{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - square root
114*4882a593SmuzhiyunRND{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - round
115*4882a593Smuzhiyun
116*4882a593SmuzhiyunThese are fully implemented.
117*4882a593Smuzhiyun
118*4882a593SmuzhiyunURD{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - unnormalized round
119*4882a593SmuzhiyunNRM{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - normalize
120*4882a593Smuzhiyun
121*4882a593SmuzhiyunThese are implemented.  URD is implemented using the same code as the RND
122*4882a593Smuzhiyuninstruction.  Since URD cannot return a unnormalized number, NRM becomes
123*4882a593Smuzhiyuna NOP.
124*4882a593Smuzhiyun
125*4882a593SmuzhiyunLibrary calls:
126*4882a593Smuzhiyun
127*4882a593SmuzhiyunPOW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - power
128*4882a593SmuzhiyunRPW{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - reverse power
129*4882a593SmuzhiyunPOL{cond}<S|D|E>{P,M,Z} Fd, Fn, <Fm,#value> - polar angle (arctan2)
130*4882a593Smuzhiyun
131*4882a593SmuzhiyunLOG{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base 10
132*4882a593SmuzhiyunLGN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - logarithm to base e
133*4882a593SmuzhiyunEXP{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - exponent
134*4882a593SmuzhiyunSIN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - sine
135*4882a593SmuzhiyunCOS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - cosine
136*4882a593SmuzhiyunTAN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - tangent
137*4882a593SmuzhiyunASN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arcsine
138*4882a593SmuzhiyunACS{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arccosine
139*4882a593SmuzhiyunATN{cond}<S|D|E>{P,M,Z} Fd, <Fm,#value> - arctangent
140*4882a593Smuzhiyun
141*4882a593SmuzhiyunThese are not implemented.  They are not currently issued by the compiler,
142*4882a593Smuzhiyunand are handled by routines in libc.  These are not implemented by the FPA11
143*4882a593Smuzhiyunhardware, but are handled by the floating point support code.  They should
144*4882a593Smuzhiyunbe implemented in future versions.
145*4882a593Smuzhiyun
146*4882a593SmuzhiyunSignalling:
147*4882a593Smuzhiyun
148*4882a593SmuzhiyunSignals are implemented.  However current ELF kernels produced by Rebel.com
149*4882a593Smuzhiyunhave a bug in them that prevents the module from generating a SIGFPE.  This
150*4882a593Smuzhiyunis caused by a failure to alias fp_current to the kernel variable
151*4882a593Smuzhiyuncurrent_set[0] correctly.
152*4882a593Smuzhiyun
153*4882a593SmuzhiyunThe kernel provided with this distribution (vmlinux-nwfpe-0.93) contains
154*4882a593Smuzhiyuna fix for this problem and also incorporates the current version of the
155*4882a593Smuzhiyunemulator directly.  It is possible to run with no floating point module
156*4882a593Smuzhiyunloaded with this kernel.  It is provided as a demonstration of the
157*4882a593Smuzhiyuntechnology and for those who want to do floating point work that depends
158*4882a593Smuzhiyunon signals.  It is not strictly necessary to use the module.
159*4882a593Smuzhiyun
160*4882a593SmuzhiyunA module (either the one provided by Russell King, or the one in this
161*4882a593Smuzhiyundistribution) can be loaded to replace the functionality of the emulator
162*4882a593Smuzhiyunbuilt into the kernel.
163