1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun.. include:: <isonum.txt> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun====================================== 5*4882a593SmuzhiyunIntel Performance and Energy Bias Hint 6*4882a593Smuzhiyun====================================== 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun:Copyright: |copy| 2019 Intel Corporation 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun:Author: Rafael J. Wysocki <rafael.j.wysocki@intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun.. kernel-doc:: arch/x86/kernel/cpu/intel_epb.c 14*4882a593Smuzhiyun :doc: overview 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunIntel Performance and Energy Bias Attribute in ``sysfs`` 17*4882a593Smuzhiyun======================================================== 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe Intel Performance and Energy Bias Hint (EPB) value for a given (logical) CPU 20*4882a593Smuzhiyuncan be checked or updated through a ``sysfs`` attribute (file) under 21*4882a593Smuzhiyun:file:`/sys/devices/system/cpu/cpu<N>/power/`, where the CPU number ``<N>`` 22*4882a593Smuzhiyunis allocated at the system initialization time: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun``energy_perf_bias`` 25*4882a593Smuzhiyun Shows the current EPB value for the CPU in a sliding scale 0 - 15, where 26*4882a593Smuzhiyun a value of 0 corresponds to a hint preference for highest performance 27*4882a593Smuzhiyun and a value of 15 corresponds to the maximum energy savings. 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun In order to update the EPB value for the CPU, this attribute can be 30*4882a593Smuzhiyun written to, either with a number in the 0 - 15 sliding scale above, or 31*4882a593Smuzhiyun with one of the strings: "performance", "balance-performance", "normal", 32*4882a593Smuzhiyun "balance-power", "power" that represent values reflected by their 33*4882a593Smuzhiyun meaning. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun This attribute is present for all online CPUs supporting the EPB 36*4882a593Smuzhiyun feature. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunNote that while the EPB interface to the processor is defined at the logical CPU 39*4882a593Smuzhiyunlevel, the physical register backing it may be shared by multiple CPUs (for 40*4882a593Smuzhiyunexample, SMT siblings or cores in one package). For this reason, updating the 41*4882a593SmuzhiyunEPB value for one CPU may cause the EPB values for other CPUs to change. 42