1*4882a593Smuzhiyun=========================================================================== 2*4882a593SmuzhiyunQualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU) 3*4882a593Smuzhiyun=========================================================================== 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunThis driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies 6*4882a593SmuzhiyunCentriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared 7*4882a593Smuzhiyunby all cores within a socket. Each slice is exposed as a separate uncore perf 8*4882a593SmuzhiyunPMU with device name l3cache_<socket>_<instance>. User space is responsible 9*4882a593Smuzhiyunfor aggregating across slices. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe driver provides a description of its available events and configuration 12*4882a593Smuzhiyunoptions in sysfs, see /sys/devices/l3cache*. Given that these are uncore PMUs 13*4882a593Smuzhiyunthe driver also exposes a "cpumask" sysfs attribute which contains a mask 14*4882a593Smuzhiyunconsisting of one CPU per socket which will be used to handle all the PMU 15*4882a593Smuzhiyunevents on that socket. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe hardware implements 32bit event counters and has a flat 8bit event space 18*4882a593Smuzhiyunexposed via the "event" format attribute. In addition to the 32bit physical 19*4882a593Smuzhiyuncounters the driver supports virtual 64bit hardware counters by using hardware 20*4882a593Smuzhiyuncounter chaining. This feature is exposed via the "lc" (long counter) format 21*4882a593Smuzhiyunflag. E.g.:: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun perf stat -e l3cache_0_0/read-miss,lc/ 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunGiven that these are uncore PMUs the driver does not support sampling, therefore 26*4882a593Smuzhiyun"perf record" will not work. Per-task perf sessions are not supported. 27