xref: /OK3568_Linux_fs/kernel/Documentation/admin-guide/media/qcom_camss.rst (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun.. include:: <isonum.txt>
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunQualcomm Camera Subsystem driver
6*4882a593Smuzhiyun================================
7*4882a593Smuzhiyun
8*4882a593SmuzhiyunIntroduction
9*4882a593Smuzhiyun------------
10*4882a593Smuzhiyun
11*4882a593SmuzhiyunThis file documents the Qualcomm Camera Subsystem driver located under
12*4882a593Smuzhiyundrivers/media/platform/qcom/camss.
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunThe current version of the driver supports the Camera Subsystem found on
15*4882a593SmuzhiyunQualcomm MSM8916/APQ8016 and MSM8996/APQ8096 processors.
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunThe driver implements V4L2, Media controller and V4L2 subdev interfaces.
18*4882a593SmuzhiyunCamera sensor using V4L2 subdev interface in the kernel is supported.
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunThe driver is implemented using as a reference the Qualcomm Camera Subsystem
21*4882a593Smuzhiyundriver for Android as found in Code Aurora [#f1]_ [#f2]_.
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunQualcomm Camera Subsystem hardware
25*4882a593Smuzhiyun----------------------------------
26*4882a593Smuzhiyun
27*4882a593SmuzhiyunThe Camera Subsystem hardware found on 8x16 / 8x96 processors and supported by
28*4882a593Smuzhiyunthe driver consists of:
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun- 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
31*4882a593Smuzhiyun  A separate camera sensor can be connected to each of the CSIPHY module;
32*4882a593Smuzhiyun- 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
33*4882a593Smuzhiyun  layer of the CSI2 receivers. A CSID can decode data stream from any of the
34*4882a593Smuzhiyun  CSIPHY. Each CSID also contains a TG (Test Generator) block which can generate
35*4882a593Smuzhiyun  artificial input data for test purposes;
36*4882a593Smuzhiyun- ISPIF (ISP Interface) module. Handles the routing of the data streams from
37*4882a593Smuzhiyun  the CSIDs to the inputs of the VFE;
38*4882a593Smuzhiyun- 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
39*4882a593Smuzhiyun  hardware blocks. The VFE has different input interfaces. The PIX (Pixel) input
40*4882a593Smuzhiyun  interface feeds the input data to the image processing pipeline. The image
41*4882a593Smuzhiyun  processing pipeline contains also a scale and crop module at the end. Three
42*4882a593Smuzhiyun  RDI (Raw Dump Interface) input interfaces bypass the image processing
43*4882a593Smuzhiyun  pipeline. The VFE also contains the AXI bus interface which writes the output
44*4882a593Smuzhiyun  data to memory.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun
47*4882a593SmuzhiyunSupported functionality
48*4882a593Smuzhiyun-----------------------
49*4882a593Smuzhiyun
50*4882a593SmuzhiyunThe current version of the driver supports:
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun- Input from camera sensor via CSIPHY;
53*4882a593Smuzhiyun- Generation of test input data by the TG in CSID;
54*4882a593Smuzhiyun- RDI interface of VFE
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun  - Raw dump of the input data to memory.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun    Supported formats:
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun    - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
61*4882a593Smuzhiyun      V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY);
62*4882a593Smuzhiyun    - MIPI RAW8 (8bit Bayer RAW - V4L2_PIX_FMT_SRGGB8 /
63*4882a593Smuzhiyun      V4L2_PIX_FMT_SGRBG8 / V4L2_PIX_FMT_SGBRG8 / V4L2_PIX_FMT_SBGGR8);
64*4882a593Smuzhiyun    - MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P /
65*4882a593Smuzhiyun      V4L2_PIX_FMT_SGBRG10P / V4L2_PIX_FMT_SGRBG10P / V4L2_PIX_FMT_SRGGB10P /
66*4882a593Smuzhiyun      V4L2_PIX_FMT_Y10P);
67*4882a593Smuzhiyun    - MIPI RAW12 (12bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB12P /
68*4882a593Smuzhiyun      V4L2_PIX_FMT_SGBRG12P / V4L2_PIX_FMT_SGRBG12P / V4L2_PIX_FMT_SRGGB12P).
69*4882a593Smuzhiyun    - (8x96 only) MIPI RAW14 (14bit packed Bayer RAW - V4L2_PIX_FMT_SRGGB14P /
70*4882a593Smuzhiyun      V4L2_PIX_FMT_SGBRG14P / V4L2_PIX_FMT_SGRBG14P / V4L2_PIX_FMT_SRGGB14P).
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun  - (8x96 only) Format conversion of the input data.
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun    Supported input formats:
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun    - MIPI RAW10 (10bit packed Bayer RAW - V4L2_PIX_FMT_SBGGR10P / V4L2_PIX_FMT_Y10P).
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun    Supported output formats:
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun    - Plain16 RAW10 (10bit unpacked Bayer RAW - V4L2_PIX_FMT_SBGGR10 / V4L2_PIX_FMT_Y10).
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun- PIX interface of VFE
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun  - Format conversion of the input data.
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun    Supported input formats:
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun    - YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
89*4882a593Smuzhiyun      V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY).
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun    Supported output formats:
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun    - NV12/NV21 (two plane YUV 4:2:0 - V4L2_PIX_FMT_NV12 / V4L2_PIX_FMT_NV21);
94*4882a593Smuzhiyun    - NV16/NV61 (two plane YUV 4:2:2 - V4L2_PIX_FMT_NV16 / V4L2_PIX_FMT_NV61).
95*4882a593Smuzhiyun    - (8x96 only) YUYV/UYVY/YVYU/VYUY (packed YUV 4:2:2 - V4L2_PIX_FMT_YUYV /
96*4882a593Smuzhiyun      V4L2_PIX_FMT_UYVY / V4L2_PIX_FMT_YVYU / V4L2_PIX_FMT_VYUY).
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun  - Scaling support. Configuration of the VFE Encoder Scale module
99*4882a593Smuzhiyun    for downscalling with ratio up to 16x.
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun  - Cropping support. Configuration of the VFE Encoder Crop module.
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun- Concurrent and independent usage of two (8x96: three) data inputs -
104*4882a593Smuzhiyun  could be camera sensors and/or TG.
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun
107*4882a593SmuzhiyunDriver Architecture and Design
108*4882a593Smuzhiyun------------------------------
109*4882a593Smuzhiyun
110*4882a593SmuzhiyunThe driver implements the V4L2 subdev interface. With the goal to model the
111*4882a593Smuzhiyunhardware links between the modules and to expose a clean, logical and usable
112*4882a593Smuzhiyuninterface, the driver is split into V4L2 sub-devices as follows (8x16 / 8x96):
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun- 2 / 3 CSIPHY sub-devices - each CSIPHY is represented by a single sub-device;
115*4882a593Smuzhiyun- 2 / 4 CSID sub-devices - each CSID is represented by a single sub-device;
116*4882a593Smuzhiyun- 2 / 4 ISPIF sub-devices - ISPIF is represented by a number of sub-devices
117*4882a593Smuzhiyun  equal to the number of CSID sub-devices;
118*4882a593Smuzhiyun- 4 / 8 VFE sub-devices - VFE is represented by a number of sub-devices equal to
119*4882a593Smuzhiyun  the number of the input interfaces (3 RDI and 1 PIX for each VFE).
120*4882a593Smuzhiyun
121*4882a593SmuzhiyunThe considerations to split the driver in this particular way are as follows:
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun- representing CSIPHY and CSID modules by a separate sub-device for each module
124*4882a593Smuzhiyun  allows to model the hardware links between these modules;
125*4882a593Smuzhiyun- representing VFE by a separate sub-devices for each input interface allows
126*4882a593Smuzhiyun  to use the input interfaces concurrently and independently as this is
127*4882a593Smuzhiyun  supported by the hardware;
128*4882a593Smuzhiyun- representing ISPIF by a number of sub-devices equal to the number of CSID
129*4882a593Smuzhiyun  sub-devices allows to create linear media controller pipelines when using two
130*4882a593Smuzhiyun  cameras simultaneously. This avoids branches in the pipelines which otherwise
131*4882a593Smuzhiyun  will require a) userspace and b) media framework (e.g. power on/off
132*4882a593Smuzhiyun  operations) to  make assumptions about the data flow from a sink pad to a
133*4882a593Smuzhiyun  source pad on a single media entity.
134*4882a593Smuzhiyun
135*4882a593SmuzhiyunEach VFE sub-device is linked to a separate video device node.
136*4882a593Smuzhiyun
137*4882a593SmuzhiyunThe media controller pipeline graph is as follows (with connected two / three
138*4882a593SmuzhiyunOV5645 camera sensors):
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun.. _qcom_camss_graph:
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun.. kernel-figure:: qcom_camss_graph.dot
143*4882a593Smuzhiyun    :alt:   qcom_camss_graph.dot
144*4882a593Smuzhiyun    :align: center
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun    Media pipeline graph 8x16
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun.. kernel-figure:: qcom_camss_8x96_graph.dot
149*4882a593Smuzhiyun    :alt:   qcom_camss_8x96_graph.dot
150*4882a593Smuzhiyun    :align: center
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun    Media pipeline graph 8x96
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun
155*4882a593SmuzhiyunImplementation
156*4882a593Smuzhiyun--------------
157*4882a593Smuzhiyun
158*4882a593SmuzhiyunRuntime configuration of the hardware (updating settings while streaming) is
159*4882a593Smuzhiyunnot required to implement the currently supported functionality. The complete
160*4882a593Smuzhiyunconfiguration on each hardware module is applied on STREAMON ioctl based on
161*4882a593Smuzhiyunthe current active media links, formats and controls set.
162*4882a593Smuzhiyun
163*4882a593SmuzhiyunThe output size of the scaler module in the VFE is configured with the actual
164*4882a593Smuzhiyuncompose selection rectangle on the sink pad of the 'msm_vfe0_pix' entity.
165*4882a593Smuzhiyun
166*4882a593SmuzhiyunThe crop output area of the crop module in the VFE is configured with the actual
167*4882a593Smuzhiyuncrop selection rectangle on the source pad of the 'msm_vfe0_pix' entity.
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun
170*4882a593SmuzhiyunDocumentation
171*4882a593Smuzhiyun-------------
172*4882a593Smuzhiyun
173*4882a593SmuzhiyunAPQ8016 Specification:
174*4882a593Smuzhiyunhttps://developer.qualcomm.com/download/sd410/snapdragon-410-processor-device-specification.pdf
175*4882a593SmuzhiyunReferenced 2016-11-24.
176*4882a593Smuzhiyun
177*4882a593SmuzhiyunAPQ8096 Specification:
178*4882a593Smuzhiyunhttps://developer.qualcomm.com/download/sd820e/qualcomm-snapdragon-820e-processor-apq8096sge-device-specification.pdf
179*4882a593SmuzhiyunReferenced 2018-06-22.
180*4882a593Smuzhiyun
181*4882a593SmuzhiyunReferences
182*4882a593Smuzhiyun----------
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun.. [#f1] https://source.codeaurora.org/quic/la/kernel/msm-3.10/
185*4882a593Smuzhiyun.. [#f2] https://source.codeaurora.org/quic/la/kernel/msm-3.18/
186