1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun================= 4*4882a593SmuzhiyunPCI Test Function 5*4882a593Smuzhiyun================= 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun:Author: Kishon Vijay Abraham I <kishon@ti.com> 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunTraditionally PCI RC has always been validated by using standard 10*4882a593SmuzhiyunPCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards. 11*4882a593SmuzhiyunHowever with the addition of EP-core in linux kernel, it is possible 12*4882a593Smuzhiyunto configure a PCI controller that can operate in EP mode to work as 13*4882a593Smuzhiyuna test device. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe PCI endpoint test device is a virtual device (defined in software) 16*4882a593Smuzhiyunused to test the endpoint functionality and serve as a sample driver 17*4882a593Smuzhiyunfor other PCI endpoint devices (to use the EP framework). 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe PCI endpoint test device has the following registers: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 1) PCI_ENDPOINT_TEST_MAGIC 22*4882a593Smuzhiyun 2) PCI_ENDPOINT_TEST_COMMAND 23*4882a593Smuzhiyun 3) PCI_ENDPOINT_TEST_STATUS 24*4882a593Smuzhiyun 4) PCI_ENDPOINT_TEST_SRC_ADDR 25*4882a593Smuzhiyun 5) PCI_ENDPOINT_TEST_DST_ADDR 26*4882a593Smuzhiyun 6) PCI_ENDPOINT_TEST_SIZE 27*4882a593Smuzhiyun 7) PCI_ENDPOINT_TEST_CHECKSUM 28*4882a593Smuzhiyun 8) PCI_ENDPOINT_TEST_IRQ_TYPE 29*4882a593Smuzhiyun 9) PCI_ENDPOINT_TEST_IRQ_NUMBER 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_MAGIC 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunThis register will be used to test BAR0. A known pattern will be written 34*4882a593Smuzhiyunand read back from MAGIC register to verify BAR0. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_COMMAND 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunThis register will be used by the host driver to indicate the function 39*4882a593Smuzhiyunthat the endpoint device must perform. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun======== ================================================================ 42*4882a593SmuzhiyunBitfield Description 43*4882a593Smuzhiyun======== ================================================================ 44*4882a593SmuzhiyunBit 0 raise legacy IRQ 45*4882a593SmuzhiyunBit 1 raise MSI IRQ 46*4882a593SmuzhiyunBit 2 raise MSI-X IRQ 47*4882a593SmuzhiyunBit 3 read command (read data from RC buffer) 48*4882a593SmuzhiyunBit 4 write command (write data to RC buffer) 49*4882a593SmuzhiyunBit 5 copy command (copy data from one RC buffer to another RC buffer) 50*4882a593Smuzhiyun======== ================================================================ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_STATUS 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunThis register reflects the status of the PCI endpoint device. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun======== ============================== 57*4882a593SmuzhiyunBitfield Description 58*4882a593Smuzhiyun======== ============================== 59*4882a593SmuzhiyunBit 0 read success 60*4882a593SmuzhiyunBit 1 read fail 61*4882a593SmuzhiyunBit 2 write success 62*4882a593SmuzhiyunBit 3 write fail 63*4882a593SmuzhiyunBit 4 copy success 64*4882a593SmuzhiyunBit 5 copy fail 65*4882a593SmuzhiyunBit 6 IRQ raised 66*4882a593SmuzhiyunBit 7 source address is invalid 67*4882a593SmuzhiyunBit 8 destination address is invalid 68*4882a593Smuzhiyun======== ============================== 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_SRC_ADDR 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunThis register contains the source address (RC buffer address) for the 73*4882a593SmuzhiyunCOPY/READ command. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_DST_ADDR 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunThis register contains the destination address (RC buffer address) for 78*4882a593Smuzhiyunthe COPY/WRITE command. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_IRQ_TYPE 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunThis register contains the interrupt type (Legacy/MSI) triggered 83*4882a593Smuzhiyunfor the READ/WRITE/COPY and raise IRQ (Legacy/MSI) commands. 84*4882a593Smuzhiyun 85*4882a593SmuzhiyunPossible types: 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun====== == 88*4882a593SmuzhiyunLegacy 0 89*4882a593SmuzhiyunMSI 1 90*4882a593SmuzhiyunMSI-X 2 91*4882a593Smuzhiyun====== == 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun* PCI_ENDPOINT_TEST_IRQ_NUMBER 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunThis register contains the triggered ID interrupt. 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunAdmissible values: 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun====== =========== 100*4882a593SmuzhiyunLegacy 0 101*4882a593SmuzhiyunMSI [1 .. 32] 102*4882a593SmuzhiyunMSI-X [1 .. 2048] 103*4882a593Smuzhiyun====== =========== 104