1*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/chanops/chan*/priority 2*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/chanops/chan*/priority 3*4882a593SmuzhiyunDate: Nov 2015 4*4882a593SmuzhiyunKernelVersion: 4.4 5*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 6*4882a593SmuzhiyunDescription: 7*4882a593Smuzhiyun Contains either 0 or 1 and indicates if the DMA channel is a 8*4882a593Smuzhiyun low priority (0) or high priority (1) channel. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/chanops/chan*/weight 11*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/chanops/chan*/weight 12*4882a593SmuzhiyunDate: Nov 2015 13*4882a593SmuzhiyunKernelVersion: 4.4 14*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 15*4882a593SmuzhiyunDescription: 16*4882a593Smuzhiyun Contains 0..15 and indicates the weight of the channel among 17*4882a593Smuzhiyun equal priority channels during round robin scheduling. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/chreset_timeout_cycles 20*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/chreset_timeout_cycles 21*4882a593SmuzhiyunDate: Nov 2015 22*4882a593SmuzhiyunKernelVersion: 4.4 23*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 24*4882a593SmuzhiyunDescription: 25*4882a593Smuzhiyun Contains the platform specific cycle value to wait after a 26*4882a593Smuzhiyun reset command is issued. If the value is chosen too short, 27*4882a593Smuzhiyun then the HW will issue a reset failure interrupt. The value 28*4882a593Smuzhiyun is platform specific and should not be changed without 29*4882a593Smuzhiyun consultance. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/dma_channels 32*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/dma_channels 33*4882a593SmuzhiyunDate: Nov 2015 34*4882a593SmuzhiyunKernelVersion: 4.4 35*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 36*4882a593SmuzhiyunDescription: 37*4882a593Smuzhiyun Contains the number of dma channels supported by one instance 38*4882a593Smuzhiyun of HIDMA hardware. The value may change from chip to chip. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/hw_version_major 41*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/hw_version_major 42*4882a593SmuzhiyunDate: Nov 2015 43*4882a593SmuzhiyunKernelVersion: 4.4 44*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 45*4882a593SmuzhiyunDescription: 46*4882a593Smuzhiyun Version number major for the hardware. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/hw_version_minor 49*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/hw_version_minor 50*4882a593SmuzhiyunDate: Nov 2015 51*4882a593SmuzhiyunKernelVersion: 4.4 52*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 53*4882a593SmuzhiyunDescription: 54*4882a593Smuzhiyun Version number minor for the hardware. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/max_rd_xactions 57*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/max_rd_xactions 58*4882a593SmuzhiyunDate: Nov 2015 59*4882a593SmuzhiyunKernelVersion: 4.4 60*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 61*4882a593SmuzhiyunDescription: 62*4882a593Smuzhiyun Contains a value between 0 and 31. Maximum number of 63*4882a593Smuzhiyun read transactions that can be issued back to back. 64*4882a593Smuzhiyun Choosing a higher number gives better performance but 65*4882a593Smuzhiyun can also cause performance reduction to other peripherals 66*4882a593Smuzhiyun sharing the same bus. 67*4882a593Smuzhiyun 68*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/max_read_request 69*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/max_read_request 70*4882a593SmuzhiyunDate: Nov 2015 71*4882a593SmuzhiyunKernelVersion: 4.4 72*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 73*4882a593SmuzhiyunDescription: 74*4882a593Smuzhiyun Size of each read request. The value needs to be a power 75*4882a593Smuzhiyun of two and can be between 128 and 1024. 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/max_wr_xactions 78*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/max_wr_xactions 79*4882a593SmuzhiyunDate: Nov 2015 80*4882a593SmuzhiyunKernelVersion: 4.4 81*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 82*4882a593SmuzhiyunDescription: 83*4882a593Smuzhiyun Contains a value between 0 and 31. Maximum number of 84*4882a593Smuzhiyun write transactions that can be issued back to back. 85*4882a593Smuzhiyun Choosing a higher number gives better performance but 86*4882a593Smuzhiyun can also cause performance reduction to other peripherals 87*4882a593Smuzhiyun sharing the same bus. 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunWhat: /sys/devices/platform/hidma-mgmt*/max_write_request 91*4882a593Smuzhiyun /sys/devices/platform/QCOM8060:*/max_write_request 92*4882a593SmuzhiyunDate: Nov 2015 93*4882a593SmuzhiyunKernelVersion: 4.4 94*4882a593SmuzhiyunContact: "Sinan Kaya <okaya@codeaurora.org>" 95*4882a593SmuzhiyunDescription: 96*4882a593Smuzhiyun Size of each write request. The value needs to be a power 97*4882a593Smuzhiyun of two and can be between 128 and 1024. 98