1*4882a593SmuzhiyunWhat: /sys/devices/*/<our-device>/fuse 2*4882a593SmuzhiyunDate: February 2014 3*4882a593SmuzhiyunContact: Peter De Schrijver <pdeschrijver@nvidia.com> 4*4882a593SmuzhiyunDescription: read-only access to the efuses on Tegra20, Tegra30, Tegra114 5*4882a593Smuzhiyun and Tegra124 SoC's from NVIDIA. The efuses contain write once 6*4882a593Smuzhiyun data programmed at the factory. The data is layed out in 32bit 7*4882a593Smuzhiyun words in LSB first format. Each bit represents a single value 8*4882a593Smuzhiyun as decoded from the fuse registers. Bits order/assignment 9*4882a593Smuzhiyun exactly matches the HW registers, including any unused bits. 10*4882a593SmuzhiyunUsers: any user space application which wants to read the efuses on 11*4882a593Smuzhiyun Tegra SoC's 12