1*4882a593SmuzhiyunWhat: /sys/class/pwm/ 2*4882a593SmuzhiyunDate: May 2013 3*4882a593SmuzhiyunKernelVersion: 3.11 4*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 5*4882a593SmuzhiyunDescription: 6*4882a593Smuzhiyun The pwm/ class sub-directory belongs to the Generic PWM 7*4882a593Smuzhiyun Framework and provides a sysfs interface for using PWM 8*4882a593Smuzhiyun channels. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/ 11*4882a593SmuzhiyunDate: May 2013 12*4882a593SmuzhiyunKernelVersion: 3.11 13*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 14*4882a593SmuzhiyunDescription: 15*4882a593Smuzhiyun A /sys/class/pwm/pwmchipN directory is created for each 16*4882a593Smuzhiyun probed PWM controller/chip where N is the base of the 17*4882a593Smuzhiyun PWM chip. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/npwm 20*4882a593SmuzhiyunDate: May 2013 21*4882a593SmuzhiyunKernelVersion: 3.11 22*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 23*4882a593SmuzhiyunDescription: 24*4882a593Smuzhiyun The number of PWM channels supported by the PWM chip. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/export 27*4882a593SmuzhiyunDate: May 2013 28*4882a593SmuzhiyunKernelVersion: 3.11 29*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 30*4882a593SmuzhiyunDescription: 31*4882a593Smuzhiyun Exports a PWM channel from the PWM chip for sysfs control. 32*4882a593Smuzhiyun Value is between 0 and /sys/class/pwm/pwmchipN/npwm - 1. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/unexport 35*4882a593SmuzhiyunDate: May 2013 36*4882a593SmuzhiyunKernelVersion: 3.11 37*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 38*4882a593SmuzhiyunDescription: 39*4882a593Smuzhiyun Unexports a PWM channel. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX 42*4882a593SmuzhiyunDate: May 2013 43*4882a593SmuzhiyunKernelVersion: 3.11 44*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 45*4882a593SmuzhiyunDescription: 46*4882a593Smuzhiyun A /sys/class/pwm/pwmchipN/pwmX directory is created for 47*4882a593Smuzhiyun each exported PWM channel where X is the exported PWM 48*4882a593Smuzhiyun channel number. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX/period 51*4882a593SmuzhiyunDate: May 2013 52*4882a593SmuzhiyunKernelVersion: 3.11 53*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 54*4882a593SmuzhiyunDescription: 55*4882a593Smuzhiyun Sets the PWM signal period in nanoseconds. 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX/duty_cycle 58*4882a593SmuzhiyunDate: May 2013 59*4882a593SmuzhiyunKernelVersion: 3.11 60*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 61*4882a593SmuzhiyunDescription: 62*4882a593Smuzhiyun Sets the PWM signal duty cycle in nanoseconds. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX/polarity 65*4882a593SmuzhiyunDate: May 2013 66*4882a593SmuzhiyunKernelVersion: 3.11 67*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 68*4882a593SmuzhiyunDescription: 69*4882a593Smuzhiyun Sets the output polarity of the PWM signal to "normal" or 70*4882a593Smuzhiyun "inversed". 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX/enable 73*4882a593SmuzhiyunDate: May 2013 74*4882a593SmuzhiyunKernelVersion: 3.11 75*4882a593SmuzhiyunContact: H Hartley Sweeten <hsweeten@visionengravers.com> 76*4882a593SmuzhiyunDescription: 77*4882a593Smuzhiyun Enable/disable the PWM signal. 78*4882a593Smuzhiyun 0 is disabled 79*4882a593Smuzhiyun 1 is enabled 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunWhat: /sys/class/pwm/pwmchipN/pwmX/capture 82*4882a593SmuzhiyunDate: June 2016 83*4882a593SmuzhiyunKernelVersion: 4.8 84*4882a593SmuzhiyunContact: Lee Jones <lee.jones@linaro.org> 85*4882a593SmuzhiyunDescription: 86*4882a593Smuzhiyun Capture information about a PWM signal. The output format is a 87*4882a593Smuzhiyun pair unsigned integers (period and duty cycle), separated by a 88*4882a593Smuzhiyun single space. 89