1*4882a593SmuzhiyunWhat: /sys/class/fpga_manager/<fpga>/name 2*4882a593SmuzhiyunDate: August 2015 3*4882a593SmuzhiyunKernelVersion: 4.3 4*4882a593SmuzhiyunContact: Alan Tull <atull@opensource.altera.com> 5*4882a593SmuzhiyunDescription: Name of low level fpga manager driver. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunWhat: /sys/class/fpga_manager/<fpga>/state 8*4882a593SmuzhiyunDate: August 2015 9*4882a593SmuzhiyunKernelVersion: 4.3 10*4882a593SmuzhiyunContact: Alan Tull <atull@opensource.altera.com> 11*4882a593SmuzhiyunDescription: Read fpga manager state as a string. 12*4882a593Smuzhiyun The intent is to provide enough detail that if something goes 13*4882a593Smuzhiyun wrong during FPGA programming (something that the driver can't 14*4882a593Smuzhiyun fix) then userspace can know, i.e. if the firmware request 15*4882a593Smuzhiyun fails, that could be due to not being able to find the firmware 16*4882a593Smuzhiyun file. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun This is a superset of FPGA states and fpga manager driver 19*4882a593Smuzhiyun states. The fpga manager driver is walking through these steps 20*4882a593Smuzhiyun to get the FPGA into a known operating state. It's a sequence, 21*4882a593Smuzhiyun though some steps may get skipped. Valid FPGA states will vary 22*4882a593Smuzhiyun by manufacturer; this is a superset. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun * unknown = can't determine state 25*4882a593Smuzhiyun * power off = FPGA power is off 26*4882a593Smuzhiyun * power up = FPGA reports power is up 27*4882a593Smuzhiyun * reset = FPGA held in reset state 28*4882a593Smuzhiyun * firmware request = firmware class request in progress 29*4882a593Smuzhiyun * firmware request error = firmware request failed 30*4882a593Smuzhiyun * write init = preparing FPGA for programming 31*4882a593Smuzhiyun * write init error = Error while preparing FPGA for programming 32*4882a593Smuzhiyun * write = FPGA ready to receive image data 33*4882a593Smuzhiyun * write error = Error while programming 34*4882a593Smuzhiyun * write complete = Doing post programming steps 35*4882a593Smuzhiyun * write complete error = Error while doing post programming 36*4882a593Smuzhiyun * operating = FPGA is programmed and operating 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunWhat: /sys/class/fpga_manager/<fpga>/status 39*4882a593SmuzhiyunDate: June 2018 40*4882a593SmuzhiyunKernelVersion: 4.19 41*4882a593SmuzhiyunContact: Wu Hao <hao.wu@intel.com> 42*4882a593SmuzhiyunDescription: Read fpga manager status as a string. 43*4882a593Smuzhiyun If FPGA programming operation fails, it could be caused by crc 44*4882a593Smuzhiyun error or incompatible bitstream image. The intent of this 45*4882a593Smuzhiyun interface is to provide more detailed information for FPGA 46*4882a593Smuzhiyun programming errors to userspace. This is a list of strings for 47*4882a593Smuzhiyun the supported status. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun * reconfig operation error - invalid operations detected by 50*4882a593Smuzhiyun reconfiguration hardware. 51*4882a593Smuzhiyun e.g. start reconfiguration 52*4882a593Smuzhiyun with errors not cleared 53*4882a593Smuzhiyun * reconfig CRC error - CRC error detected by 54*4882a593Smuzhiyun reconfiguration hardware. 55*4882a593Smuzhiyun * reconfig incompatible image - reconfiguration image is 56*4882a593Smuzhiyun incompatible with hardware 57*4882a593Smuzhiyun * reconfig IP protocol error - protocol errors detected by 58*4882a593Smuzhiyun reconfiguration hardware 59*4882a593Smuzhiyun * reconfig fifo overflow error - FIFO overflow detected by 60*4882a593Smuzhiyun reconfiguration hardware 61