1*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pll2_feedback_clk_present 2*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pll2_reference_clk_present 3*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_a_present 4*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_b_present 5*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pll1_reference_clk_test_present 6*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/vcxo_clk_present 7*4882a593SmuzhiyunKernelVersion: 3.4.0 8*4882a593SmuzhiyunContact: linux-iio@vger.kernel.org 9*4882a593SmuzhiyunDescription: 10*4882a593Smuzhiyun Reading returns either '1' or '0'. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun '1' means that the clock in question is present. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun '0' means that the clock is missing. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/pllY_locked 17*4882a593SmuzhiyunKernelVersion: 3.4.0 18*4882a593SmuzhiyunContact: linux-iio@vger.kernel.org 19*4882a593SmuzhiyunDescription: 20*4882a593Smuzhiyun Reading returns either '1' or '0'. '1' means that the 21*4882a593Smuzhiyun pllY is locked. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunWhat: /sys/bus/iio/devices/iio:deviceX/sync_dividers 24*4882a593SmuzhiyunKernelVersion: 3.4.0 25*4882a593SmuzhiyunContact: linux-iio@vger.kernel.org 26*4882a593SmuzhiyunDescription: 27*4882a593Smuzhiyun Writing '1' triggers the clock distribution synchronization 28*4882a593Smuzhiyun functionality. All dividers are reset and the channels start 29*4882a593Smuzhiyun with their predefined phase offsets (out_altvoltageY_phase). 30*4882a593Smuzhiyun Writing this file has the effect as driving the external 31*4882a593Smuzhiyun /SYNC pin low. 32