1*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.funnel/funnel_ctrl 2*4882a593SmuzhiyunDate: November 2014 3*4882a593SmuzhiyunKernelVersion: 3.19 4*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 5*4882a593SmuzhiyunDescription: (RW) Enables the slave ports and defines the hold time of the 6*4882a593Smuzhiyun slave ports. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunWhat: /sys/bus/coresight/devices/<memory_map>.funnel/priority 9*4882a593SmuzhiyunDate: November 2014 10*4882a593SmuzhiyunKernelVersion: 3.19 11*4882a593SmuzhiyunContact: Mathieu Poirier <mathieu.poirier@linaro.org> 12*4882a593SmuzhiyunDescription: (RW) Defines input port priority order. 13