1*4882a593Smuzhiyun 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 1997,1998 The XFree86 Project, Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Loosely based on code bearing the following copyright: 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright 1990,91 by Thomas Roell, Dinkelscherben, Germany. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Author: Dirk Hohndel 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef _VGAHW_H 13*4882a593Smuzhiyun #define _VGAHW_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <X11/X.h> 16*4882a593Smuzhiyun #include "misc.h" 17*4882a593Smuzhiyun #include "input.h" 18*4882a593Smuzhiyun #include "scrnintstr.h" 19*4882a593Smuzhiyun #include "colormapst.h" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include "xf86str.h" 22*4882a593Smuzhiyun #include "xf86Pci.h" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #include "xf86DDC.h" 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include "globals.h" 27*4882a593Smuzhiyun #include <X11/extensions/dpmsconst.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun extern _X_EXPORT int vgaHWGetIndex(void); 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * access macro 33*4882a593Smuzhiyun */ 34*4882a593Smuzhiyun #define VGAHWPTR(p) ((vgaHWPtr)((p)->privates[vgaHWGetIndex()].ptr)) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* Standard VGA registers */ 37*4882a593Smuzhiyun #define VGA_ATTR_INDEX 0x3C0 38*4882a593Smuzhiyun #define VGA_ATTR_DATA_W 0x3C0 39*4882a593Smuzhiyun #define VGA_ATTR_DATA_R 0x3C1 40*4882a593Smuzhiyun #define VGA_IN_STAT_0 0x3C2 /* read */ 41*4882a593Smuzhiyun #define VGA_MISC_OUT_W 0x3C2 /* write */ 42*4882a593Smuzhiyun #define VGA_ENABLE 0x3C3 43*4882a593Smuzhiyun #define VGA_SEQ_INDEX 0x3C4 44*4882a593Smuzhiyun #define VGA_SEQ_DATA 0x3C5 45*4882a593Smuzhiyun #define VGA_DAC_MASK 0x3C6 46*4882a593Smuzhiyun #define VGA_DAC_READ_ADDR 0x3C7 47*4882a593Smuzhiyun #define VGA_DAC_WRITE_ADDR 0x3C8 48*4882a593Smuzhiyun #define VGA_DAC_DATA 0x3C9 49*4882a593Smuzhiyun #define VGA_FEATURE_R 0x3CA /* read */ 50*4882a593Smuzhiyun #define VGA_MISC_OUT_R 0x3CC /* read */ 51*4882a593Smuzhiyun #define VGA_GRAPH_INDEX 0x3CE 52*4882a593Smuzhiyun #define VGA_GRAPH_DATA 0x3CF 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define VGA_IOBASE_MONO 0x3B0 55*4882a593Smuzhiyun #define VGA_IOBASE_COLOR 0x3D0 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define VGA_CRTC_INDEX_OFFSET 0x04 58*4882a593Smuzhiyun #define VGA_CRTC_DATA_OFFSET 0x05 59*4882a593Smuzhiyun #define VGA_IN_STAT_1_OFFSET 0x0A /* read */ 60*4882a593Smuzhiyun #define VGA_FEATURE_W_OFFSET 0x0A /* write */ 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* default number of VGA registers stored internally */ 63*4882a593Smuzhiyun #define VGA_NUM_CRTC 25 64*4882a593Smuzhiyun #define VGA_NUM_SEQ 5 65*4882a593Smuzhiyun #define VGA_NUM_GFX 9 66*4882a593Smuzhiyun #define VGA_NUM_ATTR 21 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Flags for vgaHWSave() and vgaHWRestore() */ 69*4882a593Smuzhiyun #define VGA_SR_MODE 0x01 70*4882a593Smuzhiyun #define VGA_SR_FONTS 0x02 71*4882a593Smuzhiyun #define VGA_SR_CMAP 0x04 72*4882a593Smuzhiyun #define VGA_SR_ALL (VGA_SR_MODE | VGA_SR_FONTS | VGA_SR_CMAP) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Defaults for the VGA memory window */ 75*4882a593Smuzhiyun #define VGA_DEFAULT_PHYS_ADDR 0xA0000 76*4882a593Smuzhiyun #define VGA_DEFAULT_MEM_SIZE (64 * 1024) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * vgaRegRec contains settings of standard VGA registers. 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun typedef struct { 82*4882a593Smuzhiyun unsigned char MiscOutReg; /* */ 83*4882a593Smuzhiyun unsigned char *CRTC; /* Crtc Controller */ 84*4882a593Smuzhiyun unsigned char *Sequencer; /* Video Sequencer */ 85*4882a593Smuzhiyun unsigned char *Graphics; /* Video Graphics */ 86*4882a593Smuzhiyun unsigned char *Attribute; /* Video Atribute */ 87*4882a593Smuzhiyun unsigned char DAC[768]; /* Internal Colorlookuptable */ 88*4882a593Smuzhiyun unsigned char numCRTC; /* number of CRTC registers, def=VGA_NUM_CRTC */ 89*4882a593Smuzhiyun unsigned char numSequencer; /* number of seq registers, def=VGA_NUM_SEQ */ 90*4882a593Smuzhiyun unsigned char numGraphics; /* number of gfx registers, def=VGA_NUM_GFX */ 91*4882a593Smuzhiyun unsigned char numAttribute; /* number of attr registers, def=VGA_NUM_ATTR */ 92*4882a593Smuzhiyun } vgaRegRec, *vgaRegPtr; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun typedef struct _vgaHWRec *vgaHWPtr; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun typedef void (*vgaHWWriteIndexProcPtr) (vgaHWPtr hwp, CARD8 indx, CARD8 value); 97*4882a593Smuzhiyun typedef CARD8 (*vgaHWReadIndexProcPtr) (vgaHWPtr hwp, CARD8 indx); 98*4882a593Smuzhiyun typedef void (*vgaHWWriteProcPtr) (vgaHWPtr hwp, CARD8 value); 99*4882a593Smuzhiyun typedef CARD8 (*vgaHWReadProcPtr) (vgaHWPtr hwp); 100*4882a593Smuzhiyun typedef void (*vgaHWMiscProcPtr) (vgaHWPtr hwp); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * vgaHWRec contains per-screen information required by the vgahw module. 104*4882a593Smuzhiyun * 105*4882a593Smuzhiyun * Note, the palette referred to by the paletteEnabled, enablePalette and 106*4882a593Smuzhiyun * disablePalette is the 16-entry (+overscan) EGA-compatible palette accessed 107*4882a593Smuzhiyun * via the first 17 attribute registers and not the main 8-bit palette. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun typedef struct _vgaHWRec { 110*4882a593Smuzhiyun void *Base; /* Address of "VGA" memory */ 111*4882a593Smuzhiyun int MapSize; /* Size of "VGA" memory */ 112*4882a593Smuzhiyun unsigned long MapPhys; /* phys location of VGA mem */ 113*4882a593Smuzhiyun int IOBase; /* I/O Base address */ 114*4882a593Smuzhiyun CARD8 *MMIOBase; /* Pointer to MMIO start */ 115*4882a593Smuzhiyun int MMIOOffset; /* base + offset + vgareg 116*4882a593Smuzhiyun = mmioreg */ 117*4882a593Smuzhiyun void *FontInfo1; /* save area for fonts in 118*4882a593Smuzhiyun plane 2 */ 119*4882a593Smuzhiyun void *FontInfo2; /* save area for fonts in 120*4882a593Smuzhiyun plane 3 */ 121*4882a593Smuzhiyun void *TextInfo; /* save area for text */ 122*4882a593Smuzhiyun vgaRegRec SavedReg; /* saved registers */ 123*4882a593Smuzhiyun vgaRegRec ModeReg; /* register settings for 124*4882a593Smuzhiyun current mode */ 125*4882a593Smuzhiyun Bool ShowOverscan; 126*4882a593Smuzhiyun Bool paletteEnabled; 127*4882a593Smuzhiyun Bool cmapSaved; 128*4882a593Smuzhiyun ScrnInfoPtr pScrn; 129*4882a593Smuzhiyun vgaHWWriteIndexProcPtr writeCrtc; 130*4882a593Smuzhiyun vgaHWReadIndexProcPtr readCrtc; 131*4882a593Smuzhiyun vgaHWWriteIndexProcPtr writeGr; 132*4882a593Smuzhiyun vgaHWReadIndexProcPtr readGr; 133*4882a593Smuzhiyun vgaHWReadProcPtr readST00; 134*4882a593Smuzhiyun vgaHWReadProcPtr readST01; 135*4882a593Smuzhiyun vgaHWReadProcPtr readFCR; 136*4882a593Smuzhiyun vgaHWWriteProcPtr writeFCR; 137*4882a593Smuzhiyun vgaHWWriteIndexProcPtr writeAttr; 138*4882a593Smuzhiyun vgaHWReadIndexProcPtr readAttr; 139*4882a593Smuzhiyun vgaHWWriteIndexProcPtr writeSeq; 140*4882a593Smuzhiyun vgaHWReadIndexProcPtr readSeq; 141*4882a593Smuzhiyun vgaHWWriteProcPtr writeMiscOut; 142*4882a593Smuzhiyun vgaHWReadProcPtr readMiscOut; 143*4882a593Smuzhiyun vgaHWMiscProcPtr enablePalette; 144*4882a593Smuzhiyun vgaHWMiscProcPtr disablePalette; 145*4882a593Smuzhiyun vgaHWWriteProcPtr writeDacMask; 146*4882a593Smuzhiyun vgaHWReadProcPtr readDacMask; 147*4882a593Smuzhiyun vgaHWWriteProcPtr writeDacWriteAddr; 148*4882a593Smuzhiyun vgaHWWriteProcPtr writeDacReadAddr; 149*4882a593Smuzhiyun vgaHWWriteProcPtr writeDacData; 150*4882a593Smuzhiyun vgaHWReadProcPtr readDacData; 151*4882a593Smuzhiyun void *ddc; 152*4882a593Smuzhiyun struct pci_io_handle *io; 153*4882a593Smuzhiyun vgaHWReadProcPtr readEnable; 154*4882a593Smuzhiyun vgaHWWriteProcPtr writeEnable; 155*4882a593Smuzhiyun struct pci_device *dev; 156*4882a593Smuzhiyun } vgaHWRec; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* Some macros that VGA drivers can use in their ChipProbe() function */ 159*4882a593Smuzhiyun #define OVERSCAN 0x11 /* Index of OverScan register */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* Flags that define how overscan correction should take place */ 162*4882a593Smuzhiyun #define KGA_FIX_OVERSCAN 1 /* overcan correction required */ 163*4882a593Smuzhiyun #define KGA_ENABLE_ON_ZERO 2 /* if possible enable display at beginning */ 164*4882a593Smuzhiyun /* of next scanline/frame */ 165*4882a593Smuzhiyun #define KGA_BE_TOT_DEC 4 /* always fix problem by setting blank end */ 166*4882a593Smuzhiyun /* to total - 1 */ 167*4882a593Smuzhiyun #define BIT_PLANE 3 /* Which plane we write to in mono mode */ 168*4882a593Smuzhiyun #define BITS_PER_GUN 6 169*4882a593Smuzhiyun #define COLORMAP_SIZE 256 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define DACDelay(hw) \ 172*4882a593Smuzhiyun do { \ 173*4882a593Smuzhiyun (hw)->readST01((hw)); \ 174*4882a593Smuzhiyun (hw)->readST01((hw)); \ 175*4882a593Smuzhiyun } while (0) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun /* Function Prototypes */ 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* vgaHW.c */ 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun typedef void vgaHWProtectProc(ScrnInfoPtr, Bool); 182*4882a593Smuzhiyun typedef void vgaHWBlankScreenProc(ScrnInfoPtr, Bool); 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSetStdFuncs(vgaHWPtr hwp); 185*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSetMmioFuncs(vgaHWPtr hwp, CARD8 *base, int offset); 186*4882a593Smuzhiyun extern _X_EXPORT void vgaHWProtect(ScrnInfoPtr pScrn, Bool on); 187*4882a593Smuzhiyun extern _X_EXPORT vgaHWProtectProc *vgaHWProtectWeak(void); 188*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWSaveScreen(ScreenPtr pScreen, int mode); 189*4882a593Smuzhiyun extern _X_EXPORT void vgaHWBlankScreen(ScrnInfoPtr pScrn, Bool on); 190*4882a593Smuzhiyun extern _X_EXPORT vgaHWBlankScreenProc *vgaHWBlankScreenWeak(void); 191*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSeqReset(vgaHWPtr hwp, Bool start); 192*4882a593Smuzhiyun extern _X_EXPORT void vgaHWRestoreFonts(ScrnInfoPtr scrninfp, 193*4882a593Smuzhiyun vgaRegPtr restore); 194*4882a593Smuzhiyun extern _X_EXPORT void vgaHWRestoreMode(ScrnInfoPtr scrninfp, vgaRegPtr restore); 195*4882a593Smuzhiyun extern _X_EXPORT void vgaHWRestoreColormap(ScrnInfoPtr scrninfp, 196*4882a593Smuzhiyun vgaRegPtr restore); 197*4882a593Smuzhiyun extern _X_EXPORT void vgaHWRestore(ScrnInfoPtr scrninfp, vgaRegPtr restore, 198*4882a593Smuzhiyun int flags); 199*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSaveFonts(ScrnInfoPtr scrninfp, vgaRegPtr save); 200*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSaveMode(ScrnInfoPtr scrninfp, vgaRegPtr save); 201*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSaveColormap(ScrnInfoPtr scrninfp, vgaRegPtr save); 202*4882a593Smuzhiyun extern _X_EXPORT void vgaHWSave(ScrnInfoPtr scrninfp, vgaRegPtr save, 203*4882a593Smuzhiyun int flags); 204*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWInit(ScrnInfoPtr scrnp, DisplayModePtr mode); 205*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWSetRegCounts(ScrnInfoPtr scrp, int numCRTC, 206*4882a593Smuzhiyun int numSequencer, int numGraphics, 207*4882a593Smuzhiyun int numAttribute); 208*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWCopyReg(vgaRegPtr dst, vgaRegPtr src); 209*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWGetHWRec(ScrnInfoPtr scrp); 210*4882a593Smuzhiyun extern _X_EXPORT void vgaHWFreeHWRec(ScrnInfoPtr scrp); 211*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWMapMem(ScrnInfoPtr scrp); 212*4882a593Smuzhiyun extern _X_EXPORT void vgaHWUnmapMem(ScrnInfoPtr scrp); 213*4882a593Smuzhiyun extern _X_EXPORT void vgaHWGetIOBase(vgaHWPtr hwp); 214*4882a593Smuzhiyun extern _X_EXPORT void vgaHWLock(vgaHWPtr hwp); 215*4882a593Smuzhiyun extern _X_EXPORT void vgaHWUnlock(vgaHWPtr hwp); 216*4882a593Smuzhiyun extern _X_EXPORT void vgaHWEnable(vgaHWPtr hwp); 217*4882a593Smuzhiyun extern _X_EXPORT void vgaHWDisable(vgaHWPtr hwp); 218*4882a593Smuzhiyun extern _X_EXPORT void vgaHWDPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, 219*4882a593Smuzhiyun int flags); 220*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWHandleColormaps(ScreenPtr pScreen); 221*4882a593Smuzhiyun extern _X_EXPORT void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed); 222*4882a593Smuzhiyun extern _X_EXPORT CARD32 vgaHWHBlankKGA(DisplayModePtr mode, vgaRegPtr regp, 223*4882a593Smuzhiyun int nBits, unsigned int Flags); 224*4882a593Smuzhiyun extern _X_EXPORT CARD32 vgaHWVBlankKGA(DisplayModePtr mode, vgaRegPtr regp, 225*4882a593Smuzhiyun int nBits, unsigned int Flags); 226*4882a593Smuzhiyun extern _X_EXPORT Bool vgaHWAllocDefaultRegs(vgaRegPtr regp); 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun extern _X_EXPORT DDC1SetSpeedProc vgaHWddc1SetSpeedWeak(void); 229*4882a593Smuzhiyun extern _X_EXPORT SaveScreenProcPtr vgaHWSaveScreenWeak(void); 230*4882a593Smuzhiyun extern _X_EXPORT void xf86GetClocks(ScrnInfoPtr pScrn, int num, 231*4882a593Smuzhiyun Bool (*ClockFunc) (ScrnInfoPtr, int), 232*4882a593Smuzhiyun void (*ProtectRegs) (ScrnInfoPtr, Bool), 233*4882a593Smuzhiyun void (*BlankScreen) (ScrnInfoPtr, Bool), 234*4882a593Smuzhiyun unsigned long vertsyncreg, int maskval, 235*4882a593Smuzhiyun int knownclkindex, int knownclkvalue); 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun #endif /* _VGAHW_H */ 238