1*4882a593Smuzhiyun 2*4882a593Smuzhiyun #include <xf86RamDac.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun extern _X_EXPORT unsigned long TIramdacCalculateMNPForClock(unsigned long 5*4882a593Smuzhiyun RefClock, 6*4882a593Smuzhiyun unsigned long 7*4882a593Smuzhiyun ReqClock, 8*4882a593Smuzhiyun char IsPixClock, 9*4882a593Smuzhiyun unsigned long 10*4882a593Smuzhiyun MinClock, 11*4882a593Smuzhiyun unsigned long 12*4882a593Smuzhiyun MaxClock, 13*4882a593Smuzhiyun unsigned long *rM, 14*4882a593Smuzhiyun unsigned long *rN, 15*4882a593Smuzhiyun unsigned long *rP); 16*4882a593Smuzhiyun extern _X_EXPORT RamDacHelperRecPtr TIramdacProbe(ScrnInfoPtr pScrn, 17*4882a593Smuzhiyun RamDacSupportedInfoRecPtr 18*4882a593Smuzhiyun ramdacs); 19*4882a593Smuzhiyun extern _X_EXPORT void TIramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, 20*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 21*4882a593Smuzhiyun extern _X_EXPORT void TIramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, 22*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 23*4882a593Smuzhiyun extern _X_EXPORT void TIramdac3026SetBpp(ScrnInfoPtr pScrn, 24*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 25*4882a593Smuzhiyun extern _X_EXPORT void TIramdac3030SetBpp(ScrnInfoPtr pScrn, 26*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 27*4882a593Smuzhiyun extern _X_EXPORT void TIramdacHWCursorInit(xf86CursorInfoPtr infoPtr); 28*4882a593Smuzhiyun extern _X_EXPORT void TIramdacLoadPalette(ScrnInfoPtr pScrn, int numColors, 29*4882a593Smuzhiyun int *indices, LOCO * colors, 30*4882a593Smuzhiyun VisualPtr pVisual); 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun typedef void TIramdacLoadPaletteProc(ScrnInfoPtr, int, int *, LOCO *, 33*4882a593Smuzhiyun VisualPtr); 34*4882a593Smuzhiyun extern _X_EXPORT TIramdacLoadPaletteProc *TIramdacLoadPaletteWeak(void); 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define TI3030_RAMDAC (VENDOR_TI << 16) | 0x00 37*4882a593Smuzhiyun #define TI3026_RAMDAC (VENDOR_TI << 16) | 0x01 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * TI Ramdac registers 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define TIDAC_rev 0x01 44*4882a593Smuzhiyun #define TIDAC_ind_curs_ctrl 0x06 45*4882a593Smuzhiyun #define TIDAC_byte_router_ctrl 0x07 46*4882a593Smuzhiyun #define TIDAC_latch_ctrl 0x0f 47*4882a593Smuzhiyun #define TIDAC_true_color_ctrl 0x18 48*4882a593Smuzhiyun #define TIDAC_multiplex_ctrl 0x19 49*4882a593Smuzhiyun #define TIDAC_clock_select 0x1a 50*4882a593Smuzhiyun #define TIDAC_palette_page 0x1c 51*4882a593Smuzhiyun #define TIDAC_general_ctrl 0x1d 52*4882a593Smuzhiyun #define TIDAC_misc_ctrl 0x1e 53*4882a593Smuzhiyun #define TIDAC_pll_addr 0x2c 54*4882a593Smuzhiyun #define TIDAC_pll_pixel_data 0x2d 55*4882a593Smuzhiyun #define TIDAC_pll_memory_data 0x2e 56*4882a593Smuzhiyun #define TIDAC_pll_loop_data 0x2f 57*4882a593Smuzhiyun #define TIDAC_key_over_low 0x30 58*4882a593Smuzhiyun #define TIDAC_key_over_high 0x31 59*4882a593Smuzhiyun #define TIDAC_key_red_low 0x32 60*4882a593Smuzhiyun #define TIDAC_key_red_high 0x33 61*4882a593Smuzhiyun #define TIDAC_key_green_low 0x34 62*4882a593Smuzhiyun #define TIDAC_key_green_high 0x35 63*4882a593Smuzhiyun #define TIDAC_key_blue_low 0x36 64*4882a593Smuzhiyun #define TIDAC_key_blue_high 0x37 65*4882a593Smuzhiyun #define TIDAC_key_ctrl 0x38 66*4882a593Smuzhiyun #define TIDAC_clock_ctrl 0x39 67*4882a593Smuzhiyun #define TIDAC_sense_test 0x3a 68*4882a593Smuzhiyun #define TIDAC_test_mode_data 0x3b 69*4882a593Smuzhiyun #define TIDAC_crc_remain_lsb 0x3c 70*4882a593Smuzhiyun #define TIDAC_crc_remain_msb 0x3d 71*4882a593Smuzhiyun #define TIDAC_crc_bit_select 0x3e 72*4882a593Smuzhiyun #define TIDAC_id 0x3f 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* These are pll values that are accessed via TIDAC_pll_pixel_data */ 75*4882a593Smuzhiyun #define TIDAC_PIXEL_N 0x80 76*4882a593Smuzhiyun #define TIDAC_PIXEL_M 0x81 77*4882a593Smuzhiyun #define TIDAC_PIXEL_P 0x82 78*4882a593Smuzhiyun #define TIDAC_PIXEL_VALID 0x83 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* These are pll values that are accessed via TIDAC_pll_loop_data */ 81*4882a593Smuzhiyun #define TIDAC_LOOP_N 0x90 82*4882a593Smuzhiyun #define TIDAC_LOOP_M 0x91 83*4882a593Smuzhiyun #define TIDAC_LOOP_P 0x92 84*4882a593Smuzhiyun #define TIDAC_LOOP_VALID 0x93 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Direct mapping addresses */ 87*4882a593Smuzhiyun #define TIDAC_INDEX 0xa0 88*4882a593Smuzhiyun #define TIDAC_PALETTE_DATA 0xa1 89*4882a593Smuzhiyun #define TIDAC_READ_MASK 0xa2 90*4882a593Smuzhiyun #define TIDAC_READ_ADDR 0xa3 91*4882a593Smuzhiyun #define TIDAC_CURS_WRITE_ADDR 0xa4 92*4882a593Smuzhiyun #define TIDAC_CURS_COLOR 0xa5 93*4882a593Smuzhiyun #define TIDAC_CURS_READ_ADDR 0xa7 94*4882a593Smuzhiyun #define TIDAC_CURS_CTL 0xa9 95*4882a593Smuzhiyun #define TIDAC_INDEXED_DATA 0xaa 96*4882a593Smuzhiyun #define TIDAC_CURS_RAM_DATA 0xab 97*4882a593Smuzhiyun #define TIDAC_CURS_XLOW 0xac 98*4882a593Smuzhiyun #define TIDAC_CURS_XHIGH 0xad 99*4882a593Smuzhiyun #define TIDAC_CURS_YLOW 0xae 100*4882a593Smuzhiyun #define TIDAC_CURS_YHIGH 0xaf 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define TIDAC_sw_reset 0xff 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Constants */ 105*4882a593Smuzhiyun #define TIDAC_TVP_3026_ID 0x26 106*4882a593Smuzhiyun #define TIDAC_TVP_3030_ID 0x30 107