1*4882a593Smuzhiyun 2*4882a593Smuzhiyun #include <xf86RamDac.h> 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun extern _X_EXPORT RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn, 5*4882a593Smuzhiyun RamDacSupportedInfoRecPtr 6*4882a593Smuzhiyun ramdacs); 7*4882a593Smuzhiyun extern _X_EXPORT void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, 8*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 9*4882a593Smuzhiyun extern _X_EXPORT void IBMramdacRestore(ScrnInfoPtr pScrn, 10*4882a593Smuzhiyun RamDacRecPtr RamDacRec, 11*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 12*4882a593Smuzhiyun extern _X_EXPORT void IBMramdac526SetBpp(ScrnInfoPtr pScrn, 13*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 14*4882a593Smuzhiyun extern _X_EXPORT void IBMramdac640SetBpp(ScrnInfoPtr pScrn, 15*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 16*4882a593Smuzhiyun extern _X_EXPORT unsigned long IBMramdac526CalculateMNPCForClock(unsigned long 17*4882a593Smuzhiyun RefClock, 18*4882a593Smuzhiyun unsigned long 19*4882a593Smuzhiyun ReqClock, 20*4882a593Smuzhiyun char 21*4882a593Smuzhiyun IsPixClock, 22*4882a593Smuzhiyun unsigned long 23*4882a593Smuzhiyun MinClock, 24*4882a593Smuzhiyun unsigned long 25*4882a593Smuzhiyun MaxClock, 26*4882a593Smuzhiyun unsigned long 27*4882a593Smuzhiyun *rM, 28*4882a593Smuzhiyun unsigned long 29*4882a593Smuzhiyun *rN, 30*4882a593Smuzhiyun unsigned long 31*4882a593Smuzhiyun *rP, 32*4882a593Smuzhiyun unsigned long 33*4882a593Smuzhiyun *rC); 34*4882a593Smuzhiyun extern _X_EXPORT unsigned long IBMramdac640CalculateMNPCForClock(unsigned long 35*4882a593Smuzhiyun RefClock, 36*4882a593Smuzhiyun unsigned long 37*4882a593Smuzhiyun ReqClock, 38*4882a593Smuzhiyun char 39*4882a593Smuzhiyun IsPixClock, 40*4882a593Smuzhiyun unsigned long 41*4882a593Smuzhiyun MinClock, 42*4882a593Smuzhiyun unsigned long 43*4882a593Smuzhiyun MaxClock, 44*4882a593Smuzhiyun unsigned long 45*4882a593Smuzhiyun *rM, 46*4882a593Smuzhiyun unsigned long 47*4882a593Smuzhiyun *rN, 48*4882a593Smuzhiyun unsigned long 49*4882a593Smuzhiyun *rP, 50*4882a593Smuzhiyun unsigned long 51*4882a593Smuzhiyun *rC); 52*4882a593Smuzhiyun extern _X_EXPORT void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr); 53*4882a593Smuzhiyun extern _X_EXPORT void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun typedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr); 56*4882a593Smuzhiyun extern _X_EXPORT IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define IBM524_RAMDAC ((VENDOR_IBM << 16) | 0x00) 59*4882a593Smuzhiyun #define IBM524A_RAMDAC ((VENDOR_IBM << 16) | 0x01) 60*4882a593Smuzhiyun #define IBM525_RAMDAC ((VENDOR_IBM << 16) | 0x02) 61*4882a593Smuzhiyun #define IBM526_RAMDAC ((VENDOR_IBM << 16) | 0x03) 62*4882a593Smuzhiyun #define IBM526DB_RAMDAC ((VENDOR_IBM << 16) | 0x04) 63*4882a593Smuzhiyun #define IBM528_RAMDAC ((VENDOR_IBM << 16) | 0x05) 64*4882a593Smuzhiyun #define IBM528A_RAMDAC ((VENDOR_IBM << 16) | 0x06) 65*4882a593Smuzhiyun #define IBM624_RAMDAC ((VENDOR_IBM << 16) | 0x07) 66*4882a593Smuzhiyun #define IBM624DB_RAMDAC ((VENDOR_IBM << 16) | 0x08) 67*4882a593Smuzhiyun #define IBM640_RAMDAC ((VENDOR_IBM << 16) | 0x09) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* 70*4882a593Smuzhiyun * IBM Ramdac registers 71*4882a593Smuzhiyun */ 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define IBMRGB_REF_FREQ_1 14.31818 74*4882a593Smuzhiyun #define IBMRGB_REF_FREQ_2 50.00000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define IBMRGB_rev 0x00 77*4882a593Smuzhiyun #define IBMRGB_id 0x01 78*4882a593Smuzhiyun #define IBMRGB_misc_clock 0x02 79*4882a593Smuzhiyun #define IBMRGB_sync 0x03 80*4882a593Smuzhiyun #define IBMRGB_hsync_pos 0x04 81*4882a593Smuzhiyun #define IBMRGB_pwr_mgmt 0x05 82*4882a593Smuzhiyun #define IBMRGB_dac_op 0x06 83*4882a593Smuzhiyun #define IBMRGB_pal_ctrl 0x07 84*4882a593Smuzhiyun #define IBMRGB_sysclk 0x08 /* not RGB525 */ 85*4882a593Smuzhiyun #define IBMRGB_pix_fmt 0x0a 86*4882a593Smuzhiyun #define IBMRGB_8bpp 0x0b 87*4882a593Smuzhiyun #define IBMRGB_16bpp 0x0c 88*4882a593Smuzhiyun #define IBMRGB_24bpp 0x0d 89*4882a593Smuzhiyun #define IBMRGB_32bpp 0x0e 90*4882a593Smuzhiyun #define IBMRGB_pll_ctrl1 0x10 91*4882a593Smuzhiyun #define IBMRGB_pll_ctrl2 0x11 92*4882a593Smuzhiyun #define IBMRGB_pll_ref_div_fix 0x14 93*4882a593Smuzhiyun #define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */ 94*4882a593Smuzhiyun #define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */ 95*4882a593Smuzhiyun /* #define IBMRGB_f0 0x20 */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define IBMRGB_sysclk_n 0x15 98*4882a593Smuzhiyun #define IBMRGB_sysclk_m 0x16 99*4882a593Smuzhiyun #define IBMRGB_sysclk_p 0x17 100*4882a593Smuzhiyun #define IBMRGB_sysclk_c 0x18 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define IBMRGB_m0 0x20 103*4882a593Smuzhiyun #define IBMRGB_n0 0x21 104*4882a593Smuzhiyun #define IBMRGB_p0 0x22 105*4882a593Smuzhiyun #define IBMRGB_c0 0x23 106*4882a593Smuzhiyun #define IBMRGB_m1 0x24 107*4882a593Smuzhiyun #define IBMRGB_n1 0x25 108*4882a593Smuzhiyun #define IBMRGB_p1 0x26 109*4882a593Smuzhiyun #define IBMRGB_c1 0x27 110*4882a593Smuzhiyun #define IBMRGB_m2 0x28 111*4882a593Smuzhiyun #define IBMRGB_n2 0x29 112*4882a593Smuzhiyun #define IBMRGB_p2 0x2a 113*4882a593Smuzhiyun #define IBMRGB_c2 0x2b 114*4882a593Smuzhiyun #define IBMRGB_m3 0x2c 115*4882a593Smuzhiyun #define IBMRGB_n3 0x2d 116*4882a593Smuzhiyun #define IBMRGB_p3 0x2e 117*4882a593Smuzhiyun #define IBMRGB_c3 0x2f 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define IBMRGB_curs 0x30 120*4882a593Smuzhiyun #define IBMRGB_curs_xl 0x31 121*4882a593Smuzhiyun #define IBMRGB_curs_xh 0x32 122*4882a593Smuzhiyun #define IBMRGB_curs_yl 0x33 123*4882a593Smuzhiyun #define IBMRGB_curs_yh 0x34 124*4882a593Smuzhiyun #define IBMRGB_curs_hot_x 0x35 125*4882a593Smuzhiyun #define IBMRGB_curs_hot_y 0x36 126*4882a593Smuzhiyun #define IBMRGB_curs_col1_r 0x40 127*4882a593Smuzhiyun #define IBMRGB_curs_col1_g 0x41 128*4882a593Smuzhiyun #define IBMRGB_curs_col1_b 0x42 129*4882a593Smuzhiyun #define IBMRGB_curs_col2_r 0x43 130*4882a593Smuzhiyun #define IBMRGB_curs_col2_g 0x44 131*4882a593Smuzhiyun #define IBMRGB_curs_col2_b 0x45 132*4882a593Smuzhiyun #define IBMRGB_curs_col3_r 0x46 133*4882a593Smuzhiyun #define IBMRGB_curs_col3_g 0x47 134*4882a593Smuzhiyun #define IBMRGB_curs_col3_b 0x48 135*4882a593Smuzhiyun #define IBMRGB_border_col_r 0x60 136*4882a593Smuzhiyun #define IBMRGB_border_col_g 0x61 137*4882a593Smuzhiyun #define IBMRGB_botder_col_b 0x62 138*4882a593Smuzhiyun #define IBMRGB_key 0x68 139*4882a593Smuzhiyun #define IBMRGB_key_mask 0x6C 140*4882a593Smuzhiyun #define IBMRGB_misc1 0x70 141*4882a593Smuzhiyun #define IBMRGB_misc2 0x71 142*4882a593Smuzhiyun #define IBMRGB_misc3 0x72 143*4882a593Smuzhiyun #define IBMRGB_misc4 0x73 /* not RGB525 */ 144*4882a593Smuzhiyun #define IBMRGB_key_control 0x78 145*4882a593Smuzhiyun #define IBMRGB_dac_sense 0x82 146*4882a593Smuzhiyun #define IBMRGB_misr_r 0x84 147*4882a593Smuzhiyun #define IBMRGB_misr_g 0x86 148*4882a593Smuzhiyun #define IBMRGB_misr_b 0x88 149*4882a593Smuzhiyun #define IBMRGB_pll_vco_div_in 0x8e 150*4882a593Smuzhiyun #define IBMRGB_pll_ref_div_in 0x8f 151*4882a593Smuzhiyun #define IBMRGB_vram_mask_0 0x90 152*4882a593Smuzhiyun #define IBMRGB_vram_mask_1 0x91 153*4882a593Smuzhiyun #define IBMRGB_vram_mask_2 0x92 154*4882a593Smuzhiyun #define IBMRGB_vram_mask_3 0x93 155*4882a593Smuzhiyun #define IBMRGB_curs_array 0x100 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* Constants rgb525.h */ 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* RGB525_REVISION_LEVEL */ 160*4882a593Smuzhiyun #define RGB525_PRODUCT_REV_LEVEL 0xf0 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun /* RGB525_ID */ 163*4882a593Smuzhiyun #define RGB525_PRODUCT_ID 0x01 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun /* RGB525_MISC_CTRL_1 */ 166*4882a593Smuzhiyun #define MISR_CNTL_ENABLE 0x80 167*4882a593Smuzhiyun #define VMSK_CNTL_ENABLE 0x40 168*4882a593Smuzhiyun #define PADR_RDMT_RDADDR 0x0 169*4882a593Smuzhiyun #define PADR_RDMT_PAL_STATE 0x20 170*4882a593Smuzhiyun #define SENS_DSAB_DISABLE 0x10 171*4882a593Smuzhiyun #define SENS_SEL_BIT3 0x0 172*4882a593Smuzhiyun #define SENS_SEL_BIT7 0x08 173*4882a593Smuzhiyun #define VRAM_SIZE_32 0x0 174*4882a593Smuzhiyun #define VRAM_SIZE_64 0x01 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* RGB525_MISC_CTRL_2 */ 177*4882a593Smuzhiyun #define PCLK_SEL_LCLK 0x0 178*4882a593Smuzhiyun #define PCLK_SEL_PLL 0x40 179*4882a593Smuzhiyun #define PCLK_SEL_EXT 0x80 180*4882a593Smuzhiyun #define INTL_MODE_ENABLE 0x20 181*4882a593Smuzhiyun #define BLANK_CNTL_ENABLE 0x10 182*4882a593Smuzhiyun #define COL_RES_6BIT 0x0 183*4882a593Smuzhiyun #define COL_RES_8BIT 0x04 184*4882a593Smuzhiyun #define PORT_SEL_VGA 0x0 185*4882a593Smuzhiyun #define PORT_SEL_VRAM 0x01 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun /* RGB525_MISC_CTRL_3 */ 188*4882a593Smuzhiyun #define SWAP_RB 0x80 189*4882a593Smuzhiyun #define SWAP_WORD_LOHI 0x0 190*4882a593Smuzhiyun #define SWAP_WORD_HILO 0x10 191*4882a593Smuzhiyun #define SWAP_NIB_HILO 0x0 192*4882a593Smuzhiyun #define SWAP_NIB_LOHI 0x02 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* RGB525_MISC_CLK_CTRL */ 195*4882a593Smuzhiyun #define DDOT_CLK_ENABLE 0x0 196*4882a593Smuzhiyun #define DDOT_CLK_DISABLE 0x80 197*4882a593Smuzhiyun #define SCLK_ENABLE 0x0 198*4882a593Smuzhiyun #define SCLK_DISABLE 0x40 199*4882a593Smuzhiyun #define B24P_DDOT_PLL 0x0 200*4882a593Smuzhiyun #define B24P_DDOT_SCLK 0x20 201*4882a593Smuzhiyun #define DDOT_DIV_PLL_1 0x0 202*4882a593Smuzhiyun #define DDOT_DIV_PLL_2 0x02 203*4882a593Smuzhiyun #define DDOT_DIV_PLL_4 0x04 204*4882a593Smuzhiyun #define DDOT_DIV_PLL_8 0x06 205*4882a593Smuzhiyun #define DDOT_DIV_PLL_16 0x08 206*4882a593Smuzhiyun #define PLL_DISABLE 0x0 207*4882a593Smuzhiyun #define PLL_ENABLE 0x01 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* RGB525_SYNC_CTRL */ 210*4882a593Smuzhiyun #define DLY_CNTL_ADD 0x0 211*4882a593Smuzhiyun #define DLY_SYNC_NOADD 0x80 212*4882a593Smuzhiyun #define CSYN_INVT_DISABLE 0x0 213*4882a593Smuzhiyun #define CSYN_INVT_ENABLE 0x40 214*4882a593Smuzhiyun #define VSYN_INVT_DISABLE 0x0 215*4882a593Smuzhiyun #define VSYN_INVT_ENABLE 0x20 216*4882a593Smuzhiyun #define HSYN_INVT_DISABLE 0x0 217*4882a593Smuzhiyun #define HSYN_INVT_ENABLE 0x10 218*4882a593Smuzhiyun #define VSYN_CNTL_NORMAL 0x0 219*4882a593Smuzhiyun #define VSYN_CNTL_HIGH 0x04 220*4882a593Smuzhiyun #define VSYN_CNTL_LOW 0x08 221*4882a593Smuzhiyun #define VSYN_CNTL_DISABLE 0x0C 222*4882a593Smuzhiyun #define HSYN_CNTL_NORMAL 0x0 223*4882a593Smuzhiyun #define HSYN_CNTL_HIGH 0x01 224*4882a593Smuzhiyun #define HSYN_CNTL_LOW 0x02 225*4882a593Smuzhiyun #define HSYN_CNTL_DISABLE 0x03 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* RGB525_HSYNC_CTRL */ 228*4882a593Smuzhiyun #define HSYN_POS(n) (n) 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* RGB525_POWER_MANAGEMENT */ 231*4882a593Smuzhiyun #define SCLK_PWR_NORMAL 0x0 232*4882a593Smuzhiyun #define SCLK_PWR_DISABLE 0x10 233*4882a593Smuzhiyun #define DDOT_PWR_NORMAL 0x0 234*4882a593Smuzhiyun #define DDOT_PWR_DISABLE 0x08 235*4882a593Smuzhiyun #define SYNC_PWR_NORMAL 0x0 236*4882a593Smuzhiyun #define SYNC_PWR_DISABLE 0x04 237*4882a593Smuzhiyun #define ICLK_PWR_NORMAL 0x0 238*4882a593Smuzhiyun #define ICLK_PWR_DISABLE 0x02 239*4882a593Smuzhiyun #define DAC_PWR_NORMAL 0x0 240*4882a593Smuzhiyun #define DAC_PWR_DISABLE 0x01 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun /* RGB525_DAC_OPERATION */ 243*4882a593Smuzhiyun #define SOG_DISABLE 0x0 244*4882a593Smuzhiyun #define SOG_ENABLE 0x08 245*4882a593Smuzhiyun #define BRB_NORMAL 0x0 246*4882a593Smuzhiyun #define BRB_ALWAYS 0x04 247*4882a593Smuzhiyun #define DSR_DAC_SLOW 0x02 248*4882a593Smuzhiyun #define DSR_DAC_FAST 0x0 249*4882a593Smuzhiyun #define DPE_DISABLE 0x0 250*4882a593Smuzhiyun #define DPE_ENABLE 0x01 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* RGB525_PALETTE_CTRL */ 253*4882a593Smuzhiyun #define SIXBIT_LINEAR_ENABLE 0x0 254*4882a593Smuzhiyun #define SIXBIT_LINEAR_DISABLE 0x80 255*4882a593Smuzhiyun #define PALETTE_PARITION(n) (n) 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /* RGB525_PIXEL_FORMAT */ 258*4882a593Smuzhiyun #define PIXEL_FORMAT_4BPP 0x02 259*4882a593Smuzhiyun #define PIXEL_FORMAT_8BPP 0x03 260*4882a593Smuzhiyun #define PIXEL_FORMAT_16BPP 0x04 261*4882a593Smuzhiyun #define PIXEL_FORMAT_24BPP 0x05 262*4882a593Smuzhiyun #define PIXEL_FORMAT_32BPP 0x06 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun /* RGB525_8BPP_CTRL */ 265*4882a593Smuzhiyun #define B8_DCOL_INDIRECT 0x0 266*4882a593Smuzhiyun #define B8_DCOL_DIRECT 0x01 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun /* RGB525_16BPP_CTRL */ 269*4882a593Smuzhiyun #define B16_DCOL_INDIRECT 0x0 270*4882a593Smuzhiyun #define B16_DCOL_DYNAMIC 0x40 271*4882a593Smuzhiyun #define B16_DCOL_DIRECT 0xC0 272*4882a593Smuzhiyun #define B16_POL_FORCE_BYPASS 0x0 273*4882a593Smuzhiyun #define B16_POL_FORCE_LOOKUP 0x20 274*4882a593Smuzhiyun #define B16_ZIB 0x0 275*4882a593Smuzhiyun #define B16_LINEAR 0x04 276*4882a593Smuzhiyun #define B16_555 0x0 277*4882a593Smuzhiyun #define B16_565 0x02 278*4882a593Smuzhiyun #define B16_SPARSE 0x0 279*4882a593Smuzhiyun #define B16_CONTIGUOUS 0x01 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* RGB525_24BPP_CTRL */ 282*4882a593Smuzhiyun #define B24_DCOL_INDIRECT 0x0 283*4882a593Smuzhiyun #define B24_DCOL_DIRECT 0x01 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /* RGB525_32BPP_CTRL */ 286*4882a593Smuzhiyun #define B32_POL_FORCE_BYPASS 0x0 287*4882a593Smuzhiyun #define B32_POL_FORCE_LOOKUP 0x04 288*4882a593Smuzhiyun #define B32_DCOL_INDIRECT 0x0 289*4882a593Smuzhiyun #define B32_DCOL_DYNAMIC 0x01 290*4882a593Smuzhiyun #define B32_DCOL_DIRECT 0x03 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun /* RGB525_PLL_CTRL_1 */ 293*4882a593Smuzhiyun #define REF_SRC_REFCLK 0x0 294*4882a593Smuzhiyun #define REF_SRC_EXTCLK 0x10 295*4882a593Smuzhiyun #define PLL_EXT_FS_3_0 0x0 296*4882a593Smuzhiyun #define PLL_EXT_FS_2_0 0x01 297*4882a593Smuzhiyun #define PLL_CNTL2_3_0 0x02 298*4882a593Smuzhiyun #define PLL_CNTL2_2_0 0x03 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun /* RGB525_PLL_CTRL_2 */ 301*4882a593Smuzhiyun #define PLL_INT_FS_3_0(n) (n) 302*4882a593Smuzhiyun #define PLL_INT_FS_2_0(n) (n) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun /* RGB525_PLL_REF_DIV_COUNT */ 305*4882a593Smuzhiyun #define REF_DIV_COUNT(n) (n) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* RGB525_F0 - RGB525_F15 */ 308*4882a593Smuzhiyun #define VCO_DIV_COUNT(n) (n) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* RGB525_PLL_REFCLK values */ 311*4882a593Smuzhiyun #define RGB525_PLL_REFCLK_MHz(n) ((n)/2) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun /* RGB525_CURSOR_CONTROL */ 314*4882a593Smuzhiyun #define SMLC_PART_0 0x0 315*4882a593Smuzhiyun #define SMLC_PART_1 0x40 316*4882a593Smuzhiyun #define SMLC_PART_2 0x80 317*4882a593Smuzhiyun #define SMLC_PART_3 0xC0 318*4882a593Smuzhiyun #define PIX_ORDER_RL 0x0 319*4882a593Smuzhiyun #define PIX_ORDER_LR 0x20 320*4882a593Smuzhiyun #define LOC_READ_LAST 0x0 321*4882a593Smuzhiyun #define LOC_READ_ACTUAL 0x10 322*4882a593Smuzhiyun #define UPDT_CNTL_DELAYED 0x0 323*4882a593Smuzhiyun #define UPDT_CNTL_IMMEDIATE 0x08 324*4882a593Smuzhiyun #define CURSOR_SIZE_32 0x0 325*4882a593Smuzhiyun #define CURSOR_SIZE_64 0x40 326*4882a593Smuzhiyun #define CURSOR_MODE_OFF 0x0 327*4882a593Smuzhiyun #define CURSOR_MODE_3_COLOR 0x01 328*4882a593Smuzhiyun #define CURSOR_MODE_2_COLOR_HL 0x02 329*4882a593Smuzhiyun #define CURSOR_MODE_2_COLOR 0x03 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* RGB525_REVISION_LEVEL */ 332*4882a593Smuzhiyun #define REVISION_LEVEL 0xF0 /* predefined */ 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun /* RGB525_ID */ 335*4882a593Smuzhiyun #define ID_CODE 0x01 /* predefined */ 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun /* MISR status */ 338*4882a593Smuzhiyun #define RGB525_MISR_DONE 0x01 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun /* the IBMRGB640 is rather different from the rest of the RAMDACs, 341*4882a593Smuzhiyun so we define a completely new set of register names for it */ 342*4882a593Smuzhiyun #define RGB640_SER_07_00 0x02 343*4882a593Smuzhiyun #define RGB640_SER_15_08 0x03 344*4882a593Smuzhiyun #define RGB640_SER_23_16 0x04 345*4882a593Smuzhiyun #define RGB640_SER_31_24 0x05 346*4882a593Smuzhiyun #define RGB640_SER_WID_03_00 0x06 347*4882a593Smuzhiyun #define RGB640_SER_WID_07_04 0x07 348*4882a593Smuzhiyun #define RGB640_SER_MODE 0x08 349*4882a593Smuzhiyun #define IBM640_SER_2_1 0x00 350*4882a593Smuzhiyun #define IBM640_SER_4_1 0x01 351*4882a593Smuzhiyun #define IBM640_SER_8_1 0x02 352*4882a593Smuzhiyun #define IBM640_SER_16_1 0x03 353*4882a593Smuzhiyun #define IBM640_SER_16_3 0x05 354*4882a593Smuzhiyun #define IBM640_SER_5_1 0x06 355*4882a593Smuzhiyun #define RGB640_PIXEL_INTERLEAVE 0x09 356*4882a593Smuzhiyun #define RGB640_MISC_CONF 0x0a 357*4882a593Smuzhiyun #define IBM640_PCLK 0x00 358*4882a593Smuzhiyun #define IBM640_PCLK_2 0x40 359*4882a593Smuzhiyun #define IBM640_PCLK_4 0x80 360*4882a593Smuzhiyun #define IBM640_PCLK_8 0xc0 361*4882a593Smuzhiyun #define IBM640_PSIZE10 0x10 362*4882a593Smuzhiyun #define IBM640_LCI 0x08 363*4882a593Smuzhiyun #define IBM640_WIDCTL_MASK 0x07 364*4882a593Smuzhiyun #define RGB640_VGA_CONTROL 0x0b 365*4882a593Smuzhiyun #define IBM640_RDBK 0x04 366*4882a593Smuzhiyun #define IBM640_PSIZE8 0x02 367*4882a593Smuzhiyun #define IBM640_VRAM 0x01 368*4882a593Smuzhiyun #define RGB640_DAC_CONTROL 0x0d 369*4882a593Smuzhiyun #define IBM640_MONO 0x08 370*4882a593Smuzhiyun #define IBM640_DACENBL 0x04 371*4882a593Smuzhiyun #define IBM640_SHUNT 0x02 372*4882a593Smuzhiyun #define IBM640_SLOWSLEW 0x01 373*4882a593Smuzhiyun #define RGB640_OUTPUT_CONTROL 0x0e 374*4882a593Smuzhiyun #define IBM640_RDAI 0x04 375*4882a593Smuzhiyun #define IBM640_WDAI 0x02 376*4882a593Smuzhiyun #define IBM640_WATCTL 0x01 377*4882a593Smuzhiyun #define RGB640_SYNC_CONTROL 0x0f 378*4882a593Smuzhiyun #define IBM640_PWR 0x20 379*4882a593Smuzhiyun #define IBM640_VSP 0x10 380*4882a593Smuzhiyun #define IBM640_HSP 0x08 381*4882a593Smuzhiyun #define IBM640_CSE 0x04 382*4882a593Smuzhiyun #define IBM640_CSG 0x02 383*4882a593Smuzhiyun #define IBM640_BPE 0x01 384*4882a593Smuzhiyun #define RGB640_PLL_N 0x10 385*4882a593Smuzhiyun #define RGB640_PLL_M 0x11 386*4882a593Smuzhiyun #define RGB640_PLL_P 0x12 387*4882a593Smuzhiyun #define RGB640_PLL_CTL 0x13 388*4882a593Smuzhiyun #define IBM640_PLL_EN 0x04 389*4882a593Smuzhiyun #define IBM640_PLL_HIGH 0x10 390*4882a593Smuzhiyun #define IBM640_PLL_LOW 0x01 391*4882a593Smuzhiyun #define RGB640_AUX_PLL_CTL 0x17 392*4882a593Smuzhiyun #define IBM640_AUXPLL 0x04 393*4882a593Smuzhiyun #define IBM640_AUX_HI 0x02 394*4882a593Smuzhiyun #define IBM640_AUX_LO 0x01 395*4882a593Smuzhiyun #define RGB640_CHROMA_KEY0 0x20 396*4882a593Smuzhiyun #define RGB640_CHROMA_MASK0 0x21 397*4882a593Smuzhiyun #define RGB640_CURS_X_LOW 0x40 398*4882a593Smuzhiyun #define RGB640_CURS_X_HIGH 0x41 399*4882a593Smuzhiyun #define RGB640_CURS_Y_LOW 0x42 400*4882a593Smuzhiyun #define RGB640_CURS_Y_HIGH 0x43 401*4882a593Smuzhiyun #define RGB640_CURS_OFFSETX 0x44 402*4882a593Smuzhiyun #define RGB640_CURS_OFFSETY 0x45 403*4882a593Smuzhiyun #define RGB640_CURSOR_CONTROL 0x4B 404*4882a593Smuzhiyun #define IBM640_CURS_OFF 0x00 405*4882a593Smuzhiyun #define IBM640_CURS_MODE0 0x01 406*4882a593Smuzhiyun #define IBM640_CURS_MODE1 0x02 407*4882a593Smuzhiyun #define IBM640_CURS_MODE2 0x03 408*4882a593Smuzhiyun #define IBM640_CURS_ADV 0x04 409*4882a593Smuzhiyun #define RGB640_CROSSHAIR_CONTROL 0x57 410*4882a593Smuzhiyun #define RGB640_VRAM_MASK0 0xf0 411*4882a593Smuzhiyun #define RGB640_VRAM_MASK1 0xf1 412*4882a593Smuzhiyun #define RGB640_VRAM_MASK2 0xf2 413*4882a593Smuzhiyun #define RGB640_DIAGS 0xfa 414*4882a593Smuzhiyun #define RGB640_CURS_WRITE 0x1000 415*4882a593Smuzhiyun #define RGB640_CURS_COL0 0x4800 416*4882a593Smuzhiyun #define RGB640_CURS_COL1 0x4801 417*4882a593Smuzhiyun #define RGB640_CURS_COL2 0x4802 418*4882a593Smuzhiyun #define RGB640_CURS_COL3 0x4803 419