1*4882a593Smuzhiyun 2*4882a593Smuzhiyun #include "xf86RamDac.h" 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun extern _X_EXPORT RamDacHelperRecPtr BTramdacProbe(ScrnInfoPtr pScrn, 5*4882a593Smuzhiyun RamDacSupportedInfoRecPtr 6*4882a593Smuzhiyun ramdacs); 7*4882a593Smuzhiyun extern _X_EXPORT void BTramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, 8*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 9*4882a593Smuzhiyun extern _X_EXPORT void BTramdacRestore(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec, 10*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 11*4882a593Smuzhiyun extern _X_EXPORT void BTramdacSetBpp(ScrnInfoPtr pScrn, 12*4882a593Smuzhiyun RamDacRegRecPtr RamDacRegRec); 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define ATT20C504_RAMDAC (VENDOR_BT << 16) | 0x00 15*4882a593Smuzhiyun #define ATT20C505_RAMDAC (VENDOR_BT << 16) | 0x01 16*4882a593Smuzhiyun #define BT485_RAMDAC (VENDOR_BT << 16) | 0x02 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* 19*4882a593Smuzhiyun * BT registers 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define BT_WRITE_ADDR 0x00 23*4882a593Smuzhiyun #define BT_RAMDAC_DATA 0x01 24*4882a593Smuzhiyun #define BT_PIXEL_MASK 0x02 25*4882a593Smuzhiyun #define BT_READ_ADDR 0x03 26*4882a593Smuzhiyun #define BT_CURS_WR_ADDR 0x04 27*4882a593Smuzhiyun #define BT_CURS_DATA 0x05 28*4882a593Smuzhiyun #define BT_COMMAND_REG_0 0x06 29*4882a593Smuzhiyun #define BT_CURS_RD_ADDR 0x07 30*4882a593Smuzhiyun #define BT_COMMAND_REG_1 0x08 31*4882a593Smuzhiyun #define BT_COMMAND_REG_2 0x09 32*4882a593Smuzhiyun #define BT_STATUS_REG 0x0A 33*4882a593Smuzhiyun #define BT_CURS_RAM_DATA 0x0B 34*4882a593Smuzhiyun #define BT_CURS_X_LOW 0x0C 35*4882a593Smuzhiyun #define BT_CURS_X_HIGH 0x0D 36*4882a593Smuzhiyun #define BT_CURS_Y_LOW 0x0E 37*4882a593Smuzhiyun #define BT_CURS_Y_HIGH 0x0F 38