1*4882a593Smuzhiyun 2*4882a593Smuzhiyun /* xf86DDC.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file contains all information to interpret a standard EDIC block 5*4882a593Smuzhiyun * transmitted by a display device via DDC (Display Data Channel). So far 6*4882a593Smuzhiyun * there is no information to deal with optional EDID blocks. 7*4882a593Smuzhiyun * DDC is a Trademark of VESA (Video Electronics Standard Association). 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef XF86_DDC_H 13*4882a593Smuzhiyun #define XF86_DDC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "edid.h" 16*4882a593Smuzhiyun #include "xf86i2c.h" 17*4882a593Smuzhiyun #include "xf86str.h" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* speed up / slow down */ 20*4882a593Smuzhiyun typedef enum { 21*4882a593Smuzhiyun DDC_SLOW, 22*4882a593Smuzhiyun DDC_FAST 23*4882a593Smuzhiyun } xf86ddcSpeed; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun typedef void (*DDC1SetSpeedProc) (ScrnInfoPtr, xf86ddcSpeed); 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86DoEDID_DDC1(ScrnInfoPtr pScrn, 28*4882a593Smuzhiyun DDC1SetSpeedProc DDC1SetSpeed, 29*4882a593Smuzhiyun unsigned 30*4882a593Smuzhiyun int (*DDC1Read) (ScrnInfoPtr) 31*4882a593Smuzhiyun ); 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86DoEDID_DDC2(ScrnInfoPtr pScrn, I2CBusPtr pBus); 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86DoEEDID(ScrnInfoPtr pScrn, I2CBusPtr pBus, Bool); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86PrintEDID(xf86MonPtr monPtr); 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86InterpretEDID(int screenIndex, Uchar * block); 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun extern _X_EXPORT xf86MonPtr xf86InterpretEEDID(int screenIndex, Uchar * block); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun extern _X_EXPORT void 44*4882a593Smuzhiyun xf86EdidMonitorSet(int scrnIndex, MonPtr Monitor, xf86MonPtr DDC); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun extern _X_EXPORT Bool xf86SetDDCproperties(ScrnInfoPtr pScreen, xf86MonPtr DDC); 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun extern _X_EXPORT Bool 49*4882a593Smuzhiyun xf86MonitorIsHDMI(xf86MonPtr mon); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun extern _X_EXPORT Bool 52*4882a593Smuzhiyun gtf_supported(xf86MonPtr mon); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun extern _X_EXPORT DisplayModePtr 55*4882a593Smuzhiyun FindDMTMode(int hsize, int vsize, int refresh, Bool rb); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun extern _X_EXPORT const DisplayModeRec DMTModes[]; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * Quirks to work around broken EDID data from various monitors. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun typedef enum { 63*4882a593Smuzhiyun DDC_QUIRK_NONE = 0, 64*4882a593Smuzhiyun /* First detailed mode is bogus, prefer largest mode at 60hz */ 65*4882a593Smuzhiyun DDC_QUIRK_PREFER_LARGE_60 = 1 << 0, 66*4882a593Smuzhiyun /* 135MHz clock is too high, drop a bit */ 67*4882a593Smuzhiyun DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 1, 68*4882a593Smuzhiyun /* Prefer the largest mode at 75 Hz */ 69*4882a593Smuzhiyun DDC_QUIRK_PREFER_LARGE_75 = 1 << 2, 70*4882a593Smuzhiyun /* Convert detailed timing's horizontal from units of cm to mm */ 71*4882a593Smuzhiyun DDC_QUIRK_DETAILED_H_IN_CM = 1 << 3, 72*4882a593Smuzhiyun /* Convert detailed timing's vertical from units of cm to mm */ 73*4882a593Smuzhiyun DDC_QUIRK_DETAILED_V_IN_CM = 1 << 4, 74*4882a593Smuzhiyun /* Detailed timing descriptors have bogus size values, so just take the 75*4882a593Smuzhiyun * maximum size and use that. 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun DDC_QUIRK_DETAILED_USE_MAXIMUM_SIZE = 1 << 5, 78*4882a593Smuzhiyun /* Monitor forgot to set the first detailed is preferred bit. */ 79*4882a593Smuzhiyun DDC_QUIRK_FIRST_DETAILED_PREFERRED = 1 << 6, 80*4882a593Smuzhiyun /* use +hsync +vsync for detailed mode */ 81*4882a593Smuzhiyun DDC_QUIRK_DETAILED_SYNC_PP = 1 << 7, 82*4882a593Smuzhiyun /* Force single-link DVI bandwidth limit */ 83*4882a593Smuzhiyun DDC_QUIRK_DVI_SINGLE_LINK = 1 << 8, 84*4882a593Smuzhiyun } ddc_quirk_t; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun typedef void (*handle_detailed_fn) (struct detailed_monitor_section *, void *); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun void xf86ForEachDetailedBlock(xf86MonPtr mon, handle_detailed_fn, void *data); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun ddc_quirk_t xf86DDCDetectQuirks(int scrnIndex, xf86MonPtr DDC, Bool verbose); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun void xf86DetTimingApplyQuirks(struct detailed_monitor_section *det_mon, 93*4882a593Smuzhiyun ddc_quirk_t quirks, int hsize, int vsize); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun typedef void (*handle_video_fn) (struct cea_video_block *, void *); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun void xf86ForEachVideoBlock(xf86MonPtr, handle_video_fn, void *); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct cea_data_block *xf86MonitorFindHDMIBlock(xf86MonPtr mon); 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #endif 102