xref: /OK3568_Linux_fs/external/xserver/hw/xfree86/ddc/DDC.HOWTO (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun			DDC.HOWTO
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun  This file describes how to add DDC support to a chipset driver.
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun1) DDC INITIALIZATION
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun   When implementing DDC in the driver one has the choice between
8*4882a593Smuzhiyun   DDC1 and DDC2.
9*4882a593Smuzhiyun   DDC1 data is continuously transmitted by a DDC1 capable display
10*4882a593Smuzhiyun   device. The data is send serially over a data line; the Vsync
11*4882a593Smuzhiyun   signal serves as clock. Only one EDID 1.x data block can be
12*4882a593Smuzhiyun   transmitted using DDC1. Since transmission of an EDID1 block
13*4882a593Smuzhiyun   using a regular Vsync frequency would take up several seconds
14*4882a593Smuzhiyun   the driver can increase the Vsync frequency to up to 25 kHz as
15*4882a593Smuzhiyun   soon as it detects DDC1 activity on the data line.
16*4882a593Smuzhiyun   DDC2 data is transmitted using the I2C protocol. This requires
17*4882a593Smuzhiyun   an additional clock line. DDC2 is capable of transmitting EDID1
18*4882a593Smuzhiyun   and EDID2 block as well as a VDIF block on display devices that
19*4882a593Smuzhiyun   support these.
20*4882a593Smuzhiyun   Display devices switch into the DDC2 mode as soon as they detect
21*4882a593Smuzhiyun   activity on the DDC clock line. Once the are in DDC2 mode they
22*4882a593Smuzhiyun   stop transmitting DDC1 signals until the next power cycle.
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun   Some graphics chipset configurations which are not capable of
25*4882a593Smuzhiyun   DDC2 might still be able to read DDC1 data. Where available
26*4882a593Smuzhiyun   DDC2 it is preferable.
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun   All relevant prototypes and defines are in xf86DDC.h.
29*4882a593Smuzhiyun   DDC2 additionally requires I2C support. The I2C prototypes
30*4882a593Smuzhiyun   are in xf86i2c.h.
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun   DDC1 Support:
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun     The driver has to provide a read function which waits for the
35*4882a593Smuzhiyun     end of the next Vsync signal and reads in and returns the status
36*4882a593Smuzhiyun     of the DDC line:
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun     unsigned int XXX_ddc1Read(ScrnInfoPtr pScrn)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun     Additionally a function is required to increase the Vsync
41*4882a593Smuzhiyun     frequency to max. 25 kHz.
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun     void XXX_ddc1SetSpeed(ScrnInfoPtr pScrn, xf86ddcSpeed speed)
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun     If the speed argument is DDC_FAST the function should increase
46*4882a593Smuzhiyun     the Vsync frequency on DDC_SLOW it should restore the original
47*4882a593Smuzhiyun     value. For convenience a generic ddc1SetSpeed() function is provided
48*4882a593Smuzhiyun     in the vga module for VGA-like chipsets.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun     void vgaHWddc1SetSpeed(ScrnInfoPtr pScrn, sf86ddcSpeed speed).
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun     To read out the DDC1 data the driver should call
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun     xf86MonPtr xf86DoEDID_DDC1(int scrnIndex,
55*4882a593Smuzhiyun                              void (*DDC1SetSpeed)(ScrnInfoPtr, xf86ddcSpeed),
56*4882a593Smuzhiyun                              unsigned int (*DDC1Read)(ScrnInfoPtr))
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun     in PreInit(). DDC1SetSpeed is a pointer to the SetSpeed()
59*4882a593Smuzhiyun     function, DDC1Read has to point to the DDC1 read function.
60*4882a593Smuzhiyun     The function will return a pointer to the xf86Monitor structure
61*4882a593Smuzhiyun     which contains all information retrieved by DDC.
62*4882a593Smuzhiyun     NULL will be returned on failure.
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun   DDC2 Support
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun     To read out DDC2 information I2C has to be initialized first.
67*4882a593Smuzhiyun     (See documentation for the i2c module).
68*4882a593Smuzhiyun     The function
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun     xf86MonPtr xf86DoEDID_DDC2(int scrnIndex, I2CBusPtr pBus)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun     is provided to read out and process DDC2 data. A pointer
73*4882a593Smuzhiyun     to the I2CBusRec of the appropriate I2C Bus has to be passed
74*4882a593Smuzhiyun     as the second argument.
75*4882a593Smuzhiyun     The function will return a pointer to the xf86Monitor structure
76*4882a593Smuzhiyun     which contains all information retrieved by DDC.
77*4882a593Smuzhiyun     NULL will be returned on failure.
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun   Printing monitor parameters
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun     To print out the information contained in the xf86Monitor
82*4882a593Smuzhiyun     structure the function
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun     xf86MonPtr xf86PrintEDID(xf86MonPtr monitor)
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun     is provided.
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun    Further processing of the xf86Monitor structure is not yet
89*4882a593Smuzhiyun    implemented. However, it is planned to use the information
90*4882a593Smuzhiyun    about video modes, gamma values etc.
91*4882a593Smuzhiyun    Therefore it is strongly recommended to read out DDC data
92*4882a593Smuzhiyun    before any video mode processing is done.
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun$XFree86: xc/programs/Xserver/hw/xfree86/ddc/DDC.HOWTO,v 1.2 1998/12/06 13:30:39 dawes Exp $
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