1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * \file xf86drm.h 3*4882a593Smuzhiyun * OS-independent header for DRM user-level library interface. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * \author Rickard E. (Rik) Faith <faith@valinux.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Copyright 1999, 2000 Precision Insight, Inc., Cedar Park, Texas. 10*4882a593Smuzhiyun * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 11*4882a593Smuzhiyun * All Rights Reserved. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 14*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 15*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 16*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 17*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 18*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next 21*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the 22*4882a593Smuzhiyun * Software. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 27*4882a593Smuzhiyun * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 28*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 29*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE. 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #ifndef _XF86DRM_H_ 35*4882a593Smuzhiyun #define _XF86DRM_H_ 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #include <stdarg.h> 38*4882a593Smuzhiyun #include <sys/types.h> 39*4882a593Smuzhiyun #include <stdint.h> 40*4882a593Smuzhiyun #include <drm.h> 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #if defined(__cplusplus) 43*4882a593Smuzhiyun extern "C" { 44*4882a593Smuzhiyun #endif 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #ifndef DRM_MAX_MINOR 47*4882a593Smuzhiyun #define DRM_MAX_MINOR 16 48*4882a593Smuzhiyun #endif 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #if defined(__linux__) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define DRM_IOCTL_NR(n) _IOC_NR(n) 53*4882a593Smuzhiyun #define DRM_IOC_VOID _IOC_NONE 54*4882a593Smuzhiyun #define DRM_IOC_READ _IOC_READ 55*4882a593Smuzhiyun #define DRM_IOC_WRITE _IOC_WRITE 56*4882a593Smuzhiyun #define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE 57*4882a593Smuzhiyun #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #else /* One of the *BSDs */ 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #include <sys/ioccom.h> 62*4882a593Smuzhiyun #define DRM_IOCTL_NR(n) ((n) & 0xff) 63*4882a593Smuzhiyun #define DRM_IOC_VOID IOC_VOID 64*4882a593Smuzhiyun #define DRM_IOC_READ IOC_OUT 65*4882a593Smuzhiyun #define DRM_IOC_WRITE IOC_IN 66*4882a593Smuzhiyun #define DRM_IOC_READWRITE IOC_INOUT 67*4882a593Smuzhiyun #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Defaults, if nothing set in xf86config */ 72*4882a593Smuzhiyun #define DRM_DEV_UID 0 73*4882a593Smuzhiyun #define DRM_DEV_GID 0 74*4882a593Smuzhiyun /* Default /dev/dri directory permissions 0755 */ 75*4882a593Smuzhiyun #define DRM_DEV_DIRMODE \ 76*4882a593Smuzhiyun (S_IRUSR|S_IWUSR|S_IXUSR|S_IRGRP|S_IXGRP|S_IROTH|S_IXOTH) 77*4882a593Smuzhiyun #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #ifdef __OpenBSD__ 80*4882a593Smuzhiyun #define DRM_DIR_NAME "/dev" 81*4882a593Smuzhiyun #define DRM_PRIMARY_MINOR_NAME "drm" 82*4882a593Smuzhiyun #define DRM_CONTROL_MINOR_NAME "drmC" 83*4882a593Smuzhiyun #define DRM_RENDER_MINOR_NAME "drmR" 84*4882a593Smuzhiyun #else 85*4882a593Smuzhiyun #define DRM_DIR_NAME "/dev/dri" 86*4882a593Smuzhiyun #define DRM_PRIMARY_MINOR_NAME "card" 87*4882a593Smuzhiyun #define DRM_CONTROL_MINOR_NAME "controlD" 88*4882a593Smuzhiyun #define DRM_RENDER_MINOR_NAME "renderD" 89*4882a593Smuzhiyun #define DRM_PROC_NAME "/proc/dri/" /* For backward Linux compatibility */ 90*4882a593Smuzhiyun #endif 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define DRM_DEV_NAME "%s/" DRM_PRIMARY_MINOR_NAME "%d" 93*4882a593Smuzhiyun #define DRM_CONTROL_DEV_NAME "%s/" DRM_CONTROL_MINOR_NAME "%d" 94*4882a593Smuzhiyun #define DRM_RENDER_DEV_NAME "%s/" DRM_RENDER_MINOR_NAME "%d" 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define DRM_NODE_NAME_MAX \ 97*4882a593Smuzhiyun (sizeof(DRM_DIR_NAME) + 1 /* slash */ \ 98*4882a593Smuzhiyun + MAX3(sizeof(DRM_PRIMARY_MINOR_NAME), \ 99*4882a593Smuzhiyun sizeof(DRM_CONTROL_MINOR_NAME), \ 100*4882a593Smuzhiyun sizeof(DRM_RENDER_MINOR_NAME)) \ 101*4882a593Smuzhiyun + sizeof("144") /* highest possible node number */ \ 102*4882a593Smuzhiyun + 1) /* NULL-terminator */ 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define DRM_ERR_NO_DEVICE (-1001) 105*4882a593Smuzhiyun #define DRM_ERR_NO_ACCESS (-1002) 106*4882a593Smuzhiyun #define DRM_ERR_NOT_ROOT (-1003) 107*4882a593Smuzhiyun #define DRM_ERR_INVALID (-1004) 108*4882a593Smuzhiyun #define DRM_ERR_NO_FD (-1005) 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #define DRM_AGP_NO_HANDLE 0 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun typedef unsigned int drmSize, *drmSizePtr; /**< For mapped regions */ 113*4882a593Smuzhiyun typedef void *drmAddress, **drmAddressPtr; /**< For mapped regions */ 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #if (__GNUC__ >= 3) 116*4882a593Smuzhiyun #define DRM_PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a))) 117*4882a593Smuzhiyun #else 118*4882a593Smuzhiyun #define DRM_PRINTFLIKE(f, a) 119*4882a593Smuzhiyun #endif 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun typedef struct _drmServerInfo { 122*4882a593Smuzhiyun int (*debug_print)(const char *format, va_list ap) DRM_PRINTFLIKE(1,0); 123*4882a593Smuzhiyun int (*load_module)(const char *name); 124*4882a593Smuzhiyun void (*get_perms)(gid_t *, mode_t *); 125*4882a593Smuzhiyun } drmServerInfo, *drmServerInfoPtr; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun typedef struct drmHashEntry { 128*4882a593Smuzhiyun int fd; 129*4882a593Smuzhiyun void (*f)(int, void *, void *); 130*4882a593Smuzhiyun void *tagTable; 131*4882a593Smuzhiyun } drmHashEntry; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun extern int drmIoctl(int fd, unsigned long request, void *arg); 134*4882a593Smuzhiyun extern void *drmGetHashTable(void); 135*4882a593Smuzhiyun extern drmHashEntry *drmGetEntry(int fd); 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /** 138*4882a593Smuzhiyun * Driver version information. 139*4882a593Smuzhiyun * 140*4882a593Smuzhiyun * \sa drmGetVersion() and drmSetVersion(). 141*4882a593Smuzhiyun */ 142*4882a593Smuzhiyun typedef struct _drmVersion { 143*4882a593Smuzhiyun int version_major; /**< Major version */ 144*4882a593Smuzhiyun int version_minor; /**< Minor version */ 145*4882a593Smuzhiyun int version_patchlevel; /**< Patch level */ 146*4882a593Smuzhiyun int name_len; /**< Length of name buffer */ 147*4882a593Smuzhiyun char *name; /**< Name of driver */ 148*4882a593Smuzhiyun int date_len; /**< Length of date buffer */ 149*4882a593Smuzhiyun char *date; /**< User-space buffer to hold date */ 150*4882a593Smuzhiyun int desc_len; /**< Length of desc buffer */ 151*4882a593Smuzhiyun char *desc; /**< User-space buffer to hold desc */ 152*4882a593Smuzhiyun } drmVersion, *drmVersionPtr; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun typedef struct _drmStats { 155*4882a593Smuzhiyun unsigned long count; /**< Number of data */ 156*4882a593Smuzhiyun struct { 157*4882a593Smuzhiyun unsigned long value; /**< Value from kernel */ 158*4882a593Smuzhiyun const char *long_format; /**< Suggested format for long_name */ 159*4882a593Smuzhiyun const char *long_name; /**< Long name for value */ 160*4882a593Smuzhiyun const char *rate_format; /**< Suggested format for rate_name */ 161*4882a593Smuzhiyun const char *rate_name; /**< Short name for value per second */ 162*4882a593Smuzhiyun int isvalue; /**< True if value (vs. counter) */ 163*4882a593Smuzhiyun const char *mult_names; /**< Multiplier names (e.g., "KGM") */ 164*4882a593Smuzhiyun int mult; /**< Multiplier value (e.g., 1024) */ 165*4882a593Smuzhiyun int verbose; /**< Suggest only in verbose output */ 166*4882a593Smuzhiyun } data[15]; 167*4882a593Smuzhiyun } drmStatsT; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun /* All of these enums *MUST* match with the 171*4882a593Smuzhiyun kernel implementation -- so do *NOT* 172*4882a593Smuzhiyun change them! (The drmlib implementation 173*4882a593Smuzhiyun will just copy the flags instead of 174*4882a593Smuzhiyun translating them.) */ 175*4882a593Smuzhiyun typedef enum { 176*4882a593Smuzhiyun DRM_FRAME_BUFFER = 0, /**< WC, no caching, no core dump */ 177*4882a593Smuzhiyun DRM_REGISTERS = 1, /**< no caching, no core dump */ 178*4882a593Smuzhiyun DRM_SHM = 2, /**< shared, cached */ 179*4882a593Smuzhiyun DRM_AGP = 3, /**< AGP/GART */ 180*4882a593Smuzhiyun DRM_SCATTER_GATHER = 4, /**< PCI scatter/gather */ 181*4882a593Smuzhiyun DRM_CONSISTENT = 5 /**< PCI consistent */ 182*4882a593Smuzhiyun } drmMapType; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun typedef enum { 185*4882a593Smuzhiyun DRM_RESTRICTED = 0x0001, /**< Cannot be mapped to client-virtual */ 186*4882a593Smuzhiyun DRM_READ_ONLY = 0x0002, /**< Read-only in client-virtual */ 187*4882a593Smuzhiyun DRM_LOCKED = 0x0004, /**< Physical pages locked */ 188*4882a593Smuzhiyun DRM_KERNEL = 0x0008, /**< Kernel requires access */ 189*4882a593Smuzhiyun DRM_WRITE_COMBINING = 0x0010, /**< Use write-combining, if available */ 190*4882a593Smuzhiyun DRM_CONTAINS_LOCK = 0x0020, /**< SHM page that contains lock */ 191*4882a593Smuzhiyun DRM_REMOVABLE = 0x0040 /**< Removable mapping */ 192*4882a593Smuzhiyun } drmMapFlags; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /** 195*4882a593Smuzhiyun * \warning These values *MUST* match drm.h 196*4882a593Smuzhiyun */ 197*4882a593Smuzhiyun typedef enum { 198*4882a593Smuzhiyun /** \name Flags for DMA buffer dispatch */ 199*4882a593Smuzhiyun /*@{*/ 200*4882a593Smuzhiyun DRM_DMA_BLOCK = 0x01, /**< 201*4882a593Smuzhiyun * Block until buffer dispatched. 202*4882a593Smuzhiyun * 203*4882a593Smuzhiyun * \note the buffer may not yet have been 204*4882a593Smuzhiyun * processed by the hardware -- getting a 205*4882a593Smuzhiyun * hardware lock with the hardware quiescent 206*4882a593Smuzhiyun * will ensure that the buffer has been 207*4882a593Smuzhiyun * processed. 208*4882a593Smuzhiyun */ 209*4882a593Smuzhiyun DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ 210*4882a593Smuzhiyun DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ 211*4882a593Smuzhiyun /*@}*/ 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun /** \name Flags for DMA buffer request */ 214*4882a593Smuzhiyun /*@{*/ 215*4882a593Smuzhiyun DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ 216*4882a593Smuzhiyun DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ 217*4882a593Smuzhiyun DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ 218*4882a593Smuzhiyun /*@}*/ 219*4882a593Smuzhiyun } drmDMAFlags; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun typedef enum { 222*4882a593Smuzhiyun DRM_PAGE_ALIGN = 0x01, 223*4882a593Smuzhiyun DRM_AGP_BUFFER = 0x02, 224*4882a593Smuzhiyun DRM_SG_BUFFER = 0x04, 225*4882a593Smuzhiyun DRM_FB_BUFFER = 0x08, 226*4882a593Smuzhiyun DRM_PCI_BUFFER_RO = 0x10 227*4882a593Smuzhiyun } drmBufDescFlags; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun typedef enum { 230*4882a593Smuzhiyun DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ 231*4882a593Smuzhiyun DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ 232*4882a593Smuzhiyun DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ 233*4882a593Smuzhiyun DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ 234*4882a593Smuzhiyun /* These *HALT* flags aren't supported yet 235*4882a593Smuzhiyun -- they will be used to support the 236*4882a593Smuzhiyun full-screen DGA-like mode. */ 237*4882a593Smuzhiyun DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ 238*4882a593Smuzhiyun DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ 239*4882a593Smuzhiyun } drmLockFlags; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun typedef enum { 242*4882a593Smuzhiyun DRM_CONTEXT_PRESERVED = 0x01, /**< This context is preserved and 243*4882a593Smuzhiyun never swapped. */ 244*4882a593Smuzhiyun DRM_CONTEXT_2DONLY = 0x02 /**< This context is for 2D rendering only. */ 245*4882a593Smuzhiyun } drm_context_tFlags, *drm_context_tFlagsPtr; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun typedef struct _drmBufDesc { 248*4882a593Smuzhiyun int count; /**< Number of buffers of this size */ 249*4882a593Smuzhiyun int size; /**< Size in bytes */ 250*4882a593Smuzhiyun int low_mark; /**< Low water mark */ 251*4882a593Smuzhiyun int high_mark; /**< High water mark */ 252*4882a593Smuzhiyun } drmBufDesc, *drmBufDescPtr; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun typedef struct _drmBufInfo { 255*4882a593Smuzhiyun int count; /**< Number of buffers described in list */ 256*4882a593Smuzhiyun drmBufDescPtr list; /**< List of buffer descriptions */ 257*4882a593Smuzhiyun } drmBufInfo, *drmBufInfoPtr; 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun typedef struct _drmBuf { 260*4882a593Smuzhiyun int idx; /**< Index into the master buffer list */ 261*4882a593Smuzhiyun int total; /**< Buffer size */ 262*4882a593Smuzhiyun int used; /**< Amount of buffer in use (for DMA) */ 263*4882a593Smuzhiyun drmAddress address; /**< Address */ 264*4882a593Smuzhiyun } drmBuf, *drmBufPtr; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /** 267*4882a593Smuzhiyun * Buffer mapping information. 268*4882a593Smuzhiyun * 269*4882a593Smuzhiyun * Used by drmMapBufs() and drmUnmapBufs() to store information about the 270*4882a593Smuzhiyun * mapped buffers. 271*4882a593Smuzhiyun */ 272*4882a593Smuzhiyun typedef struct _drmBufMap { 273*4882a593Smuzhiyun int count; /**< Number of buffers mapped */ 274*4882a593Smuzhiyun drmBufPtr list; /**< Buffers */ 275*4882a593Smuzhiyun } drmBufMap, *drmBufMapPtr; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun typedef struct _drmLock { 278*4882a593Smuzhiyun volatile unsigned int lock; 279*4882a593Smuzhiyun char padding[60]; 280*4882a593Smuzhiyun /* This is big enough for most current (and future?) architectures: 281*4882a593Smuzhiyun DEC Alpha: 32 bytes 282*4882a593Smuzhiyun Intel Merced: ? 283*4882a593Smuzhiyun Intel P5/PPro/PII/PIII: 32 bytes 284*4882a593Smuzhiyun Intel StrongARM: 32 bytes 285*4882a593Smuzhiyun Intel i386/i486: 16 bytes 286*4882a593Smuzhiyun MIPS: 32 bytes (?) 287*4882a593Smuzhiyun Motorola 68k: 16 bytes 288*4882a593Smuzhiyun Motorola PowerPC: 32 bytes 289*4882a593Smuzhiyun Sun SPARC: 32 bytes 290*4882a593Smuzhiyun */ 291*4882a593Smuzhiyun } drmLock, *drmLockPtr; 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /** 294*4882a593Smuzhiyun * Indices here refer to the offset into 295*4882a593Smuzhiyun * list in drmBufInfo 296*4882a593Smuzhiyun */ 297*4882a593Smuzhiyun typedef struct _drmDMAReq { 298*4882a593Smuzhiyun drm_context_t context; /**< Context handle */ 299*4882a593Smuzhiyun int send_count; /**< Number of buffers to send */ 300*4882a593Smuzhiyun int *send_list; /**< List of handles to buffers */ 301*4882a593Smuzhiyun int *send_sizes; /**< Lengths of data to send, in bytes */ 302*4882a593Smuzhiyun drmDMAFlags flags; /**< Flags */ 303*4882a593Smuzhiyun int request_count; /**< Number of buffers requested */ 304*4882a593Smuzhiyun int request_size; /**< Desired size of buffers requested */ 305*4882a593Smuzhiyun int *request_list; /**< Buffer information */ 306*4882a593Smuzhiyun int *request_sizes; /**< Minimum acceptable sizes */ 307*4882a593Smuzhiyun int granted_count; /**< Number of buffers granted at this size */ 308*4882a593Smuzhiyun } drmDMAReq, *drmDMAReqPtr; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun typedef struct _drmRegion { 311*4882a593Smuzhiyun drm_handle_t handle; 312*4882a593Smuzhiyun unsigned int offset; 313*4882a593Smuzhiyun drmSize size; 314*4882a593Smuzhiyun drmAddress map; 315*4882a593Smuzhiyun } drmRegion, *drmRegionPtr; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun typedef struct _drmTextureRegion { 318*4882a593Smuzhiyun unsigned char next; 319*4882a593Smuzhiyun unsigned char prev; 320*4882a593Smuzhiyun unsigned char in_use; 321*4882a593Smuzhiyun unsigned char padding; /**< Explicitly pad this out */ 322*4882a593Smuzhiyun unsigned int age; 323*4882a593Smuzhiyun } drmTextureRegion, *drmTextureRegionPtr; 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun typedef enum { 327*4882a593Smuzhiyun DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ 328*4882a593Smuzhiyun DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ 329*4882a593Smuzhiyun /* bits 1-6 are reserved for high crtcs */ 330*4882a593Smuzhiyun DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, 331*4882a593Smuzhiyun DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ 332*4882a593Smuzhiyun DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ 333*4882a593Smuzhiyun DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ 334*4882a593Smuzhiyun DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ 335*4882a593Smuzhiyun DRM_VBLANK_SIGNAL = 0x40000000 /* Send signal instead of blocking */ 336*4882a593Smuzhiyun } drmVBlankSeqType; 337*4882a593Smuzhiyun #define DRM_VBLANK_HIGH_CRTC_SHIFT 1 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun typedef struct _drmVBlankReq { 340*4882a593Smuzhiyun drmVBlankSeqType type; 341*4882a593Smuzhiyun unsigned int sequence; 342*4882a593Smuzhiyun unsigned long signal; 343*4882a593Smuzhiyun } drmVBlankReq, *drmVBlankReqPtr; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun typedef struct _drmVBlankReply { 346*4882a593Smuzhiyun drmVBlankSeqType type; 347*4882a593Smuzhiyun unsigned int sequence; 348*4882a593Smuzhiyun long tval_sec; 349*4882a593Smuzhiyun long tval_usec; 350*4882a593Smuzhiyun } drmVBlankReply, *drmVBlankReplyPtr; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun typedef union _drmVBlank { 353*4882a593Smuzhiyun drmVBlankReq request; 354*4882a593Smuzhiyun drmVBlankReply reply; 355*4882a593Smuzhiyun } drmVBlank, *drmVBlankPtr; 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun typedef struct _drmSetVersion { 358*4882a593Smuzhiyun int drm_di_major; 359*4882a593Smuzhiyun int drm_di_minor; 360*4882a593Smuzhiyun int drm_dd_major; 361*4882a593Smuzhiyun int drm_dd_minor; 362*4882a593Smuzhiyun } drmSetVersion, *drmSetVersionPtr; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun #define __drm_dummy_lock(lock) (*(__volatile__ unsigned int *)lock) 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun #define DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ 367*4882a593Smuzhiyun #define DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun #if defined(__GNUC__) && (__GNUC__ >= 2) 370*4882a593Smuzhiyun # if defined(__i386) || defined(__AMD64__) || defined(__x86_64__) || defined(__amd64__) 371*4882a593Smuzhiyun /* Reflect changes here to drmP.h */ 372*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 373*4882a593Smuzhiyun do { \ 374*4882a593Smuzhiyun int __dummy; /* Can't mark eax as clobbered */ \ 375*4882a593Smuzhiyun __asm__ __volatile__( \ 376*4882a593Smuzhiyun "lock ; cmpxchg %4,%1\n\t" \ 377*4882a593Smuzhiyun "setnz %0" \ 378*4882a593Smuzhiyun : "=d" (__ret), \ 379*4882a593Smuzhiyun "=m" (__drm_dummy_lock(lock)), \ 380*4882a593Smuzhiyun "=a" (__dummy) \ 381*4882a593Smuzhiyun : "2" (old), \ 382*4882a593Smuzhiyun "r" (new)); \ 383*4882a593Smuzhiyun } while (0) 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun #elif defined(__alpha__) 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun #define DRM_CAS(lock, old, new, ret) \ 388*4882a593Smuzhiyun do { \ 389*4882a593Smuzhiyun int tmp, old32; \ 390*4882a593Smuzhiyun __asm__ __volatile__( \ 391*4882a593Smuzhiyun " addl $31, %5, %3\n" \ 392*4882a593Smuzhiyun "1: ldl_l %0, %2\n" \ 393*4882a593Smuzhiyun " cmpeq %0, %3, %1\n" \ 394*4882a593Smuzhiyun " beq %1, 2f\n" \ 395*4882a593Smuzhiyun " mov %4, %0\n" \ 396*4882a593Smuzhiyun " stl_c %0, %2\n" \ 397*4882a593Smuzhiyun " beq %0, 3f\n" \ 398*4882a593Smuzhiyun " mb\n" \ 399*4882a593Smuzhiyun "2: cmpeq %1, 0, %1\n" \ 400*4882a593Smuzhiyun ".subsection 2\n" \ 401*4882a593Smuzhiyun "3: br 1b\n" \ 402*4882a593Smuzhiyun ".previous" \ 403*4882a593Smuzhiyun : "=&r"(tmp), "=&r"(ret), \ 404*4882a593Smuzhiyun "=m"(__drm_dummy_lock(lock)), \ 405*4882a593Smuzhiyun "=&r"(old32) \ 406*4882a593Smuzhiyun : "r"(new), "r"(old) \ 407*4882a593Smuzhiyun : "memory"); \ 408*4882a593Smuzhiyun } while (0) 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun #elif defined(__sparc__) 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 413*4882a593Smuzhiyun do { register unsigned int __old __asm("o0"); \ 414*4882a593Smuzhiyun register unsigned int __new __asm("o1"); \ 415*4882a593Smuzhiyun register volatile unsigned int *__lock __asm("o2"); \ 416*4882a593Smuzhiyun __old = old; \ 417*4882a593Smuzhiyun __new = new; \ 418*4882a593Smuzhiyun __lock = (volatile unsigned int *)lock; \ 419*4882a593Smuzhiyun __asm__ __volatile__( \ 420*4882a593Smuzhiyun /*"cas [%2], %3, %0"*/ \ 421*4882a593Smuzhiyun ".word 0xd3e29008\n\t" \ 422*4882a593Smuzhiyun /*"membar #StoreStore | #StoreLoad"*/ \ 423*4882a593Smuzhiyun ".word 0x8143e00a" \ 424*4882a593Smuzhiyun : "=&r" (__new) \ 425*4882a593Smuzhiyun : "0" (__new), \ 426*4882a593Smuzhiyun "r" (__lock), \ 427*4882a593Smuzhiyun "r" (__old) \ 428*4882a593Smuzhiyun : "memory"); \ 429*4882a593Smuzhiyun __ret = (__new != __old); \ 430*4882a593Smuzhiyun } while(0) 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun #elif defined(__ia64__) 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun #ifdef __INTEL_COMPILER 435*4882a593Smuzhiyun /* this currently generates bad code (missing stop bits)... */ 436*4882a593Smuzhiyun #include <ia64intrin.h> 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 439*4882a593Smuzhiyun do { \ 440*4882a593Smuzhiyun unsigned long __result, __old = (old) & 0xffffffff; \ 441*4882a593Smuzhiyun __mf(); \ 442*4882a593Smuzhiyun __result = _InterlockedCompareExchange_acq(&__drm_dummy_lock(lock), (new), __old);\ 443*4882a593Smuzhiyun __ret = (__result) != (__old); \ 444*4882a593Smuzhiyun /* __ret = (__sync_val_compare_and_swap(&__drm_dummy_lock(lock), \ 445*4882a593Smuzhiyun (old), (new)) \ 446*4882a593Smuzhiyun != (old)); */\ 447*4882a593Smuzhiyun } while (0) 448*4882a593Smuzhiyun 449*4882a593Smuzhiyun #else 450*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 451*4882a593Smuzhiyun do { \ 452*4882a593Smuzhiyun unsigned int __result, __old = (old); \ 453*4882a593Smuzhiyun __asm__ __volatile__( \ 454*4882a593Smuzhiyun "mf\n" \ 455*4882a593Smuzhiyun "mov ar.ccv=%2\n" \ 456*4882a593Smuzhiyun ";;\n" \ 457*4882a593Smuzhiyun "cmpxchg4.acq %0=%1,%3,ar.ccv" \ 458*4882a593Smuzhiyun : "=r" (__result), "=m" (__drm_dummy_lock(lock)) \ 459*4882a593Smuzhiyun : "r" ((unsigned long)__old), "r" (new) \ 460*4882a593Smuzhiyun : "memory"); \ 461*4882a593Smuzhiyun __ret = (__result) != (__old); \ 462*4882a593Smuzhiyun } while (0) 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun #endif 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun #elif defined(__powerpc__) 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 469*4882a593Smuzhiyun do { \ 470*4882a593Smuzhiyun __asm__ __volatile__( \ 471*4882a593Smuzhiyun "sync;" \ 472*4882a593Smuzhiyun "0: lwarx %0,0,%1;" \ 473*4882a593Smuzhiyun " xor. %0,%3,%0;" \ 474*4882a593Smuzhiyun " bne 1f;" \ 475*4882a593Smuzhiyun " stwcx. %2,0,%1;" \ 476*4882a593Smuzhiyun " bne- 0b;" \ 477*4882a593Smuzhiyun "1: " \ 478*4882a593Smuzhiyun "sync;" \ 479*4882a593Smuzhiyun : "=&r"(__ret) \ 480*4882a593Smuzhiyun : "r"(lock), "r"(new), "r"(old) \ 481*4882a593Smuzhiyun : "cr0", "memory"); \ 482*4882a593Smuzhiyun } while (0) 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun # elif defined (__ARM_ARCH_6__) || defined(__ARM_ARCH_6J__) \ 485*4882a593Smuzhiyun || defined (__ARM_ARCH_6Z__) || defined(__ARM_ARCH_6ZK__) \ 486*4882a593Smuzhiyun || defined (__ARM_ARCH_6K__) || defined(__ARM_ARCH_6T2__) \ 487*4882a593Smuzhiyun || defined (__ARM_ARCH_7__) || defined(__ARM_ARCH_7A__) \ 488*4882a593Smuzhiyun || defined(__ARM_ARCH_7R__) || defined(__ARM_ARCH_7M__) \ 489*4882a593Smuzhiyun || defined(__ARM_ARCH_7EM__) 490*4882a593Smuzhiyun /* excluding ARMv4/ARMv5 and lower (lacking ldrex/strex support) */ 491*4882a593Smuzhiyun #undef DRM_DEV_MODE 492*4882a593Smuzhiyun #define DRM_DEV_MODE (S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH|S_IWOTH) 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,__ret) \ 495*4882a593Smuzhiyun do { \ 496*4882a593Smuzhiyun __asm__ __volatile__ ( \ 497*4882a593Smuzhiyun "1: ldrex %0, [%1]\n" \ 498*4882a593Smuzhiyun " teq %0, %2\n" \ 499*4882a593Smuzhiyun " ite eq\n" \ 500*4882a593Smuzhiyun " strexeq %0, %3, [%1]\n" \ 501*4882a593Smuzhiyun " movne %0, #1\n" \ 502*4882a593Smuzhiyun : "=&r" (__ret) \ 503*4882a593Smuzhiyun : "r" (lock), "r" (old), "r" (new) \ 504*4882a593Smuzhiyun : "cc","memory"); \ 505*4882a593Smuzhiyun } while (0) 506*4882a593Smuzhiyun 507*4882a593Smuzhiyun #endif /* architecture */ 508*4882a593Smuzhiyun #endif /* __GNUC__ >= 2 */ 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun #ifndef DRM_CAS 511*4882a593Smuzhiyun #define DRM_CAS(lock,old,new,ret) do { ret=1; } while (0) /* FAST LOCK FAILS */ 512*4882a593Smuzhiyun #endif 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #if defined(__alpha__) 515*4882a593Smuzhiyun #define DRM_CAS_RESULT(_result) long _result 516*4882a593Smuzhiyun #elif defined(__powerpc__) 517*4882a593Smuzhiyun #define DRM_CAS_RESULT(_result) int _result 518*4882a593Smuzhiyun #else 519*4882a593Smuzhiyun #define DRM_CAS_RESULT(_result) char _result 520*4882a593Smuzhiyun #endif 521*4882a593Smuzhiyun 522*4882a593Smuzhiyun #define DRM_LIGHT_LOCK(fd,lock,context) \ 523*4882a593Smuzhiyun do { \ 524*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 525*4882a593Smuzhiyun DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ 526*4882a593Smuzhiyun if (__ret) drmGetLock(fd,context,0); \ 527*4882a593Smuzhiyun } while(0) 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun /* This one counts fast locks -- for 530*4882a593Smuzhiyun benchmarking only. */ 531*4882a593Smuzhiyun #define DRM_LIGHT_LOCK_COUNT(fd,lock,context,count) \ 532*4882a593Smuzhiyun do { \ 533*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 534*4882a593Smuzhiyun DRM_CAS(lock,context,DRM_LOCK_HELD|context,__ret); \ 535*4882a593Smuzhiyun if (__ret) drmGetLock(fd,context,0); \ 536*4882a593Smuzhiyun else ++count; \ 537*4882a593Smuzhiyun } while(0) 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun #define DRM_LOCK(fd,lock,context,flags) \ 540*4882a593Smuzhiyun do { \ 541*4882a593Smuzhiyun if (flags) drmGetLock(fd,context,flags); \ 542*4882a593Smuzhiyun else DRM_LIGHT_LOCK(fd,lock,context); \ 543*4882a593Smuzhiyun } while(0) 544*4882a593Smuzhiyun 545*4882a593Smuzhiyun #define DRM_UNLOCK(fd,lock,context) \ 546*4882a593Smuzhiyun do { \ 547*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 548*4882a593Smuzhiyun DRM_CAS(lock,DRM_LOCK_HELD|context,context,__ret); \ 549*4882a593Smuzhiyun if (__ret) drmUnlock(fd,context); \ 550*4882a593Smuzhiyun } while(0) 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun /* Simple spin locks */ 553*4882a593Smuzhiyun #define DRM_SPINLOCK(spin,val) \ 554*4882a593Smuzhiyun do { \ 555*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 556*4882a593Smuzhiyun do { \ 557*4882a593Smuzhiyun DRM_CAS(spin,0,val,__ret); \ 558*4882a593Smuzhiyun if (__ret) while ((spin)->lock); \ 559*4882a593Smuzhiyun } while (__ret); \ 560*4882a593Smuzhiyun } while(0) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun #define DRM_SPINLOCK_TAKE(spin,val) \ 563*4882a593Smuzhiyun do { \ 564*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 565*4882a593Smuzhiyun int cur; \ 566*4882a593Smuzhiyun do { \ 567*4882a593Smuzhiyun cur = (*spin).lock; \ 568*4882a593Smuzhiyun DRM_CAS(spin,cur,val,__ret); \ 569*4882a593Smuzhiyun } while (__ret); \ 570*4882a593Smuzhiyun } while(0) 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun #define DRM_SPINLOCK_COUNT(spin,val,count,__ret) \ 573*4882a593Smuzhiyun do { \ 574*4882a593Smuzhiyun int __i; \ 575*4882a593Smuzhiyun __ret = 1; \ 576*4882a593Smuzhiyun for (__i = 0; __ret && __i < count; __i++) { \ 577*4882a593Smuzhiyun DRM_CAS(spin,0,val,__ret); \ 578*4882a593Smuzhiyun if (__ret) for (;__i < count && (spin)->lock; __i++); \ 579*4882a593Smuzhiyun } \ 580*4882a593Smuzhiyun } while(0) 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun #define DRM_SPINUNLOCK(spin,val) \ 583*4882a593Smuzhiyun do { \ 584*4882a593Smuzhiyun DRM_CAS_RESULT(__ret); \ 585*4882a593Smuzhiyun if ((*spin).lock == val) { /* else server stole lock */ \ 586*4882a593Smuzhiyun do { \ 587*4882a593Smuzhiyun DRM_CAS(spin,val,0,__ret); \ 588*4882a593Smuzhiyun } while (__ret); \ 589*4882a593Smuzhiyun } \ 590*4882a593Smuzhiyun } while(0) 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun /* General user-level programmer's API: unprivileged */ 595*4882a593Smuzhiyun extern int drmAvailable(void); 596*4882a593Smuzhiyun extern int drmOpen(const char *name, const char *busid); 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun #define DRM_NODE_PRIMARY 0 599*4882a593Smuzhiyun #define DRM_NODE_CONTROL 1 600*4882a593Smuzhiyun #define DRM_NODE_RENDER 2 601*4882a593Smuzhiyun #define DRM_NODE_MAX 3 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun extern int drmOpenWithType(const char *name, const char *busid, 604*4882a593Smuzhiyun int type); 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun extern int drmOpenControl(int minor); 607*4882a593Smuzhiyun extern int drmOpenRender(int minor); 608*4882a593Smuzhiyun extern int drmClose(int fd); 609*4882a593Smuzhiyun extern drmVersionPtr drmGetVersion(int fd); 610*4882a593Smuzhiyun extern drmVersionPtr drmGetLibVersion(int fd); 611*4882a593Smuzhiyun extern int drmGetCap(int fd, uint64_t capability, uint64_t *value); 612*4882a593Smuzhiyun extern void drmFreeVersion(drmVersionPtr); 613*4882a593Smuzhiyun extern int drmGetMagic(int fd, drm_magic_t * magic); 614*4882a593Smuzhiyun extern char *drmGetBusid(int fd); 615*4882a593Smuzhiyun extern int drmGetInterruptFromBusID(int fd, int busnum, int devnum, 616*4882a593Smuzhiyun int funcnum); 617*4882a593Smuzhiyun extern int drmGetMap(int fd, int idx, drm_handle_t *offset, 618*4882a593Smuzhiyun drmSize *size, drmMapType *type, 619*4882a593Smuzhiyun drmMapFlags *flags, drm_handle_t *handle, 620*4882a593Smuzhiyun int *mtrr); 621*4882a593Smuzhiyun extern int drmGetClient(int fd, int idx, int *auth, int *pid, 622*4882a593Smuzhiyun int *uid, unsigned long *magic, 623*4882a593Smuzhiyun unsigned long *iocs); 624*4882a593Smuzhiyun extern int drmGetStats(int fd, drmStatsT *stats); 625*4882a593Smuzhiyun extern int drmSetInterfaceVersion(int fd, drmSetVersion *version); 626*4882a593Smuzhiyun extern int drmCommandNone(int fd, unsigned long drmCommandIndex); 627*4882a593Smuzhiyun extern int drmCommandRead(int fd, unsigned long drmCommandIndex, 628*4882a593Smuzhiyun void *data, unsigned long size); 629*4882a593Smuzhiyun extern int drmCommandWrite(int fd, unsigned long drmCommandIndex, 630*4882a593Smuzhiyun void *data, unsigned long size); 631*4882a593Smuzhiyun extern int drmCommandWriteRead(int fd, unsigned long drmCommandIndex, 632*4882a593Smuzhiyun void *data, unsigned long size); 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun /* General user-level programmer's API: X server (root) only */ 635*4882a593Smuzhiyun extern void drmFreeBusid(const char *busid); 636*4882a593Smuzhiyun extern int drmSetBusid(int fd, const char *busid); 637*4882a593Smuzhiyun extern int drmAuthMagic(int fd, drm_magic_t magic); 638*4882a593Smuzhiyun extern int drmAddMap(int fd, 639*4882a593Smuzhiyun drm_handle_t offset, 640*4882a593Smuzhiyun drmSize size, 641*4882a593Smuzhiyun drmMapType type, 642*4882a593Smuzhiyun drmMapFlags flags, 643*4882a593Smuzhiyun drm_handle_t * handle); 644*4882a593Smuzhiyun extern int drmRmMap(int fd, drm_handle_t handle); 645*4882a593Smuzhiyun extern int drmAddContextPrivateMapping(int fd, drm_context_t ctx_id, 646*4882a593Smuzhiyun drm_handle_t handle); 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun extern int drmAddBufs(int fd, int count, int size, 649*4882a593Smuzhiyun drmBufDescFlags flags, 650*4882a593Smuzhiyun int agp_offset); 651*4882a593Smuzhiyun extern int drmMarkBufs(int fd, double low, double high); 652*4882a593Smuzhiyun extern int drmCreateContext(int fd, drm_context_t * handle); 653*4882a593Smuzhiyun extern int drmSetContextFlags(int fd, drm_context_t context, 654*4882a593Smuzhiyun drm_context_tFlags flags); 655*4882a593Smuzhiyun extern int drmGetContextFlags(int fd, drm_context_t context, 656*4882a593Smuzhiyun drm_context_tFlagsPtr flags); 657*4882a593Smuzhiyun extern int drmAddContextTag(int fd, drm_context_t context, void *tag); 658*4882a593Smuzhiyun extern int drmDelContextTag(int fd, drm_context_t context); 659*4882a593Smuzhiyun extern void *drmGetContextTag(int fd, drm_context_t context); 660*4882a593Smuzhiyun extern drm_context_t * drmGetReservedContextList(int fd, int *count); 661*4882a593Smuzhiyun extern void drmFreeReservedContextList(drm_context_t *); 662*4882a593Smuzhiyun extern int drmSwitchToContext(int fd, drm_context_t context); 663*4882a593Smuzhiyun extern int drmDestroyContext(int fd, drm_context_t handle); 664*4882a593Smuzhiyun extern int drmCreateDrawable(int fd, drm_drawable_t * handle); 665*4882a593Smuzhiyun extern int drmDestroyDrawable(int fd, drm_drawable_t handle); 666*4882a593Smuzhiyun extern int drmUpdateDrawableInfo(int fd, drm_drawable_t handle, 667*4882a593Smuzhiyun drm_drawable_info_type_t type, 668*4882a593Smuzhiyun unsigned int num, void *data); 669*4882a593Smuzhiyun extern int drmCtlInstHandler(int fd, int irq); 670*4882a593Smuzhiyun extern int drmCtlUninstHandler(int fd); 671*4882a593Smuzhiyun extern int drmSetClientCap(int fd, uint64_t capability, 672*4882a593Smuzhiyun uint64_t value); 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun extern int drmCrtcGetSequence(int fd, uint32_t crtcId, 675*4882a593Smuzhiyun uint64_t *sequence, uint64_t *ns); 676*4882a593Smuzhiyun extern int drmCrtcQueueSequence(int fd, uint32_t crtcId, 677*4882a593Smuzhiyun uint32_t flags, uint64_t sequence, 678*4882a593Smuzhiyun uint64_t *sequence_queued, 679*4882a593Smuzhiyun uint64_t user_data); 680*4882a593Smuzhiyun /* General user-level programmer's API: authenticated client and/or X */ 681*4882a593Smuzhiyun extern int drmMap(int fd, 682*4882a593Smuzhiyun drm_handle_t handle, 683*4882a593Smuzhiyun drmSize size, 684*4882a593Smuzhiyun drmAddressPtr address); 685*4882a593Smuzhiyun extern int drmUnmap(drmAddress address, drmSize size); 686*4882a593Smuzhiyun extern drmBufInfoPtr drmGetBufInfo(int fd); 687*4882a593Smuzhiyun extern drmBufMapPtr drmMapBufs(int fd); 688*4882a593Smuzhiyun extern int drmUnmapBufs(drmBufMapPtr bufs); 689*4882a593Smuzhiyun extern int drmDMA(int fd, drmDMAReqPtr request); 690*4882a593Smuzhiyun extern int drmFreeBufs(int fd, int count, int *list); 691*4882a593Smuzhiyun extern int drmGetLock(int fd, 692*4882a593Smuzhiyun drm_context_t context, 693*4882a593Smuzhiyun drmLockFlags flags); 694*4882a593Smuzhiyun extern int drmUnlock(int fd, drm_context_t context); 695*4882a593Smuzhiyun extern int drmFinish(int fd, int context, drmLockFlags flags); 696*4882a593Smuzhiyun extern int drmGetContextPrivateMapping(int fd, drm_context_t ctx_id, 697*4882a593Smuzhiyun drm_handle_t * handle); 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun /* AGP/GART support: X server (root) only */ 700*4882a593Smuzhiyun extern int drmAgpAcquire(int fd); 701*4882a593Smuzhiyun extern int drmAgpRelease(int fd); 702*4882a593Smuzhiyun extern int drmAgpEnable(int fd, unsigned long mode); 703*4882a593Smuzhiyun extern int drmAgpAlloc(int fd, unsigned long size, 704*4882a593Smuzhiyun unsigned long type, unsigned long *address, 705*4882a593Smuzhiyun drm_handle_t *handle); 706*4882a593Smuzhiyun extern int drmAgpFree(int fd, drm_handle_t handle); 707*4882a593Smuzhiyun extern int drmAgpBind(int fd, drm_handle_t handle, 708*4882a593Smuzhiyun unsigned long offset); 709*4882a593Smuzhiyun extern int drmAgpUnbind(int fd, drm_handle_t handle); 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun /* AGP/GART info: authenticated client and/or X */ 712*4882a593Smuzhiyun extern int drmAgpVersionMajor(int fd); 713*4882a593Smuzhiyun extern int drmAgpVersionMinor(int fd); 714*4882a593Smuzhiyun extern unsigned long drmAgpGetMode(int fd); 715*4882a593Smuzhiyun extern unsigned long drmAgpBase(int fd); /* Physical location */ 716*4882a593Smuzhiyun extern unsigned long drmAgpSize(int fd); /* Bytes */ 717*4882a593Smuzhiyun extern unsigned long drmAgpMemoryUsed(int fd); 718*4882a593Smuzhiyun extern unsigned long drmAgpMemoryAvail(int fd); 719*4882a593Smuzhiyun extern unsigned int drmAgpVendorId(int fd); 720*4882a593Smuzhiyun extern unsigned int drmAgpDeviceId(int fd); 721*4882a593Smuzhiyun 722*4882a593Smuzhiyun /* PCI scatter/gather support: X server (root) only */ 723*4882a593Smuzhiyun extern int drmScatterGatherAlloc(int fd, unsigned long size, 724*4882a593Smuzhiyun drm_handle_t *handle); 725*4882a593Smuzhiyun extern int drmScatterGatherFree(int fd, drm_handle_t handle); 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun extern int drmWaitVBlank(int fd, drmVBlankPtr vbl); 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun /* Support routines */ 730*4882a593Smuzhiyun extern void drmSetServerInfo(drmServerInfoPtr info); 731*4882a593Smuzhiyun extern int drmError(int err, const char *label); 732*4882a593Smuzhiyun extern void *drmMalloc(int size); 733*4882a593Smuzhiyun extern void drmFree(void *pt); 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun /* Hash table routines */ 736*4882a593Smuzhiyun extern void *drmHashCreate(void); 737*4882a593Smuzhiyun extern int drmHashDestroy(void *t); 738*4882a593Smuzhiyun extern int drmHashLookup(void *t, unsigned long key, void **value); 739*4882a593Smuzhiyun extern int drmHashInsert(void *t, unsigned long key, void *value); 740*4882a593Smuzhiyun extern int drmHashDelete(void *t, unsigned long key); 741*4882a593Smuzhiyun extern int drmHashFirst(void *t, unsigned long *key, void **value); 742*4882a593Smuzhiyun extern int drmHashNext(void *t, unsigned long *key, void **value); 743*4882a593Smuzhiyun 744*4882a593Smuzhiyun /* PRNG routines */ 745*4882a593Smuzhiyun extern void *drmRandomCreate(unsigned long seed); 746*4882a593Smuzhiyun extern int drmRandomDestroy(void *state); 747*4882a593Smuzhiyun extern unsigned long drmRandom(void *state); 748*4882a593Smuzhiyun extern double drmRandomDouble(void *state); 749*4882a593Smuzhiyun 750*4882a593Smuzhiyun /* Skip list routines */ 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun extern void *drmSLCreate(void); 753*4882a593Smuzhiyun extern int drmSLDestroy(void *l); 754*4882a593Smuzhiyun extern int drmSLLookup(void *l, unsigned long key, void **value); 755*4882a593Smuzhiyun extern int drmSLInsert(void *l, unsigned long key, void *value); 756*4882a593Smuzhiyun extern int drmSLDelete(void *l, unsigned long key); 757*4882a593Smuzhiyun extern int drmSLNext(void *l, unsigned long *key, void **value); 758*4882a593Smuzhiyun extern int drmSLFirst(void *l, unsigned long *key, void **value); 759*4882a593Smuzhiyun extern void drmSLDump(void *l); 760*4882a593Smuzhiyun extern int drmSLLookupNeighbors(void *l, unsigned long key, 761*4882a593Smuzhiyun unsigned long *prev_key, void **prev_value, 762*4882a593Smuzhiyun unsigned long *next_key, void **next_value); 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun extern int drmOpenOnce(void *unused, const char *BusID, int *newlyopened); 765*4882a593Smuzhiyun extern int drmOpenOnceWithType(const char *BusID, int *newlyopened, int type); 766*4882a593Smuzhiyun extern void drmCloseOnce(int fd); 767*4882a593Smuzhiyun extern void drmMsg(const char *format, ...) DRM_PRINTFLIKE(1, 2); 768*4882a593Smuzhiyun 769*4882a593Smuzhiyun extern int drmSetMaster(int fd); 770*4882a593Smuzhiyun extern int drmDropMaster(int fd); 771*4882a593Smuzhiyun extern int drmIsMaster(int fd); 772*4882a593Smuzhiyun 773*4882a593Smuzhiyun #define DRM_EVENT_CONTEXT_VERSION 4 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun typedef struct _drmEventContext { 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun /* This struct is versioned so we can add more pointers if we 778*4882a593Smuzhiyun * add more events. */ 779*4882a593Smuzhiyun int version; 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun void (*vblank_handler)(int fd, 782*4882a593Smuzhiyun unsigned int sequence, 783*4882a593Smuzhiyun unsigned int tv_sec, 784*4882a593Smuzhiyun unsigned int tv_usec, 785*4882a593Smuzhiyun void *user_data); 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun void (*page_flip_handler)(int fd, 788*4882a593Smuzhiyun unsigned int sequence, 789*4882a593Smuzhiyun unsigned int tv_sec, 790*4882a593Smuzhiyun unsigned int tv_usec, 791*4882a593Smuzhiyun void *user_data); 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun void (*page_flip_handler2)(int fd, 794*4882a593Smuzhiyun unsigned int sequence, 795*4882a593Smuzhiyun unsigned int tv_sec, 796*4882a593Smuzhiyun unsigned int tv_usec, 797*4882a593Smuzhiyun unsigned int crtc_id, 798*4882a593Smuzhiyun void *user_data); 799*4882a593Smuzhiyun 800*4882a593Smuzhiyun void (*sequence_handler)(int fd, 801*4882a593Smuzhiyun uint64_t sequence, 802*4882a593Smuzhiyun uint64_t ns, 803*4882a593Smuzhiyun uint64_t user_data); 804*4882a593Smuzhiyun } drmEventContext, *drmEventContextPtr; 805*4882a593Smuzhiyun 806*4882a593Smuzhiyun extern int drmHandleEvent(int fd, drmEventContextPtr evctx); 807*4882a593Smuzhiyun 808*4882a593Smuzhiyun extern char *drmGetDeviceNameFromFd(int fd); 809*4882a593Smuzhiyun 810*4882a593Smuzhiyun /* Improved version of drmGetDeviceNameFromFd which attributes for any type of 811*4882a593Smuzhiyun * device/node - card, control or renderD. 812*4882a593Smuzhiyun */ 813*4882a593Smuzhiyun extern char *drmGetDeviceNameFromFd2(int fd); 814*4882a593Smuzhiyun extern int drmGetNodeTypeFromFd(int fd); 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun /* Convert between GEM handles and DMA-BUF file descriptors. 817*4882a593Smuzhiyun * 818*4882a593Smuzhiyun * Warning: since GEM handles are not reference-counted and are unique per 819*4882a593Smuzhiyun * DRM file description, the caller is expected to perform its own reference 820*4882a593Smuzhiyun * counting. drmPrimeFDToHandle is guaranteed to return the same handle for 821*4882a593Smuzhiyun * different FDs if they reference the same underlying buffer object. This 822*4882a593Smuzhiyun * could even be a buffer object originally created on the same DRM FD. 823*4882a593Smuzhiyun * 824*4882a593Smuzhiyun * When sharing a DRM FD with an API such as EGL or GBM, the caller must not 825*4882a593Smuzhiyun * use drmPrimeHandleToFD nor drmPrimeFDToHandle. A single user-space 826*4882a593Smuzhiyun * reference-counting implementation is necessary to avoid double-closing GEM 827*4882a593Smuzhiyun * handles. 828*4882a593Smuzhiyun * 829*4882a593Smuzhiyun * Two processes can't share the same DRM FD and both use it to create or 830*4882a593Smuzhiyun * import GEM handles, even when using a single user-space reference-counting 831*4882a593Smuzhiyun * implementation like GBM, because GBM doesn't share its state between 832*4882a593Smuzhiyun * processes. 833*4882a593Smuzhiyun */ 834*4882a593Smuzhiyun extern int drmPrimeHandleToFD(int fd, uint32_t handle, uint32_t flags, int *prime_fd); 835*4882a593Smuzhiyun extern int drmPrimeFDToHandle(int fd, int prime_fd, uint32_t *handle); 836*4882a593Smuzhiyun 837*4882a593Smuzhiyun extern char *drmGetPrimaryDeviceNameFromFd(int fd); 838*4882a593Smuzhiyun extern char *drmGetRenderDeviceNameFromFd(int fd); 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun #define DRM_BUS_PCI 0 841*4882a593Smuzhiyun #define DRM_BUS_USB 1 842*4882a593Smuzhiyun #define DRM_BUS_PLATFORM 2 843*4882a593Smuzhiyun #define DRM_BUS_HOST1X 3 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun typedef struct _drmPciBusInfo { 846*4882a593Smuzhiyun uint16_t domain; 847*4882a593Smuzhiyun uint8_t bus; 848*4882a593Smuzhiyun uint8_t dev; 849*4882a593Smuzhiyun uint8_t func; 850*4882a593Smuzhiyun } drmPciBusInfo, *drmPciBusInfoPtr; 851*4882a593Smuzhiyun 852*4882a593Smuzhiyun typedef struct _drmPciDeviceInfo { 853*4882a593Smuzhiyun uint16_t vendor_id; 854*4882a593Smuzhiyun uint16_t device_id; 855*4882a593Smuzhiyun uint16_t subvendor_id; 856*4882a593Smuzhiyun uint16_t subdevice_id; 857*4882a593Smuzhiyun uint8_t revision_id; 858*4882a593Smuzhiyun } drmPciDeviceInfo, *drmPciDeviceInfoPtr; 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun typedef struct _drmUsbBusInfo { 861*4882a593Smuzhiyun uint8_t bus; 862*4882a593Smuzhiyun uint8_t dev; 863*4882a593Smuzhiyun } drmUsbBusInfo, *drmUsbBusInfoPtr; 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun typedef struct _drmUsbDeviceInfo { 866*4882a593Smuzhiyun uint16_t vendor; 867*4882a593Smuzhiyun uint16_t product; 868*4882a593Smuzhiyun } drmUsbDeviceInfo, *drmUsbDeviceInfoPtr; 869*4882a593Smuzhiyun 870*4882a593Smuzhiyun #define DRM_PLATFORM_DEVICE_NAME_LEN 512 871*4882a593Smuzhiyun 872*4882a593Smuzhiyun typedef struct _drmPlatformBusInfo { 873*4882a593Smuzhiyun char fullname[DRM_PLATFORM_DEVICE_NAME_LEN]; 874*4882a593Smuzhiyun } drmPlatformBusInfo, *drmPlatformBusInfoPtr; 875*4882a593Smuzhiyun 876*4882a593Smuzhiyun typedef struct _drmPlatformDeviceInfo { 877*4882a593Smuzhiyun char **compatible; /* NULL terminated list of compatible strings */ 878*4882a593Smuzhiyun } drmPlatformDeviceInfo, *drmPlatformDeviceInfoPtr; 879*4882a593Smuzhiyun 880*4882a593Smuzhiyun #define DRM_HOST1X_DEVICE_NAME_LEN 512 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun typedef struct _drmHost1xBusInfo { 883*4882a593Smuzhiyun char fullname[DRM_HOST1X_DEVICE_NAME_LEN]; 884*4882a593Smuzhiyun } drmHost1xBusInfo, *drmHost1xBusInfoPtr; 885*4882a593Smuzhiyun 886*4882a593Smuzhiyun typedef struct _drmHost1xDeviceInfo { 887*4882a593Smuzhiyun char **compatible; /* NULL terminated list of compatible strings */ 888*4882a593Smuzhiyun } drmHost1xDeviceInfo, *drmHost1xDeviceInfoPtr; 889*4882a593Smuzhiyun 890*4882a593Smuzhiyun typedef struct _drmDevice { 891*4882a593Smuzhiyun char **nodes; /* DRM_NODE_MAX sized array */ 892*4882a593Smuzhiyun int available_nodes; /* DRM_NODE_* bitmask */ 893*4882a593Smuzhiyun int bustype; 894*4882a593Smuzhiyun union { 895*4882a593Smuzhiyun drmPciBusInfoPtr pci; 896*4882a593Smuzhiyun drmUsbBusInfoPtr usb; 897*4882a593Smuzhiyun drmPlatformBusInfoPtr platform; 898*4882a593Smuzhiyun drmHost1xBusInfoPtr host1x; 899*4882a593Smuzhiyun } businfo; 900*4882a593Smuzhiyun union { 901*4882a593Smuzhiyun drmPciDeviceInfoPtr pci; 902*4882a593Smuzhiyun drmUsbDeviceInfoPtr usb; 903*4882a593Smuzhiyun drmPlatformDeviceInfoPtr platform; 904*4882a593Smuzhiyun drmHost1xDeviceInfoPtr host1x; 905*4882a593Smuzhiyun } deviceinfo; 906*4882a593Smuzhiyun } drmDevice, *drmDevicePtr; 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun extern int drmGetDevice(int fd, drmDevicePtr *device); 909*4882a593Smuzhiyun extern void drmFreeDevice(drmDevicePtr *device); 910*4882a593Smuzhiyun 911*4882a593Smuzhiyun extern int drmGetDevices(drmDevicePtr devices[], int max_devices); 912*4882a593Smuzhiyun extern void drmFreeDevices(drmDevicePtr devices[], int count); 913*4882a593Smuzhiyun 914*4882a593Smuzhiyun #define DRM_DEVICE_GET_PCI_REVISION (1 << 0) 915*4882a593Smuzhiyun extern int drmGetDevice2(int fd, uint32_t flags, drmDevicePtr *device); 916*4882a593Smuzhiyun extern int drmGetDevices2(uint32_t flags, drmDevicePtr devices[], int max_devices); 917*4882a593Smuzhiyun 918*4882a593Smuzhiyun extern int drmDevicesEqual(drmDevicePtr a, drmDevicePtr b); 919*4882a593Smuzhiyun 920*4882a593Smuzhiyun extern int drmSyncobjCreate(int fd, uint32_t flags, uint32_t *handle); 921*4882a593Smuzhiyun extern int drmSyncobjDestroy(int fd, uint32_t handle); 922*4882a593Smuzhiyun extern int drmSyncobjHandleToFD(int fd, uint32_t handle, int *obj_fd); 923*4882a593Smuzhiyun extern int drmSyncobjFDToHandle(int fd, int obj_fd, uint32_t *handle); 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd); 926*4882a593Smuzhiyun extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int *sync_file_fd); 927*4882a593Smuzhiyun extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles, 928*4882a593Smuzhiyun int64_t timeout_nsec, unsigned flags, 929*4882a593Smuzhiyun uint32_t *first_signaled); 930*4882a593Smuzhiyun extern int drmSyncobjReset(int fd, const uint32_t *handles, uint32_t handle_count); 931*4882a593Smuzhiyun extern int drmSyncobjSignal(int fd, const uint32_t *handles, uint32_t handle_count); 932*4882a593Smuzhiyun extern int drmSyncobjTimelineSignal(int fd, const uint32_t *handles, 933*4882a593Smuzhiyun uint64_t *points, uint32_t handle_count); 934*4882a593Smuzhiyun extern int drmSyncobjTimelineWait(int fd, uint32_t *handles, uint64_t *points, 935*4882a593Smuzhiyun unsigned num_handles, 936*4882a593Smuzhiyun int64_t timeout_nsec, unsigned flags, 937*4882a593Smuzhiyun uint32_t *first_signaled); 938*4882a593Smuzhiyun extern int drmSyncobjQuery(int fd, uint32_t *handles, uint64_t *points, 939*4882a593Smuzhiyun uint32_t handle_count); 940*4882a593Smuzhiyun extern int drmSyncobjQuery2(int fd, uint32_t *handles, uint64_t *points, 941*4882a593Smuzhiyun uint32_t handle_count, uint32_t flags); 942*4882a593Smuzhiyun extern int drmSyncobjTransfer(int fd, 943*4882a593Smuzhiyun uint32_t dst_handle, uint64_t dst_point, 944*4882a593Smuzhiyun uint32_t src_handle, uint64_t src_point, 945*4882a593Smuzhiyun uint32_t flags); 946*4882a593Smuzhiyun 947*4882a593Smuzhiyun extern char * 948*4882a593Smuzhiyun drmGetFormatModifierVendor(uint64_t modifier); 949*4882a593Smuzhiyun 950*4882a593Smuzhiyun extern char * 951*4882a593Smuzhiyun drmGetFormatModifierName(uint64_t modifier); 952*4882a593Smuzhiyun 953*4882a593Smuzhiyun #ifndef fourcc_mod_get_vendor 954*4882a593Smuzhiyun #define fourcc_mod_get_vendor(modifier) \ 955*4882a593Smuzhiyun (((modifier) >> 56) & 0xff) 956*4882a593Smuzhiyun #endif 957*4882a593Smuzhiyun 958*4882a593Smuzhiyun #if defined(__cplusplus) 959*4882a593Smuzhiyun } 960*4882a593Smuzhiyun #endif 961*4882a593Smuzhiyun 962*4882a593Smuzhiyun #endif 963