1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2021 Rockchip Electronics Co. LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 5*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 6*4882a593Smuzhiyun * You may obtain a copy of the License at 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 11*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 12*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*4882a593Smuzhiyun * See the License for the specific language governing permissions and 14*4882a593Smuzhiyun * limitations under the License. 15*4882a593Smuzhiyun * 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef INCLUDE_RT_MPI_RK_DEFINES_H_ 19*4882a593Smuzhiyun #define INCLUDE_RT_MPI_RK_DEFINES_H_ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Automatic generated [rv1109] config */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef __cplusplus 24*4882a593Smuzhiyun #if __cplusplus 25*4882a593Smuzhiyun extern "C" { 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #endif /* __cplusplus */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* For VENC */ 30*4882a593Smuzhiyun #define VENC_MAX_CHN_NUM 16 31*4882a593Smuzhiyun #define VENC_MAX_ROI_NUM 8 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* For VDEC */ 34*4882a593Smuzhiyun #define VDEC_MAX_CHN_NUM 64 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* For Region */ 37*4882a593Smuzhiyun #define RGN_MAX_HANDLE_NUM 128 38*4882a593Smuzhiyun #define RGN_EXTRA_DEVICE_TYPE 1 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* For VI */ 41*4882a593Smuzhiyun /* number of channle and device on video input unit of chip 42*4882a593Smuzhiyun * Note! VI_MAX_CHN_NUM is NOT equal to VI_MAX_DEV_NUM 43*4882a593Smuzhiyun * multiplied by VI_MAX_CHN_NUM, because all VI devices 44*4882a593Smuzhiyun * can't work at mode of 4 channles at the same time. 45*4882a593Smuzhiyun */ 46*4882a593Smuzhiyun #define VI_MAX_DEV_NUM 3 47*4882a593Smuzhiyun #define VI_MAX_PHY_PIPE_NUM VI_MAX_DEV_NUM 48*4882a593Smuzhiyun #define VI_MAX_VIR_PIPE_NUM 0 49*4882a593Smuzhiyun #define VI_MAX_PIPE_NUM (VI_MAX_PHY_PIPE_NUM + VI_MAX_VIR_PIPE_NUM) 50*4882a593Smuzhiyun #define VI_MAX_PHY_CHN_NUM 4 51*4882a593Smuzhiyun #define VI_MAX_EXT_CHN_NUM 0 52*4882a593Smuzhiyun #define VI_MAX_CHN_NUM (VI_MAX_PHY_CHN_NUM + VI_MAX_EXT_CHN_NUM) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* For VO */ 55*4882a593Smuzhiyun #define VO_SPLICE_DEVICE_TYPE 1 56*4882a593Smuzhiyun #define VO_MAX_DEV_NUM 3 /* max dev num */ 57*4882a593Smuzhiyun #define VO_MAX_LAYER_NUM 8 /* max layer num */ 58*4882a593Smuzhiyun #define VO_MAX_CHN_NUM 128 /* max chn num */ 59*4882a593Smuzhiyun #define VO_MAX_WBC_NUM 1 60*4882a593Smuzhiyun #define VO_MAX_BUF_NUM 15 61*4882a593Smuzhiyun #define VO_MAX_PRIORITY 7 /* max layer priority */ 62*4882a593Smuzhiyun #define VO_MAX_PHY_DEV_NUM 3 /* max physical dev num */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* For AUDIO */ 65*4882a593Smuzhiyun #define AI_DEV_MAX_NUM 2 66*4882a593Smuzhiyun #define AI_MAX_CHN_NUM 1 67*4882a593Smuzhiyun #define AO_DEV_MAX_NUM 2 68*4882a593Smuzhiyun #define AO_MAX_CHN_NUM 3 69*4882a593Smuzhiyun #define AENC_MAX_CHN_NUM 32 70*4882a593Smuzhiyun #define ADEC_MAX_CHN_NUM 32 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* For VPSS */ 73*4882a593Smuzhiyun #define VPSS_MAX_GRP_NUM 256 74*4882a593Smuzhiyun #define VPSS_MAX_CHN_NUM 4 75*4882a593Smuzhiyun #define VPSS_MIN_IMAGE_WIDTH 64 76*4882a593Smuzhiyun #define VPSS_MIN_IMAGE_HEIGHT 64 77*4882a593Smuzhiyun #define VPSS_MAX_IMAGE_WIDTH 8192 78*4882a593Smuzhiyun #define VPSS_MAX_IMAGE_HEIGHT 8192 79*4882a593Smuzhiyun #define VPSS_VIDEO_PROC_DEVICE_TYPE 1 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* For VGS */ 82*4882a593Smuzhiyun #define VGS_MAX_JOB_NUM 128 83*4882a593Smuzhiyun #define VGS_MAX_TASK_NUM 200 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* For TDE */ 86*4882a593Smuzhiyun #define TDE_MAX_JOB_NUM 128 87*4882a593Smuzhiyun #define TDE_MAX_TASK_NUM 200 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* For GDC */ 90*4882a593Smuzhiyun #define GDC_MAX_JOB_NUM 128 91*4882a593Smuzhiyun #define GDC_MAX_TASK_NUM 200 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* For AVS */ 94*4882a593Smuzhiyun #define AVS_MAX_GRP_NUM 4 95*4882a593Smuzhiyun #define AVS_PIPE_NUM 2 96*4882a593Smuzhiyun #define AVS_MAX_CHN_NUM 2 97*4882a593Smuzhiyun #define AVS_MAX_IN_WIDTH 4096 98*4882a593Smuzhiyun #define AVS_MAX_IN_HEIGHT 4096 99*4882a593Smuzhiyun #define AVS_MIN_IN_WIDTH 1280 100*4882a593Smuzhiyun #define AVS_MIN_IN_HEIGHT 720 101*4882a593Smuzhiyun #define AVS_MAX_OUT_WIDTH 4096 102*4882a593Smuzhiyun #define AVS_MAX_OUT_HEIGHT 4096 103*4882a593Smuzhiyun #define AVS_MIN_OUT_WIDTH 256 104*4882a593Smuzhiyun #define AVS_MIN_OUT_HEIGHT 256 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #ifdef __cplusplus 107*4882a593Smuzhiyun #if __cplusplus 108*4882a593Smuzhiyun } 109*4882a593Smuzhiyun #endif 110*4882a593Smuzhiyun #endif /* __cplusplus */ 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #endif /* INCLUDE_RT_MPI_RK_DEFINES_H_ */ 113*4882a593Smuzhiyun 114