1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2021 Rockchip Electronics Co. LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 5*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 6*4882a593Smuzhiyun * You may obtain a copy of the License at 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 11*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 12*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*4882a593Smuzhiyun * See the License for the specific language governing permissions and 14*4882a593Smuzhiyun * limitations under the License. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VPSS_H_ 18*4882a593Smuzhiyun #define SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VPSS_H_ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "rk_common.h" 21*4882a593Smuzhiyun #include "rk_comm_vpss.h" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef __cplusplus 24*4882a593Smuzhiyun #if __cplusplus 25*4882a593Smuzhiyun extern "C" { 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun typedef struct _TEST_VPSS_PROC_CTX { 30*4882a593Smuzhiyun const char *srcFileName; 31*4882a593Smuzhiyun const char *dstSaveFileName; 32*4882a593Smuzhiyun RK_U32 u32RawWidth; 33*4882a593Smuzhiyun RK_U32 u32RawHeight; 34*4882a593Smuzhiyun RK_U32 u32RawPixelFmt; 35*4882a593Smuzhiyun RK_U32 u32SendFrameRate; 36*4882a593Smuzhiyun } TEST_VPSS_PROC_CTX_S; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun RK_S32 TEST_VPSS_Start(VPSS_GRP VpssGrp, RK_U32 u32ChnNum, 39*4882a593Smuzhiyun VPSS_GRP_ATTR_S *pstVpssGrpAttr, 40*4882a593Smuzhiyun VPSS_CHN_ATTR_S *pstVpssChnAttr); 41*4882a593Smuzhiyun RK_S32 TEST_VPSS_Stop(VPSS_GRP VpssGrp, RK_U32 u32ChnNum); 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun RK_S32 TEST_VPSS_GrpSetZoom(VPSS_GRP VpssGrp, RK_U32 u32Zoom, RK_BOOL bEnable); 44*4882a593Smuzhiyun RK_S32 TEST_VPSS_ChnSetZoom(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, RK_U32 u32Zoom, RK_BOOL bEnable); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun RK_S32 TEST_VPSS_SetChnRotation(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, ROTATION_E enRotation); 47*4882a593Smuzhiyun RK_S32 TEST_VPSS_SetChnRotationEx(VPSS_GRP VpssGrp, VPSS_CHN VpssChn, RK_U32 u32Angle); 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun RK_S32 TEST_VPSS_StartProc( 50*4882a593Smuzhiyun VPSS_GRP VpssGrp, RK_U32 u32ChnNum, 51*4882a593Smuzhiyun const TEST_VPSS_PROC_CTX_S *pstProcCtx); 52*4882a593Smuzhiyun RK_S32 TEST_VPSS_StopProc(VPSS_GRP VpssGrp); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #ifdef __cplusplus 55*4882a593Smuzhiyun #if __cplusplus 56*4882a593Smuzhiyun } 57*4882a593Smuzhiyun #endif 58*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif // SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VPSS_H_ 61