1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2021 Rockchip Electronics Co. LTD 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Licensed under the Apache License, Version 2.0 (the "License"); 5*4882a593Smuzhiyun * you may not use this file except in compliance with the License. 6*4882a593Smuzhiyun * You may obtain a copy of the License at 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * http://www.apache.org/licenses/LICENSE-2.0 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Unless required by applicable law or agreed to in writing, software 11*4882a593Smuzhiyun * distributed under the License is distributed on an "AS IS" BASIS, 12*4882a593Smuzhiyun * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*4882a593Smuzhiyun * See the License for the specific language governing permissions and 14*4882a593Smuzhiyun * limitations under the License. 15*4882a593Smuzhiyun */ 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #ifndef SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VENC_H_ 18*4882a593Smuzhiyun #define SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VENC_H_ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "rk_common.h" 21*4882a593Smuzhiyun #include "rk_comm_venc.h" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef __cplusplus 24*4882a593Smuzhiyun #if __cplusplus 25*4882a593Smuzhiyun extern "C" { 26*4882a593Smuzhiyun #endif 27*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun typedef struct _COMMON_TEST_VENC_CTX_S { 30*4882a593Smuzhiyun VENC_CHN VencChn; 31*4882a593Smuzhiyun RK_U32 u32Width; 32*4882a593Smuzhiyun RK_U32 u32Height; 33*4882a593Smuzhiyun RK_U32 u32StreamBufCnt; 34*4882a593Smuzhiyun RK_S32 s32RecvPicNum; 35*4882a593Smuzhiyun RK_CODEC_ID_E enType; 36*4882a593Smuzhiyun RK_U32 u32ReadPicNum; // for performance test, read one picture to test. 37*4882a593Smuzhiyun PIXEL_FORMAT_E enPixFmt; 38*4882a593Smuzhiyun const char *pSrcFramePath; 39*4882a593Smuzhiyun const char *pSaveStreamPath; 40*4882a593Smuzhiyun } COMMON_TEST_VENC_CTX_S; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun RK_S32 TEST_VENC_Create(COMMON_TEST_VENC_CTX_S *vencCtx); 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun RK_S32 TEST_VENC_Start(COMMON_TEST_VENC_CTX_S *vencCtx); 45*4882a593Smuzhiyun RK_S32 TEST_VENC_Stop(VENC_CHN VencChn); 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun RK_S32 TEST_VENC_SnapStart(COMMON_TEST_VENC_CTX_S *vencCtx); 48*4882a593Smuzhiyun RK_S32 TEST_VENC_SnapProcess(COMMON_TEST_VENC_CTX_S *vencCtx); 49*4882a593Smuzhiyun RK_S32 TEST_VENC_SnapStop(VENC_CHN VencChn); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun RK_S32 TEST_VENC_SET_BitRate(VENC_RC_ATTR_S *pRcAttr, RK_U32 u32BitRate, RK_U32 u32BitRateMax, RK_U32 u32BitRateMin); 52*4882a593Smuzhiyun RK_S32 TEST_VENC_SET_GopSize(VENC_RC_ATTR_S *pRcAttr, RK_U32 u32GopSize); 53*4882a593Smuzhiyun RK_S32 TEST_VENC_SET_FrameRate(VENC_RC_ATTR_S *pRcAttr, RK_U32 u32Fps); 54*4882a593Smuzhiyun RK_S32 TEST_VENC_SET_FixQp(VENC_RC_ATTR_S *pRcAttr, RK_U32 u32FixIQp, 55*4882a593Smuzhiyun RK_U32 u32FixPQp, RK_U32 u32FixBQp); 56*4882a593Smuzhiyun RK_S32 TEST_VENC_SET_StatTime(VENC_RC_ATTR_S *pRcAttr, RK_U32 u32StatTime); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #ifdef __cplusplus 59*4882a593Smuzhiyun #if __cplusplus 60*4882a593Smuzhiyun } 61*4882a593Smuzhiyun #endif 62*4882a593Smuzhiyun #endif /* End of #ifdef __cplusplus */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #endif // SRC_TESTS_RT_MPI_COMMON_TEST_COMM_VENC_H_ 65