1*4882a593Smuzhiyun# Sample variables file for CYW94373 reference board 2*4882a593SmuzhiyunNVRAMRev=$Rev: 708439 $ 3*4882a593Smuzhiyunsromrev=11 4*4882a593Smuzhiyunvendid=0x14e4 5*4882a593Smuzhiyun# 11ac Dual Band Device ID 6*4882a593Smuzhiyundevid=0x4418 7*4882a593Smuzhiyunmanfid=0x2d0 8*4882a593Smuzhiyunprodid=0x070f 9*4882a593Smuzhiyunmacaddr=00:90:4c:c5:12:38 10*4882a593Smuzhiyunnocrc=1 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun# SSID 13*4882a593Smuzhiyunboardtype=0x83d 14*4882a593Smuzhiyunboardrev=0x1303 15*4882a593Smuzhiyunxtalfreq=37400 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun# X BFL_BTCOEXIST = 0x00000001 This board implements Bluetooth coexistence 18*4882a593Smuzhiyunboardflags=0x00000001 19*4882a593Smuzhiyun# Board flags 2: 20*4882a593Smuzhiyun# X BFL2_BT_SHARE_ANT0 = 0x00800000 share core0 antenna with BT 21*4882a593Smuzhiyunboardflags2=0x00800000 22*4882a593Smuzhiyun# Board flags 3: 23*4882a593Smuzhiyun# femctrl table is read from nvram and Av/Vmid read from NVRAM 24*4882a593Smuzhiyunboardflags3=0x48200100 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun# Margin to account for drift in LPO frequency in units of 0.025% 27*4882a593Smuzhiyunext_lpo_margin_frac=0 28*4882a593Smuzhiyun 29*4882a593Smuzhiyuntx_duty_cycle_thermal=40 30*4882a593Smuzhiyuntemp_threshold=105 31*4882a593Smuzhiyuntemp_delta=30 32*4882a593Smuzhiyunphycal_tempdelta=15 33*4882a593Smuzhiyunrxgains2gelnagaina0=0 34*4882a593Smuzhiyunrxgains2gtrisoa0=0 35*4882a593Smuzhiyunrxgains2gtrelnabypa0=0 36*4882a593Smuzhiyunrxgains5gelnagaina0=0 37*4882a593Smuzhiyunrxgains5gtrisoa0=0 38*4882a593Smuzhiyunrxgains5gtrelnabypa0=0 39*4882a593Smuzhiyunpdgain5g=3 40*4882a593Smuzhiyunpdgain2g=3 41*4882a593Smuzhiyunantswitch=0x6 42*4882a593Smuzhiyunrxchain=1 43*4882a593Smuzhiyuntxchain=1 44*4882a593Smuzhiyunaa2g=3 45*4882a593Smuzhiyunaa5g=3 46*4882a593Smuzhiyuntssipos5g=1 47*4882a593Smuzhiyuntssipos2g=1 48*4882a593Smuzhiyunfemctrl=0 49*4882a593Smuzhiyunpa2ga0=-176,5552,-658 50*4882a593Smuzhiyunpa5ga0=-153,5528,-664,-153,5528,-664,-155,5563,-666,-167,5492,-668 51*4882a593Smuzhiyunpdoffsetcckma0=0xf 52*4882a593Smuzhiyunpdoffset2g40ma0=0xc 53*4882a593Smuzhiyunpdoffset40ma0=0xffff 54*4882a593Smuzhiyunpdoffset80ma0=0xeeee 55*4882a593Smuzhiyunextpagain5g=2 56*4882a593Smuzhiyunextpagain2g=2 57*4882a593SmuzhiyunAvVmid_c0=1,130,0,160,0,160,0,160,0,160 58*4882a593Smuzhiyunmaxp2ga0=76 59*4882a593Smuzhiyunmaxp5ga0=70,70,70,70 60*4882a593Smuzhiyuncckbw202gpo=0x0000 61*4882a593Smuzhiyundot11agofdmhrbw202gpo=0x2222 62*4882a593Smuzhiyunofdmlrbw202gpo=0x3222 63*4882a593Smuzhiyunmcsbw202gpo=0x88764422 64*4882a593Smuzhiyunmcsbw402gpo=0x88764422 65*4882a593Smuzhiyunmcsbw205glpo=0x87664422 66*4882a593Smuzhiyunmcsbw205gmpo=0x87664422 67*4882a593Smuzhiyunmcsbw205ghpo=0x87664422 68*4882a593Smuzhiyunmcsbw405glpo=0x98664422 69*4882a593Smuzhiyunmcsbw405gmpo=0x98664422 70*4882a593Smuzhiyunmcsbw405ghpo=0x98664422 71*4882a593Smuzhiyunmcsbw805glpo=0xEA886622 72*4882a593Smuzhiyunmcsbw805gmpo=0xEA886622 73*4882a593Smuzhiyunmcsbw805ghpo=0xEA886622 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun# RF switch control 76*4882a593Smuzhiyunswctrlmap_2g=0x00001131,0x00001131,0x00001131,0x313131,0x1ff 77*4882a593Smuzhiyunswctrlmap_5g=0x00201131,0x40405171,0x40405171,0x313131,0x1ff 78*4882a593Smuzhiyunswctrlmapext_2g=0x00000000,0x00000000,0x00000000,0x000000,0x000 79*4882a593Smuzhiyunswctrlmapext_5g=0x00000000,0x00000000,0x00000000,0x000000,0x000 80*4882a593Smuzhiyunfem_table_init_val=0x1131,0x1131 81*4882a593Smuzhiyunnb_papdcalidx=0x280f 82*4882a593Smuzhiyunnb_txattn=0x0303 83*4882a593Smuzhiyunnb_rxattn=0x0303 84*4882a593Smuzhiyunnb_bbmult=0x3948 85*4882a593Smuzhiyunnb_eps_offset=0x01e601ea 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun# RSSI adjust 88*4882a593Smuzhiyunrssi_delta_2g_c0=-2,-2,-2,-2 89*4882a593Smuzhiyunrssi_delta_5gl_c0=-2,-2,-3,-3,-1,-1 90*4882a593Smuzhiyunrssi_delta_5gml_c0=-2,-2,-3,-3,-1,-1 91*4882a593Smuzhiyunrssi_delta_5gmu_c0=0,0,-1,-1,0,0 92*4882a593Smuzhiyunrssi_delta_5gh_c0=-1,-1,-2,-2,0,0 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun# WoWL_GPIO/HOST_WAKE settings 95*4882a593Smuzhiyun#wowl_gpio=0 96*4882a593Smuzhiyun#wowl_polarity=1 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun#ATE related 99*4882a593SmuzhiyunATErcalmode=1 100*4882a593Smuzhiyun 101*4882a593Smuzhiyunswdiv_en=1 #To enable SW-DIV feature 102*4882a593Smuzhiyunswdiv_gpio=0 103*4882a593Smuzhiyunswdiv_swctrl_en=2 104*4882a593Smuzhiyunswdiv_swctrl_ant0=0 105*4882a593Smuzhiyunswdiv_swctrl_ant1=1 106*4882a593Smuzhiyunswdiv_antmap2g_main=1 107*4882a593Smuzhiyunswdiv_antmap5g_main=1 108*4882a593Smuzhiyun 109*4882a593Smuzhiyunswdiv_snrlim=10000 #Only enable sw_div if the snr on present antenna is less than 10000/8=1250 110*4882a593Smuzhiyunswdiv_thresh=2000 #No.of rxpkts threshold 111*4882a593Smuzhiyunswdiv_snrthresh=24 #Difference between antenna's snr is greater than 24/8=3dB, then shift the antennas 112*4882a593Smuzhiyun 113