xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/phl_regulation_def.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2020 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _PHL_REGULATION_DEF_H_
16*4882a593Smuzhiyun #define _PHL_REGULATION_DEF_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define RSVD_DOMAIN 0x1a
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define MAX_CH_NUM_2GHZ 14
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define MAX_CH_NUM_BAND1 4 /* 36, 40, 44, 48 */
23*4882a593Smuzhiyun #define MAX_CH_NUM_BAND2 4 /* 52, 56, 60, 64 */
24*4882a593Smuzhiyun #define MAX_CH_NUM_BAND3 12 /* 100, 104, 108, 112,
25*4882a593Smuzhiyun 				116, 120, 124, 128,
26*4882a593Smuzhiyun 				132, 136, 140, 144 */
27*4882a593Smuzhiyun #define MAX_CH_NUM_BAND4 8 /* 149, 153, 157, 161, 165, 169, 173, 177 */
28*4882a593Smuzhiyun #define MAX_CH_NUM_5GHZ (MAX_CH_NUM_BAND1 + MAX_CH_NUM_BAND2 +\
29*4882a593Smuzhiyun 				MAX_CH_NUM_BAND3 + MAX_CH_NUM_BAND4)
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #define MAX_CH_NUM_UNII5 24 /* 1 ~ 93 */
32*4882a593Smuzhiyun #define MAX_CH_NUM_UNII6 6 /* 97 ~ 117 */
33*4882a593Smuzhiyun #define MAX_CH_NUM_UNII7 18 /* 121 ~ 189 */
34*4882a593Smuzhiyun #define MAX_CH_NUM_UNII8 12 /* 193 ~ 237 */
35*4882a593Smuzhiyun #define MAX_CH_NUM_6GHZ (MAX_CH_NUM_UNII5 + MAX_CH_NUM_UNII6 +\
36*4882a593Smuzhiyun 				MAX_CH_NUM_UNII7 + MAX_CH_NUM_UNII8)
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun #define BAND_2GHZ(_band_) ((_band_ == BAND_ON_24G) ? true : false)
40*4882a593Smuzhiyun #define BAND_5GHZ(_band_) ((_band_ == BAND_ON_5G) ? true : false)
41*4882a593Smuzhiyun #define BAND_6GHZ(_band_) ((_band_ == BAND_ON_6G) ? true : false)
42*4882a593Smuzhiyun #define CH_5GHZ_BAND1(_ch_) (((_ch_ >= 36) && (_ch_ <= 48)) ? true : false)
43*4882a593Smuzhiyun #define CH_5GHZ_BAND2(_ch_) (((_ch_ >= 52) && (_ch_ <= 64)) ? true : false)
44*4882a593Smuzhiyun #define CH_5GHZ_BAND3(_ch_) (((_ch_ >= 100) && (_ch_ <= 144)) ? true : false)
45*4882a593Smuzhiyun #define CH_5GHZ_BAND4(_ch_) (((_ch_ >= 149) && (_ch_ <= 177)) ? true : false)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun #define SUPPORT_11A BIT(0)
48*4882a593Smuzhiyun #define SUPPORT_11B BIT(1)
49*4882a593Smuzhiyun #define SUPPORT_11G BIT(2)
50*4882a593Smuzhiyun #define SUPPORT_11N BIT(3)
51*4882a593Smuzhiyun #define SUPPORT_11AC BIT(4)
52*4882a593Smuzhiyun #define SUPPORT_11AX BIT(5)
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun enum regulation_rsn {
55*4882a593Smuzhiyun 	REGU_RSN_DEFAULT = 0x0,
56*4882a593Smuzhiyun 	REGU_RSN_SMBIOS,
57*4882a593Smuzhiyun 	REGU_RSN_EFUSE,
58*4882a593Smuzhiyun 	REGU_RSN_11D,
59*4882a593Smuzhiyun 	REGU_RSN_REGISTRY,
60*4882a593Smuzhiyun 	REGU_RSN_LOCATION,
61*4882a593Smuzhiyun 	REGU_RSN_MANUAL,
62*4882a593Smuzhiyun 	REGU_RSN_MAX
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun enum rtw_regulation_capability {
66*4882a593Smuzhiyun 	CAPABILITY_2GHZ = BIT(0),
67*4882a593Smuzhiyun 	CAPABILITY_5GHZ = BIT(1),
68*4882a593Smuzhiyun 	CAPABILITY_DFS = BIT(2),
69*4882a593Smuzhiyun 	CAPABILITY_6GHZ = BIT(3)
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun enum rtw_regulation_query {
73*4882a593Smuzhiyun 	REGULQ_CHPLAN_FULL = 0x0,
74*4882a593Smuzhiyun 	REGULQ_CHPLAN_2GHZ,
75*4882a593Smuzhiyun 	REGULQ_CHPLAN_5GHZ_ALL,
76*4882a593Smuzhiyun 	REGULQ_CHPLAN_5GHZ_BAND1,
77*4882a593Smuzhiyun 	REGULQ_CHPLAN_5GHZ_BAND2,
78*4882a593Smuzhiyun 	REGULQ_CHPLAN_5GHZ_BAND3,
79*4882a593Smuzhiyun 	REGULQ_CHPLAN_5GHZ_BAND4,
80*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ_UNII5,
81*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ_UNII6,
82*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ_UNII7,
83*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ_UNII8,
84*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ,
85*4882a593Smuzhiyun 	REGULQ_CHPLAN_6GHZ_PSC,
86*4882a593Smuzhiyun 	REGULQ_CHPLAN_2GHZ_5GHZ,
87*4882a593Smuzhiyun };
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun enum ch_property {
90*4882a593Smuzhiyun 	CH_PASSIVE = BIT(0), /* regulatory passive channel */
91*4882a593Smuzhiyun 	CH_DFS = BIT(1), /* 5 ghz DFS channel */
92*4882a593Smuzhiyun 	CH_PSC = BIT(2) /* 6 ghz preferred scanning channel */
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun struct rtw_regulation_channel {
96*4882a593Smuzhiyun 	enum band_type band;
97*4882a593Smuzhiyun 	u8 channel;
98*4882a593Smuzhiyun 	u8 property;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct rtw_regulation_chplan {
102*4882a593Smuzhiyun 	u32 cnt;
103*4882a593Smuzhiyun 	struct rtw_regulation_channel ch[MAX_CH_NUM_2GHZ +
104*4882a593Smuzhiyun 					MAX_CH_NUM_5GHZ +
105*4882a593Smuzhiyun 					MAX_CH_NUM_6GHZ];
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun struct rtw_ch {
109*4882a593Smuzhiyun 	enum band_type band;
110*4882a593Smuzhiyun 	u8 ch;
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun struct rtw_chlist {
114*4882a593Smuzhiyun 	u32 cnt;
115*4882a593Smuzhiyun 	struct rtw_ch ch[MAX_CH_NUM_2GHZ +
116*4882a593Smuzhiyun 			MAX_CH_NUM_5GHZ +
117*4882a593Smuzhiyun 			MAX_CH_NUM_6GHZ];
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun struct rtw_regulation_info {
121*4882a593Smuzhiyun 	u8 domain_code;
122*4882a593Smuzhiyun 	u8 domain_reason;
123*4882a593Smuzhiyun 	u8 domain_code_6g;
124*4882a593Smuzhiyun 	u8 domain_reason_6g;
125*4882a593Smuzhiyun 	char country[2];
126*4882a593Smuzhiyun 	u8 support_mode;
127*4882a593Smuzhiyun 	u8 regulation_2g;
128*4882a593Smuzhiyun 	u8 regulation_5g;
129*4882a593Smuzhiyun 	u8 regulation_6g;
130*4882a593Smuzhiyun 	u8 tpo;
131*4882a593Smuzhiyun 	u8 chplan_ver;
132*4882a593Smuzhiyun 	u8 country_ver;
133*4882a593Smuzhiyun 	u16 capability;
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun struct rtw_regulation_country_chplan {
137*4882a593Smuzhiyun 	u8 domain_code;
138*4882a593Smuzhiyun 	u8 support_mode;
139*4882a593Smuzhiyun 	/*
140*4882a593Smuzhiyun 	* bit0: accept 11a
141*4882a593Smuzhiyun 	* bit1: accept 11b
142*4882a593Smuzhiyun 	* bit2: accept 11g
143*4882a593Smuzhiyun 	* bit3: accept 11n
144*4882a593Smuzhiyun 	* bit4: accept 11ac
145*4882a593Smuzhiyun 	* bit5: accept 11ax
146*4882a593Smuzhiyun 	*/
147*4882a593Smuzhiyun 	u8 tpo; /* tx power overwrite */
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun struct rtw_user_def_chplan {
151*4882a593Smuzhiyun 	u16 ch2g; /* bit0 ~ bit13 : ch1~ch14 */
152*4882a593Smuzhiyun 	u16 passive2g; /* bit0 ~ bit13 : ch1~ch14, if value = 1, means passive for that channel */
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/* 5g channels.
155*4882a593Smuzhiyun 	 * bit0~7 : ch 36/40/44/48/52/56/60/64
156*4882a593Smuzhiyun 	 * bit8~15 : ch 100/104/108/112/116/120/124/128
157*4882a593Smuzhiyun 	 * bit16~23 : ch 132/136/140/144/149/153/157/161
158*4882a593Smuzhiyun 	 * bit24~27 : ch 165/169/173/177
159*4882a593Smuzhiyun 	 */
160*4882a593Smuzhiyun 	u32 ch5g;
161*4882a593Smuzhiyun 	u32 passive5g;
162*4882a593Smuzhiyun 	u32 dfs5g;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	u32 regulatory_idx;
165*4882a593Smuzhiyun 	u8 tpo;
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun /*
169*4882a593Smuzhiyun  * NOTE:
170*4882a593Smuzhiyun  * 	This api prototype will be removed after hal related API/header is added
171*4882a593Smuzhiyun  * 	for halrf.
172*4882a593Smuzhiyun  */
173*4882a593Smuzhiyun bool rtw_phl_query_regulation_info(void *phl, struct rtw_regulation_info *info);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun #endif /* _PHL_REGULATION_DEF_H_ */
176