xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/phl_config.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2019 - 2021 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _PHL_CONFIG_H_
16*4882a593Smuzhiyun #define _PHL_CONFIG_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun /* Define correspoding PHL Feature based on information from the Core */
19*4882a593Smuzhiyun #ifdef PHL_PLATFORM_AP
20*4882a593Smuzhiyun #define PHL_FEATURE_AP
21*4882a593Smuzhiyun #elif defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS)
22*4882a593Smuzhiyun #define PHL_FEATURE_NIC
23*4882a593Smuzhiyun #else
24*4882a593Smuzhiyun #define PHL_FEATURE_NONE
25*4882a593Smuzhiyun #endif
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /******************* PLATFORM Section **************************/
28*4882a593Smuzhiyun #ifdef PHL_FEATURE_NONE/* enable compile flag for phl only compilation check */
29*4882a593Smuzhiyun 	#define CONFIG_DFS 1
30*4882a593Smuzhiyun 	#define CONFIG_USB_TX_AGGREGATION
31*4882a593Smuzhiyun 	#define CONFIG_USB_RX_AGGREGATION
32*4882a593Smuzhiyun 	#define CONFIG_USB_TX_PADDING_CHK
33*4882a593Smuzhiyun 	#define CONFIG_LOAD_PHY_PARA_FROM_FILE
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun 	#define CONFIG_WOW
36*4882a593Smuzhiyun 	#define CONFIG_WPA3_SUITEB_SUPPORT
37*4882a593Smuzhiyun 	#define CONFIG_SYNC_INTERRUPT
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun 	#define CONFIG_MR_SUPPORT
40*4882a593Smuzhiyun 	#ifdef CONFIG_MR_SUPPORT
41*4882a593Smuzhiyun 		#define CONFIG_SCC_SUPPORT
42*4882a593Smuzhiyun 		#define CONFIG_MCC_SUPPORT
43*4882a593Smuzhiyun 		#ifdef CONFIG_MCC_SUPPORT
44*4882a593Smuzhiyun 			#define MCC_ROLE_NUM 2
45*4882a593Smuzhiyun 			#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
46*4882a593Smuzhiyun 			#define RTW_WKARD_HALRF_MCC
47*4882a593Smuzhiyun 			#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
48*4882a593Smuzhiyun 		#endif /*CONFIG_MCC_SUPPORT*/
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 		#define CONFIG_DBCC_SUPPORT
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 		#define DBG_PHL_CHAN
53*4882a593Smuzhiyun 		#define DBG_PHL_MR
54*4882a593Smuzhiyun 		#define PHL_MR_PROC_CMD
55*4882a593Smuzhiyun 		#define DBG_CHCTX_RMAP
56*4882a593Smuzhiyun 	#endif /*CONFIG_MR_SUPPORT*/
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	#define DBG_PHL_MAC_REG_RW
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun 	#define CONFIG_RTW_ACS
61*4882a593Smuzhiyun 	#define CONFIG_RX_PSTS_PER_PKT
62*4882a593Smuzhiyun 
63*4882a593Smuzhiyun 	#define CONFIG_PHL_TXSC
64*4882a593Smuzhiyun 	#define RTW_PHL_BCN
65*4882a593Smuzhiyun 	#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
66*4882a593Smuzhiyun 	#define CONFIG_PHL_TWT
67*4882a593Smuzhiyun 	#define CONFIG_CMD_DISP
68*4882a593Smuzhiyun 	#ifdef CONFIG_CMD_DISP
69*4882a593Smuzhiyun 		#define CONFIG_PHL_ECSA
70*4882a593Smuzhiyun 		/*#define CONFIG_CMD_DISP_SOLO_MODE*/
71*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_SCAN
72*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_SER
73*4882a593Smuzhiyun 		#define CONFIG_PHL_CMD_BTC
74*4882a593Smuzhiyun 	#endif
75*4882a593Smuzhiyun 	#ifdef CONFIG_PCI_HCI
76*4882a593Smuzhiyun 		#define PCIE_TRX_MIT_EN
77*4882a593Smuzhiyun 	#endif
78*4882a593Smuzhiyun 	#define CONFIG_PHL_P2PPS
79*4882a593Smuzhiyun 	#define CONFIG_6GHZ
80*4882a593Smuzhiyun 	#define RTW_WKARD_BFEE_SET_AID
81*4882a593Smuzhiyun 	#define CONFIG_PHL_THERMAL_PROTECT
82*4882a593Smuzhiyun 	#define CONFIG_PHL_TX_DBG
83*4882a593Smuzhiyun #endif /* PHL_FEATURE_NONE */
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
86*4882a593Smuzhiyun 	#ifndef CONFIG_FSM
87*4882a593Smuzhiyun 		#define CONFIG_FSM
88*4882a593Smuzhiyun 	#endif
89*4882a593Smuzhiyun 	#ifndef CONFIG_CMD_DISP
90*4882a593Smuzhiyun 		#define CONFIG_CMD_DISP
91*4882a593Smuzhiyun 	#endif
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #ifdef PHL_PLATFORM_LINUX
95*4882a593Smuzhiyun 	/* comment out cfg temporarily */
96*4882a593Smuzhiyun 	/*
97*4882a593Smuzhiyun 	#define CONFIG_FSM
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun 	#ifndef CONFIG_FSM
100*4882a593Smuzhiyun 		#define CONFIG_CMD_DISP
101*4882a593Smuzhiyun 	#endif
102*4882a593Smuzhiyun 	*/
103*4882a593Smuzhiyun #endif
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /******************* Feature flags **************************/
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun #ifdef CONFIG_PHL_TEST_SUITE
108*4882a593Smuzhiyun #define CONFIG_PHL_TEST_MP
109*4882a593Smuzhiyun #define CONFIG_PHL_TEST_VERIFY
110*4882a593Smuzhiyun #endif
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #ifdef CONFIG_CORE_SYNC_INTERRUPT
113*4882a593Smuzhiyun #define CONFIG_SYNC_INTERRUPT
114*4882a593Smuzhiyun #endif
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #ifdef CONFIG_WOW
117*4882a593Smuzhiyun #define CONFIG_WOWLAN
118*4882a593Smuzhiyun /* #define RTW_WKARD_WOW_SKIP_AOAC_RPT */
119*4882a593Smuzhiyun /* #define RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG */
120*4882a593Smuzhiyun #define RTW_WKARD_WOW_L2_PWR
121*4882a593Smuzhiyun #define DBG_RST_BDRAM_TIME
122*4882a593Smuzhiyun #endif
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define DBG_PHY_ON_TIME
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /*CONFIG_IFACE_NUMBER*/
127*4882a593Smuzhiyun #ifdef CONFIG_IFACE_NUMBER
128*4882a593Smuzhiyun #define MAX_WIFI_ROLE_NUMBER CONFIG_IFACE_NUMBER
129*4882a593Smuzhiyun #else
130*4882a593Smuzhiyun #define MAX_WIFI_ROLE_NUMBER 5
131*4882a593Smuzhiyun #endif
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
134*4882a593Smuzhiyun #define CONFIG_MR_SUPPORT
135*4882a593Smuzhiyun #endif
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun #ifdef CONFIG_REUSED_FWDL_BUF
138*4882a593Smuzhiyun 	#define CONFIG_PHL_REUSED_FWDL_BUF
139*4882a593Smuzhiyun #endif
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun #ifdef CONFIG_MR_SUPPORT
142*4882a593Smuzhiyun #define CONFIG_SCC_SUPPORT
143*4882a593Smuzhiyun #define CONFIG_MCC_SUPPORT
144*4882a593Smuzhiyun #ifdef CONFIG_MCC_SUPPORT
145*4882a593Smuzhiyun #define MCC_ROLE_NUM 2
146*4882a593Smuzhiyun #define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
147*4882a593Smuzhiyun #define RTW_WKARD_HALRF_MCC
148*4882a593Smuzhiyun #define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
149*4882a593Smuzhiyun #endif /*CONFIG_MCC_SUPPORT*/
150*4882a593Smuzhiyun /*#define CONFIG_DBCC_SUPPORT*/
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #define DBG_PHL_CHAN
153*4882a593Smuzhiyun #define DBG_PHL_MR
154*4882a593Smuzhiyun #define PHL_MR_PROC_CMD
155*4882a593Smuzhiyun #define DBG_CHCTX_RMAP
156*4882a593Smuzhiyun #endif
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun #define DBG_PHL_STAINFO
159*4882a593Smuzhiyun #define PHL_MAX_STA_NUM 128
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun /**** CONFIG_CMD_DISP ***/
162*4882a593Smuzhiyun #ifdef DISABLE_CMD_DISPR
163*4882a593Smuzhiyun #undef CONFIG_CMD_DISP
164*4882a593Smuzhiyun #endif
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #ifdef CONFIG_CMD_DISP
167*4882a593Smuzhiyun /* enable SOLO mode define to create seperated background thread per dispatcher,
168*4882a593Smuzhiyun  * otherwise, all dispatcher would share single background thread, which is in share mode.
169*4882a593Smuzhiyun */
170*4882a593Smuzhiyun /*#define CONFIG_CMD_DISP_SOLO_MODE*/
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun /* Enable Self-Defined Sequence feature for sender to rearrange dispatch order,
173*4882a593Smuzhiyun  * Since this is not a mandatory feature and would have addiional memory cost (arround 2200 Bytes)
174*4882a593Smuzhiyun  * Disable by default.
175*4882a593Smuzhiyun */
176*4882a593Smuzhiyun /*#define CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ*/
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #ifndef CONFIG_FSM
179*4882a593Smuzhiyun 	#define CONFIG_SND_CMD
180*4882a593Smuzhiyun #endif
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define CONFIG_PHL_CMD_SCAN
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #ifdef CONFIG_CMD_SER
185*4882a593Smuzhiyun #define CONFIG_PHL_CMD_SER
186*4882a593Smuzhiyun #endif
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun #define CONFIG_PHL_CMD_BTC
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #ifdef CONFIG_MSG_NUM
191*4882a593Smuzhiyun 	#define CONFIG_PHL_MSG_NUM CONFIG_MSG_NUM
192*4882a593Smuzhiyun #endif
193*4882a593Smuzhiyun #endif /**** CONFIG_CMD_DISP ***/
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun #define CONFIG_GEN_GIT_INFO 1
196*4882a593Smuzhiyun /*#define CONFIG_NEW_HALMAC_INTERFACE*/
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #define CONFIG_BTCOEX
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_PADDING_CHK
201*4882a593Smuzhiyun #define CONFIG_PHL_USB_TX_PADDING_CHK
202*4882a593Smuzhiyun #endif
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_AGGREGATION
205*4882a593Smuzhiyun #define CONFIG_PHL_USB_TX_AGGREGATION
206*4882a593Smuzhiyun #endif
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun #ifdef CONFIG_USB_RX_AGGREGATION
209*4882a593Smuzhiyun #define CONFIG_PHL_USB_RX_AGGREGATION
210*4882a593Smuzhiyun #endif
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun #ifdef CONFIG_DFS_MASTER
213*4882a593Smuzhiyun #define CONFIG_PHL_DFS
214*4882a593Smuzhiyun #endif
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun #ifdef CONFIG_PHL_DFS
217*4882a593Smuzhiyun /*#define CONFIG_PHL_DFS_REGD_FCC*/
218*4882a593Smuzhiyun /*#define CONFIG_PHL_DFS_REGD_JAP*/
219*4882a593Smuzhiyun #define CONFIG_PHL_DFS_REGD_ETSI
220*4882a593Smuzhiyun #endif
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #ifdef CONFIG_WPP
223*4882a593Smuzhiyun #define CONFIG_PHL_WPP
224*4882a593Smuzhiyun #endif
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
227*4882a593Smuzhiyun #define CONFIG_PHL_CSUM_OFFLOAD_RX
228*4882a593Smuzhiyun #endif
229*4882a593Smuzhiyun 
230*4882a593Smuzhiyun #ifdef CONFIG_RX_PSTS_PER_PKT
231*4882a593Smuzhiyun #define CONFIG_PHL_RX_PSTS_PER_PKT
232*4882a593Smuzhiyun #define RTW_WKARD_DISABLE_PSTS_PER_PKT_DATA
233*4882a593Smuzhiyun #endif
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun #ifdef CONFIG_SDIO_RX_NETBUF_ALLOC_IN_PHL
236*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
237*4882a593Smuzhiyun #endif
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun #ifdef CONFIG_SDIO_READ_RXFF_IN_INT
240*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_READ_RXFF_IN_INT
241*4882a593Smuzhiyun #endif
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun #ifdef CONFIG_ECSA
244*4882a593Smuzhiyun #define CONFIG_PHL_ECSA
245*4882a593Smuzhiyun #ifdef CONFIG_ECSA_EXTEND_OPTION
246*4882a593Smuzhiyun #define CONFIG_PHL_ECSA_EXTEND_OPTION
247*4882a593Smuzhiyun #endif
248*4882a593Smuzhiyun #endif
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun #ifdef CONFIG_TWT
251*4882a593Smuzhiyun #define CONFIG_PHL_TWT
252*4882a593Smuzhiyun #endif
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun #ifdef CONFIG_RA_TXSTS_DBG
255*4882a593Smuzhiyun #define CONFIG_PHL_RA_TXSTS_DBG
256*4882a593Smuzhiyun #endif
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun #ifdef CONFIG_USB_RELEASE_RPT
259*4882a593Smuzhiyun #define CONFIG_PHL_USB_RELEASE_RPT_ENABLE
260*4882a593Smuzhiyun #endif
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun #ifdef CONFIG_PS_FW_DBG
263*4882a593Smuzhiyun #define CONFIG_PHL_PS_FW_DBG
264*4882a593Smuzhiyun #endif
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun #ifdef CONFIG_P2PPS
267*4882a593Smuzhiyun #define CONFIG_PHL_P2PPS
268*4882a593Smuzhiyun #endif
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun #ifdef CONFIG_TX_DBG
271*4882a593Smuzhiyun #define CONFIG_PHL_TX_DBG
272*4882a593Smuzhiyun #endif
273*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
274*4882a593Smuzhiyun #ifdef CONFIG_PCIE_TRX_MIT
275*4882a593Smuzhiyun #define PCIE_TRX_MIT_EN
276*4882a593Smuzhiyun #endif
277*4882a593Smuzhiyun #endif
278*4882a593Smuzhiyun #ifdef CONFIG_THERMAL_PROTECT
279*4882a593Smuzhiyun #define CONFIG_PHL_THERMAL_PROTECT
280*4882a593Smuzhiyun #endif
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun #ifdef CONFIG_RX_BATCH_IND
283*4882a593Smuzhiyun #define PHL_RX_BATCH_IND
284*4882a593Smuzhiyun #endif
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun #ifdef CONFIG_TDLS
287*4882a593Smuzhiyun #define CONFIG_PHL_TDLS
288*4882a593Smuzhiyun #endif
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
291*4882a593Smuzhiyun /* For SDIO TX TP TST - START */
292*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_AGG_NUM_MAX
293*4882a593Smuzhiyun #define PHL_SDIO_TX_AGG_MAX	CONFIG_SDIO_TX_AGG_NUM_MAX
294*4882a593Smuzhiyun #endif /* CONFIG_SDIO_TX_AGG_NUM_MAX */
295*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_TX_CB_THREAD
296*4882a593Smuzhiyun /*
297*4882a593Smuzhiyun  * RTW_WKARD_SDIO_TX_USE_YIELD
298*4882a593Smuzhiyun  * Define this would use yield() instead of event wait mechanism to improve
299*4882a593Smuzhiyun  * throughput on Linux platform.
300*4882a593Smuzhiyun  * But yield() doesn't been encouraged to use in Linux,
301*4882a593Smuzhiyun  * so if we figure out what happened and find another way to improve
302*4882a593Smuzhiyun  * throughput, this workaround would be removed later.
303*4882a593Smuzhiyun  *
304*4882a593Smuzhiyun  * RTW_WKARD_SDIO_TX_USE_YIELD is depended on CONFIG_PHL_SDIO_TX_CB_THREAD,
305*4882a593Smuzhiyun  * because the mechanism only been used with CONFIG_PHL_SDIO_TX_CB_THREAD.
306*4882a593Smuzhiyun  *
307*4882a593Smuzhiyun  * Usually this flag would be defined from core layer.
308*4882a593Smuzhiyun  */
309*4882a593Smuzhiyun /*#define RTW_WKARD_SDIO_TX_USE_YIELD*/
310*4882a593Smuzhiyun #define SDIO_TX_THREAD			/* Use dedicate thread for SDIO TX */
311*4882a593Smuzhiyun /* For SDIO TX TP TST - ENDT */
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun /* For SDIO RX TP TST - START */
314*4882a593Smuzhiyun #define CONFIG_PHL_SDIO_RX_CB_THREAD
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun #define PHL_DIS_CTRL_FRAME_TO_HOST
317*4882a593Smuzhiyun #ifdef PHL_DIS_CTRL_FRAME_TO_HOST
318*4882a593Smuzhiyun /* Disable ALL CTRL frame report to host */
319*4882a593Smuzhiyun #define PHL_DIS_CTRL_FRAME_TO_HOST_ALL		0
320*4882a593Smuzhiyun /* Disable ACK + BA + RTS + CTS frame report to host */
321*4882a593Smuzhiyun #define PHL_DIS_CTRL_FRAME_TO_HOST_POLICY_1	1
322*4882a593Smuzhiyun #define PHL_DIS_CTRL_FRAME_TO_HOST_POLICY	PHL_DIS_CTRL_FRAME_TO_HOST_POLICY_1
323*4882a593Smuzhiyun #endif
324*4882a593Smuzhiyun /* For SDIO RX TP TST - END */
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
327*4882a593Smuzhiyun 
328*4882a593Smuzhiyun #ifdef CONFIG_MAC_REG_RW_CHK
329*4882a593Smuzhiyun #define DBG_PHL_MAC_REG_RW
330*4882a593Smuzhiyun #endif
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun /******************* WKARD flags **************************/
333*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_REFINE
334*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_SINGLE_NOA
335*4882a593Smuzhiyun #define RTW_WKARD_P2PPS_NOA_MCC
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun #ifdef PHL_PLATFORM_LINUX
338*4882a593Smuzhiyun #define RTW_WKARD_RF_CR_DUMP
339*4882a593Smuzhiyun #define RTW_WKARD_LINUX_CMD_WKARD
340*4882a593Smuzhiyun #endif
341*4882a593Smuzhiyun 
342*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
343*4882a593Smuzhiyun /* Workaround for doing hal reset in changing MP mode will lost the mac entry */
344*4882a593Smuzhiyun #define RTW_WKARD_MP_MODE_CHANGE
345*4882a593Smuzhiyun #define RTW_WKARD_WIN_TRX_BALANCE
346*4882a593Smuzhiyun #define RTW_WKARD_DYNAMIC_LTR
347*4882a593Smuzhiyun #endif
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun #define RTW_WKARD_PHY_CAP
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun #define RTW_WKARD_LAMODE
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun #define RTW_WKARD_TXSC
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun #define RTW_WKARD_BB_C2H
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun /*
358*4882a593Smuzhiyun  * One workaround of EFUSE operation
359*4882a593Smuzhiyun  *  1. Dump EFUSE with FW fail
360*4882a593Smuzhiyun  */
361*4882a593Smuzhiyun #define RTW_WKARD_EFUSE_OPERATION
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun #define RTW_WKARD_STA_BCN_INTERVAL
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun #define RTW_WKARD_SER_L1_EXPIRE
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
368*4882a593Smuzhiyun #define RTW_WKARD_SER_USB_POLLING_EVENT
369*4882a593Smuzhiyun #endif
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun /* #define RTW_WKARD_SER_USB_DISABLE_L1_RCVY_FLOW */
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun #define RTW_WKARD_BTC_RFETYPE
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun #define RTW_WKARD_TXBD_UPD_LMT 	/* 8852AE/8852BE txbd index update limitation */
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun #ifdef CONFIG_WPA3_SUITEB_SUPPORT
378*4882a593Smuzhiyun #define RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
379*4882a593Smuzhiyun #endif
380*4882a593Smuzhiyun 
381*4882a593Smuzhiyun /* Workaround for cmac table config
382*4882a593Smuzhiyun  * - Default is disabled until halbb is ready
383*4882a593Smuzhiyun  * - This workaround will be removed once fw handles this cfg
384*4882a593Smuzhiyun  */
385*4882a593Smuzhiyun /*#define RTW_WKARD_DEF_CMACTBL_CFG*/
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun /* Workaround for efuse read hidden report
388*4882a593Smuzhiyun  * - Default is disabled until halmac is ready
389*4882a593Smuzhiyun  */
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun #define RTW_WKARD_PRELOAD_TRX_RESET
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun /* Workaround for cmac table config
394*4882a593Smuzhiyun  * - This workaround will be removed once fw handles this cfg
395*4882a593Smuzhiyun  */
396*4882a593Smuzhiyun #define RTW_WKARD_DEF_CMACTBL_CFG
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun #define RTW_WKARD_USB_TXAGG_BULK_END_WD
399*4882a593Smuzhiyun #ifdef CONFIG_HOMOLOGATION
400*4882a593Smuzhiyun #define CONFIG_PHL_HOMOLOGATION
401*4882a593Smuzhiyun #endif
402*4882a593Smuzhiyun 
403*4882a593Smuzhiyun #ifdef RTW_WKARD_TX_DISABLE_BFEE
404*4882a593Smuzhiyun #define RTW_WKARD_DYNAMIC_BFEE_CAP
405*4882a593Smuzhiyun #endif
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun #ifdef RTW_WKARD_NTFY_MEDIA_STS
408*4882a593Smuzhiyun #define RTW_WKARD_PHL_NTFY_MEDIA_STS
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun #ifdef RTW_WKARD_PHY_INFO_NTFY
412*4882a593Smuzhiyun #define CONFIG_PHY_INFO_NTFY
413*4882a593Smuzhiyun #endif
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
416*4882a593Smuzhiyun #define CONFIG_WOW_WITH_SER
417*4882a593Smuzhiyun #endif
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun #ifdef PHL_PLATFORM_WINDOWS
420*4882a593Smuzhiyun #define CONFIG_DBG_H2C_TX
421*4882a593Smuzhiyun #endif
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun /*
424*4882a593Smuzhiyun  * Workaround for MRC bk module call phl_mr_offch_hdl with scan_issue_null_data
425*4882a593Smuzhiyun  * ops, this should be replaced with phl issue null data function.
426*4882a593Smuzhiyun  */
427*4882a593Smuzhiyun #define RTW_WKARD_MRC_ISSUE_NULL_WITH_SCAN_OPS
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun /*
430*4882a593Smuzhiyun  * Workaround for phl_mr_offch_hdl sleep after issue null data,
431*4882a593Smuzhiyun  * - This workaround will be removed once tx report is ready
432*4882a593Smuzhiyun  */
433*4882a593Smuzhiyun #ifndef RTW_WKARD_TX_NULL_WD_RP
434*4882a593Smuzhiyun #define RTW_WKARD_ISSUE_NULL_SLEEP_PROTECTION
435*4882a593Smuzhiyun #endif
436*4882a593Smuzhiyun #ifdef RTW_WKARD_LPS_IQK_TWICE
437*4882a593Smuzhiyun #define RTW_WKARD_PHL_LPS_IQK_TWICE
438*4882a593Smuzhiyun #endif
439*4882a593Smuzhiyun 
440*4882a593Smuzhiyun #ifdef RTW_WKARD_FSM_SCAN_PASSIVE_TO_ACTIVE
441*4882a593Smuzhiyun #define RTW_WKARD_PHL_FSM_SCAN_PASSIVE_TO_ACTIVE
442*4882a593Smuzhiyun #endif
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun #define RTW_WKARD_BUSCAP_IN_HALSPEC
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun #define RTW_WKARD_IBSS_SNIFFER_MODE
447*4882a593Smuzhiyun 
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun #define RTW_WKARD_SINGLE_PATH_RSSI
450*4882a593Smuzhiyun 
451*4882a593Smuzhiyun /* #define CONFIG_6GHZ */
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #define RTW_WKARD_BFEE_DISABLE_NG16
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun #define RTW_WKARD_HW_WMM_ALLOCATE
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun #ifdef RTW_WKARD_BFEE_AID
459*4882a593Smuzhiyun #define RTW_WKARD_BFEE_SET_AID
460*4882a593Smuzhiyun #endif
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun #define RTW_WKARD_AP_CLIENT_ADD_DEL_NTY
463*4882a593Smuzhiyun 
464*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
465*4882a593Smuzhiyun #define RTW_WKARD_TX_TP	/* Improve TX throughput by busy loop */
466*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
467*4882a593Smuzhiyun 
468*4882a593Smuzhiyun #ifdef RTW_WKARD_DISABLE_2G40M_ULOFDMA
469*4882a593Smuzhiyun #define RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
470*4882a593Smuzhiyun #endif
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun #endif /*_PHL_CONFIG_H_*/
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