1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2020 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _PHL_CHNLPLAN_H_ 16*4882a593Smuzhiyun #define _PHL_CHNLPLAN_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define REGULATION_CHPLAN_VERSION 58 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun enum REGULATION { 21*4882a593Smuzhiyun REGULATION_WW = 0, 22*4882a593Smuzhiyun REGULATION_ETSI = 1, 23*4882a593Smuzhiyun REGULATION_FCC = 2, 24*4882a593Smuzhiyun REGULATION_MKK = 3, 25*4882a593Smuzhiyun REGULATION_KCC = 4, 26*4882a593Smuzhiyun REGULATION_NCC = 5, 27*4882a593Smuzhiyun REGULATION_ACMA = 6, 28*4882a593Smuzhiyun REGULATION_NA = 7, 29*4882a593Smuzhiyun REGULATION_IC = 8, 30*4882a593Smuzhiyun REGULATION_CHILE = 9, 31*4882a593Smuzhiyun REGULATION_MEX = 10, 32*4882a593Smuzhiyun REGULATION_MAX = 11, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct chdef_2ghz { 36*4882a593Smuzhiyun /* ch_def index */ 37*4882a593Smuzhiyun u8 idx; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* support channel list 40*4882a593Smuzhiyun * support_ch[0]: bit(0~7) stands for ch(1~8) 41*4882a593Smuzhiyun * support_ch[1]: bit(0~5) stands for ch (9~14) 42*4882a593Smuzhiyun */ 43*4882a593Smuzhiyun u8 support_ch[2]; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* passive ch list 46*4882a593Smuzhiyun * passive[0]: bit(0~7) stands for ch(1~8) 47*4882a593Smuzhiyun * passive[1]: bit(0~5) stands for ch (9~14) 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun u8 passive[2]; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct chdef_5ghz { 53*4882a593Smuzhiyun /* ch_def index */ 54*4882a593Smuzhiyun u8 idx; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* 57*4882a593Smuzhiyun * band1 support channel list, passive and dfs 58*4882a593Smuzhiyun * bit0 stands for ch36 59*4882a593Smuzhiyun * bit1 stands for ch40 60*4882a593Smuzhiyun * bit2 stands for ch44 61*4882a593Smuzhiyun * bit3 stands for ch48 62*4882a593Smuzhiyun */ 63*4882a593Smuzhiyun u8 support_ch_b1; 64*4882a593Smuzhiyun u8 passive_b1; 65*4882a593Smuzhiyun u8 dfs_b1; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * band2 support channel list, passive and dfs 69*4882a593Smuzhiyun * bit0 stands for ch52 70*4882a593Smuzhiyun * bit1 stands for ch56 71*4882a593Smuzhiyun * bit2 stands for ch60 72*4882a593Smuzhiyun * bit3 stands for ch64 73*4882a593Smuzhiyun */ 74*4882a593Smuzhiyun u8 support_ch_b2; 75*4882a593Smuzhiyun u8 passive_b2; 76*4882a593Smuzhiyun u8 dfs_b2; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * band3 support channel list, passive and dfs 80*4882a593Smuzhiyun * byte[0]: 81*4882a593Smuzhiyun * bit0 stands for ch100 82*4882a593Smuzhiyun * bit1 stands for ch104 83*4882a593Smuzhiyun * bit2 stands for ch108 84*4882a593Smuzhiyun * bit3 stands for ch112 85*4882a593Smuzhiyun * bit4 stands for ch116 86*4882a593Smuzhiyun * bit5 stands for ch120 87*4882a593Smuzhiyun * bit6 stands for ch124 88*4882a593Smuzhiyun * bit7 stands for ch128 89*4882a593Smuzhiyun * byte[1]: 90*4882a593Smuzhiyun * bit0 stands for ch132 91*4882a593Smuzhiyun * bit1 stands for ch136 92*4882a593Smuzhiyun * bit2 stands for ch140 93*4882a593Smuzhiyun * bit3 stands for ch144 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun u8 support_ch_b3[2]; 96*4882a593Smuzhiyun u8 passive_b3[2]; 97*4882a593Smuzhiyun u8 dfs_b3[2]; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * band4 support channel list, passive and dfs 101*4882a593Smuzhiyun * bit0 stands for ch149 102*4882a593Smuzhiyun * bit1 stands for ch153 103*4882a593Smuzhiyun * bit2 stands for ch157 104*4882a593Smuzhiyun * bit3 stands for ch161 105*4882a593Smuzhiyun * bit4 stands for ch165 106*4882a593Smuzhiyun * bit5 stands for ch169 107*4882a593Smuzhiyun * bit6 stands for ch173 108*4882a593Smuzhiyun * bit7 stands for ch177 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun u8 support_ch_b4; 111*4882a593Smuzhiyun u8 passive_b4; 112*4882a593Smuzhiyun u8 dfs_b4; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct freq_plan { 116*4882a593Smuzhiyun u8 regulation; 117*4882a593Smuzhiyun u8 ch_idx; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct regulatory_domain_mapping { 121*4882a593Smuzhiyun u8 domain_code; 122*4882a593Smuzhiyun struct freq_plan freq_2g; 123*4882a593Smuzhiyun struct freq_plan freq_5g; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define MAX_CHDEF_2GHZ 7 127*4882a593Smuzhiyun #define MAX_CHDEF_5GHZ 54 128*4882a593Smuzhiyun #define MAX_RD_MAP_NUM 108 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #endif /* _PHL_CHNLPLAN_H_ */ 133