1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2020 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __HALBB_H__ 27 #define __HALBB_H__ 28 29 /*@--------------------------[Define] ---------------------------------------*/ 30 31 #define ACTIVE_TP_THRESHOLD 1 32 #define BB_WATCH_DOG_PERIOD 2 /*sec*/ 33 #define is_sta_active(sta) ((sta) && (sta->active)) 34 #define HALBB_SNPRINT_SIZE 200 35 #define HALBB_SNPRINT_SIZE_S 20 36 37 #define BB_EFUSE_BAND_NUM 5 38 #define IC_LNA_NUM 7 39 #define IC_TIA_NUM 2 40 #define EFUSE_OFST_NUM 1 41 42 /*@--------------------------[Enum]------------------------------------------*/ 43 44 enum bb_trx_state_t { 45 BB_TX_STATE = 0, 46 BB_RX_STATE = 1, 47 BB_BI_DIR_STATE = 2 48 }; 49 50 enum bb_trafic_t { 51 TRAFFIC_NO_TP = 0, 52 TRAFFIC_ULTRA_LOW = 1, 53 TRAFFIC_LOW = 2, 54 TRAFFIC_MID = 3, 55 TRAFFIC_HIGH = 4 56 }; 57 58 enum efuse_bit_mask { 59 LOW_MASK = 0, 60 HIGH_MASK = 1 61 }; 62 /*@--------------------------[Structure]-------------------------------------*/ 63 64 struct halbb_pause_lv { 65 s8 lv_dig; 66 s8 lv_cfo; 67 s8 lv_edcca; 68 }; 69 70 struct bb_func_hooker_info { 71 void (*pause_bb_dm_handler)(struct bb_info *bb, u32 *val_buf, u8 val_len); 72 }; 73 74 struct bb_iot_info { 75 u8 is_linked_cmw500:1; 76 u8 patch_id_00000000:1; 77 u8 rsvd:6; 78 }; 79 80 struct bb_path_info { 81 /*[Path info]*/ 82 u8 tx_path_en; /*TX path enable*/ 83 u8 rx_path_en; /*RX path enable*/ 84 #ifdef HALBB_COMPILE_ABOVE_4SS 85 enum bb_path tx_4ss_path_map; /*@Use N-X for 4STS rate*/ 86 #endif 87 #ifdef HALBB_COMPILE_ABOVE_3SS 88 enum bb_path tx_3ss_path_map; /*@Use N-X for 3STS rate*/ 89 #endif 90 #ifdef HALBB_COMPILE_ABOVE_2SS 91 enum bb_path tx_2ss_path_map; /*@Use N-X for 2STS rate*/ 92 #endif 93 enum bb_path tx_1ss_path_map; /*@Use N-X for 1STS rate*/ 94 }; 95 96 struct bb_link_info { 97 /*[Link Info]*/ 98 bool is_linked; 99 bool is_linked_pre; 100 bool first_connect; 101 bool first_disconnect; 102 enum bb_trx_state_t txrx_state_all; 103 /*[One Entry TP Info]*/ 104 bool is_one_entry_only; 105 u32 one_entry_macid; 106 u32 one_entry_tp; 107 u32 one_entry_tp_pre; 108 u16 tp_active_th; 109 bool one_entry_tp_active_occur; 110 bool is_match_bssid; 111 /*[Client Number]*/ 112 u8 num_linked_client; 113 u8 num_linked_client_pre; 114 u8 num_active_client; 115 u8 num_active_client_pre; 116 /*[TP & Traffic]*/ 117 u8 traffic_load; 118 u8 traffic_load_pre; 119 u16 tx_rate; 120 u16 rx_rate_plurality; 121 u16 rx_rate_plurality_mu; 122 u32 tx_tp; /*@Mbps*/ 123 u32 rx_tp; /*@Mbps*/ 124 u32 total_tp; /*@Mbps*/ 125 u16 consecutive_idle_time; /*@unit: second*/ 126 }; 127 128 struct bb_ch_info { 129 u8 rssi_min; 130 u16 rssi_min_macid; 131 u8 pre_rssi_min; 132 u8 rssi_max; 133 u16 rssi_max_macid; 134 u8 rxsc_160; 135 u8 rxsc_80; 136 u8 rxsc_40; 137 u8 rxsc_20; 138 u8 rxsc_l; 139 u8 is_noisy; 140 u8 rf_central_ch_cfg; /*report in phy-sts*/ 141 }; 142 143 struct bb_cmn_backup_info { 144 u8 cur_tx_path; 145 u8 cur_rx_path; 146 s16 cur_tx_pwr; 147 u8 cur_pd_lower_bound; 148 u8 last_rssi; 149 struct rssi_physts last_rssi_rpt; 150 struct rxevm_physts last_rxevm_rpt; 151 }; 152 153 struct bb_gain_info { 154 s8 lna_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_LNA_NUM]; 155 s8 tia_gain[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][IC_TIA_NUM]; 156 s8 efuse_ofst[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][EFUSE_OFST_NUM]; 157 s8 rpl_ofst_20[BB_GAIN_BAND_NUM][HALBB_MAX_PATH]; 158 s8 rpl_ofst_40[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_40]; 159 s8 rpl_ofst_80[BB_GAIN_BAND_NUM][HALBB_MAX_PATH][BB_RXSC_NUM_80]; 160 }; 161 162 struct bb_efuse_info{ 163 bool normal_efuse_check; 164 bool hidden_efuse_check; 165 s8 gain_offset[HALBB_MAX_PATH][BB_EFUSE_BAND_NUM]; // S(8,0) 166 s8 gain_cs[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0) 167 s8 gain_cg[HALBB_MAX_PATH][BB_GAIN_BAND_NUM]; // S(8,0) 168 169 s8 lna_err_2g[HALBB_MAX_PATH][7]; // S(6,2) 170 s8 lna_err_5g[HALBB_MAX_PATH][7]; // S(6,2) 171 172 s8 frontend_loss[HALBB_MAX_PATH]; 173 s8 rpl_bias_comp[HALBB_MAX_PATH]; 174 s8 rssi_bias_comp[HALBB_MAX_PATH]; 175 176 s8 efuse_ofst; // 8852A:S(5,2) 8852B:S(8,4) 177 s8 efuse_ofst_tb; // 8852A:S(7,4) 8852B:S(8,4) 178 }; 179 180 struct bb_cmn_info { 181 u8 bb_dm_number; 182 #ifdef HALBB_PSD_SUPPORT 183 struct bb_psd_info bb_psd_i; 184 #endif 185 #ifdef HALBB_LA_MODE_SUPPORT 186 struct bb_la_mode_info bb_la_mode_i; 187 #endif 188 #ifdef HALBB_DYN_CSI_RSP_SUPPORT 189 struct bf_ch_raw_info bf_ch_raw_i; 190 #endif 191 struct bb_echo_cmd_info bb_echo_cmd_i; 192 struct bb_func_hooker_info bb_func_hooker_i; 193 }; 194 195 #ifdef HALBB_DIG_MCC_SUPPORT 196 #define PD_IDX_MIN 0 197 #define NUM_MAX_IGI_CNT 7 198 #define INVALID_INIT_VAL 0xff 199 200 /*For 2G/5G/6G*/ 201 enum mcc_band { 202 MCC_BAND_1 = 0, 203 MCC_BAND_2, 204 MCC_BAND_NUM 205 }; 206 207 struct halbb_mcc_dm { 208 bool mcc_pre_status_en; 209 u8 mcc_reg_id[NUM_MAX_IGI_CNT]; 210 u8 sta_cnt[MCC_BAND_NUM]; 211 u16 mcc_dm_reg[NUM_MAX_IGI_CNT]; 212 u16 mcc_dm_mask[NUM_MAX_IGI_CNT]; 213 u16 mcc_dm_val[NUM_MAX_IGI_CNT][MCC_BAND_NUM]; 214 /*mcc DIG*/ 215 u8 rssi_min[MCC_BAND_NUM]; 216 217 /* need to be config by driver*/ 218 bool mcc_status_en; 219 u8 softap_macid; 220 struct rtw_chan_def mcc_rf_ch[MCC_BAND_NUM]; 221 222 }; 223 /** 224 * @struct _mcc_h2c_ 225 * @brief _mcc_h2c_ 226 * 227 */ 228 struct mcc_h2c_reg_content { 229 // MCCDM 230 u8 addr_lsb; 231 u8 addr_msb; 232 u8 bmask_lsb; 233 u8 bmask_msb; 234 u8 val_lsb; 235 u8 val_msb; 236 }; 237 238 struct mcc_h2c { 239 // MCCDM 240 u8 reg_cnt; 241 u8 mcc_dm_en: 1; 242 u8 mcc_ch_idx: 1; 243 u8 mcc_set: 1; 244 u8 phy0_en: 1; 245 u8 phy1_en: 1; 246 u8 rsvd0: 3; 247 u8 ch_lsb; 248 u8 ch_msb; 249 struct mcc_h2c_reg_content mcc_reg_content[NUM_MAX_IGI_CNT]; 250 }; 251 #endif 252 253 struct bb_info { 254 struct rtw_phl_com_t *phl_com; 255 struct rtw_hal_com_t *hal_com; 256 struct rtw_phl_stainfo_t *phl_sta_info[PHL_MAX_STA_NUM]; 257 u8 phl2bb_macid_table[PHL_MAX_STA_NUM]; 258 bool sta_exist[PHL_MAX_STA_NUM]; 259 /*[DBCC]*/ 260 #ifdef HALBB_DBCC_SUPPORT 261 struct bb_info *bb_phy_hooker; 262 #endif 263 enum phl_phy_idx bb_phy_idx; 264 struct bb_cmn_info *bb_cmn_hooker; 265 /*[Common Info]*/ 266 struct bb_gain_info bb_gain_i; 267 struct bb_efuse_info bb_efuse_i; 268 enum bb_ic_t ic_type; 269 enum bb_cr_t cr_type; 270 u8 num_rf_path; 271 /*[System Info]*/ 272 enum bb_watchdog_mode_t bb_watchdog_mode; 273 bool bb_cmn_info_init_ready; 274 bool bb_dm_init_ready; 275 u32 bb_sys_up_time; 276 bool bb_watchdog_en; 277 u8 bb_watchdog_period; /*2s, 4s, 8s...,254s*/ 278 bool bb_ic_api_en; 279 u8 pre_dbg_priority; 280 char dbg_buf[HALBB_SNPRINT_SIZE]; 281 /*[DM Info]*/ 282 bool is_noisy; 283 bool adv_bb_dm_en; 284 u64 support_ability; /*HALBB function Supportability*/ 285 u64 manual_support_ability; 286 u64 pause_ability; /*HALBB function pause Supportability*/ 287 struct halbb_pause_lv pause_lv_table; 288 /*[FW Info]*/ 289 u8 fwofld_last_cmd; 290 u64 fw_dbg_component; 291 /*[Drv Dbg Info]*/ 292 u64 dbg_component; 293 u8 cmn_dbg_msg_period; 294 u8 cmn_dbg_msg_cnt; 295 bool is_disable_phy_api; 296 /*[Dummy]*/ 297 bool bool_dummy; 298 u8 u8_dummy; 299 u16 u16_dummy; 300 u32 u32_dummy; 301 /*[Link Info]*/ 302 enum rf_path tx_path; /*PMAC Tx Path*/ 303 enum rf_path rx_path; 304 305 /*@=== [HALBB Structure] ============================================*/ 306 #ifdef BB_8852A_CAV_SUPPORT 307 struct bb_8852a_info bb_8852a_i; 308 #endif 309 #ifdef BB_8852A_2_SUPPORT 310 struct bb_8852a_2_info bb_8852a_2_i; 311 struct bb_h2c_fw_cmw bb_fw_cmw_i; 312 #endif 313 #ifdef HALBB_RA_SUPPORT 314 struct bb_ra_info bb_ra_i[PHL_MAX_STA_NUM]; 315 #endif 316 #ifdef HALBB_ENV_MNTR_SUPPORT 317 struct bb_env_mntr_info bb_env_mntr_i; 318 #endif 319 #ifdef HALBB_EDCCA_SUPPORT 320 struct bb_edcca_info bb_edcca_i; 321 #endif 322 #ifdef HALBB_DFS_SUPPORT 323 struct bb_dfs_info bb_dfs_i; 324 #endif 325 #ifdef HALBB_STATISTICS_SUPPORT 326 struct bb_stat_info bb_stat_i; 327 #endif 328 #ifdef HALBB_DIG_SUPPORT 329 struct bb_dig_info bb_dig_i; 330 #endif 331 #ifdef HALBB_CFO_TRK_SUPPORT 332 struct bb_cfo_trk_info bb_cfo_trk_i; 333 #endif 334 #ifdef HALBB_UL_TB_CTRL_SUPPORT 335 struct bb_ul_tb_info bb_ul_tb_i; 336 #endif 337 #ifdef HALBB_PHYSTS_PARSING_SUPPORT 338 struct bb_physts_info bb_physts_i; 339 #endif 340 #ifdef HALBB_LA_MODE_SUPPORT 341 struct bb_la_mode_info bb_la_mode_i; 342 #endif 343 344 #ifdef HALBB_PWR_CTRL_SUPPORT 345 struct bb_pwr_ctrl_info bb_pwr_ctrl_i; 346 struct bb_dyncca_info bb_dyncca_i; 347 #endif 348 349 #ifdef HALBB_PMAC_TX_SUPPORT 350 struct bb_plcp_info bb_plcp_i; 351 #endif 352 struct bb_link_info bb_link_i; 353 struct bb_path_info bb_path_i; 354 struct bb_ch_info bb_ch_i; 355 struct bb_api_info bb_api_i; 356 struct bb_iot_info bb_iot_i; 357 struct bb_dbg_info bb_dbg_i; 358 struct bb_c2h_fw_tx_rpt bb_fwtx_c2h_i; 359 struct bb_h2c_fw_tx_setting bb_fwtx_h2c_i; 360 struct bb_h2c_fw_edcca bb_fw_edcca_i; 361 struct bb_h2c_he_sigb bb_h2c_he_sigb_i; 362 struct bb_fw_dbg_cmn_info bb_fwdbg_i; 363 struct bb_cmn_rpt_info bb_cmn_rpt_i; 364 struct bb_rpt_info bb_rpt_i; 365 struct rxevm_physts rxevm; 366 struct bb_cmn_backup_info bb_cmn_backup_i; 367 #ifdef HALBB_CH_INFO_SUPPORT 368 struct bb_ch_rpt_info bb_ch_rpt_i; 369 #endif 370 #ifdef HALBB_AUTO_DBG_SUPPORT 371 struct bb_auto_dbg_info bb_auto_dbg_i; 372 #endif 373 #ifdef HALBB_ANT_DIV_SUPPORT 374 struct bb_antdiv_info bb_ant_div_i; 375 #endif 376 #ifdef HALBB_DYN_L2H_SUPPORT 377 struct bb_dyn_l2h_info bb_dyn_l2h_i; 378 #endif 379 /*@=== [HALBB Timer] ================================================*/ 380 #ifdef HALBB_RUA_SUPPORT 381 /*struct rtw_rua_tbl rtw_rua_t;*/ 382 #endif 383 #ifdef HALBB_DIG_MCC_SUPPORT 384 struct halbb_mcc_dm mcc_dm; 385 #endif 386 }; 387 388 389 /*@--------------------------[Prptotype]-------------------------------------*/ 390 u8 halbb_get_rssi_min(struct bb_info *bb); 391 void halbb_cmn_info_self_reset(struct bb_info *bb); 392 void halbb_sta_info_dbg(struct bb_info *bb, char input[][16], u32 *_used, 393 char *output, u32 *_out_len); 394 void halbb_supportability_dbg(struct bb_info *bb, char input[][16], u32 *_used, 395 char *output, u32 *_out_len); 396 void halbb_pause_func_dbg(struct bb_info *bb, char input[][16], u32 *_used, 397 char *output, u32 *_out_len); 398 #endif 399