1 /****************************************************************************** 2 * 3 * Copyright(c) 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _HAL_GENERAL_DEF_H_ 16 #define _HAL_GENERAL_DEF_H_ 17 18 #define RTW_MAC_TBTT_AGG_DEF 1 19 20 enum rtw_chip_id { 21 CHIP_WIFI6_8852A, 22 CHIP_WIFI6_8834A, 23 CHIP_WIFI6_8852B, 24 CHIP_WIFI6_8852C, 25 CHIP_WIFI6_MAX 26 }; 27 28 enum rtw_efuse_info { 29 /* MAC Part */ 30 EFUSE_INFO_MAC_ADDR, 31 EFUSE_INFO_MAC_PID, 32 EFUSE_INFO_MAC_DID, 33 EFUSE_INFO_MAC_VID, 34 EFUSE_INFO_MAC_SVID, 35 EFUSE_INFO_MAC_SMID, 36 EFUSE_INFO_MAC_MAX, 37 /* BB Part */ 38 EFUSE_INFO_BB_ANTDIV, 39 EFUSE_INFO_BB_MAX, 40 /* RF Part */ 41 EFUSE_INFO_RF_PKG_TYPE, 42 EFUSE_INFO_RF_PA, 43 EFUSE_INFO_RF_VALID_PATH, 44 EFUSE_INFO_RF_RFE, 45 EFUSE_INFO_RF_TXPWR, 46 EFUSE_INFO_RF_BOARD_OPTION, 47 EFUSE_INFO_RF_CHAN_PLAN, 48 EFUSE_INFO_RF_CHAN_PLAN_FORCE_HW, 49 EFUSE_INFO_RF_COUNTRY, 50 EFUSE_INFO_RF_THERMAL, 51 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_1, 52 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_2, 53 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_3, 54 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_4, 55 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_5, 56 EFUSE_INFO_RF_2G_CCK_A_TSSI_DE_6, 57 EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_1, 58 EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_2, 59 EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_3, 60 EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_4, 61 EFUSE_INFO_RF_2G_BW40M_A_TSSI_DE_5, 62 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_1, 63 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_2, 64 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_3, 65 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_4, 66 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_5, 67 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_6, 68 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_7, 69 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_8, 70 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_9, 71 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_10, 72 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_11, 73 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_12, 74 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_13, 75 EFUSE_INFO_RF_5G_BW40M_A_TSSI_DE_14, 76 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_1, 77 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_2, 78 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_3, 79 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_4, 80 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_5, 81 EFUSE_INFO_RF_2G_CCK_B_TSSI_DE_6, 82 EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_1, 83 EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_2, 84 EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_3, 85 EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_4, 86 EFUSE_INFO_RF_2G_BW40M_B_TSSI_DE_5, 87 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_1, 88 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_2, 89 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_3, 90 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_4, 91 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_5, 92 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_6, 93 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_7, 94 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_8, 95 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_9, 96 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_10, 97 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_11, 98 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_12, 99 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_13, 100 EFUSE_INFO_RF_5G_BW40M_B_TSSI_DE_14, 101 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_1, 102 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_2, 103 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_3, 104 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_4, 105 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_5, 106 EFUSE_INFO_RF_2G_CCK_C_TSSI_DE_6, 107 EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_1, 108 EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_2, 109 EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_3, 110 EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_4, 111 EFUSE_INFO_RF_2G_BW40M_C_TSSI_DE_5, 112 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_1, 113 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_2, 114 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_3, 115 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_4, 116 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_5, 117 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_6, 118 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_7, 119 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_8, 120 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_9, 121 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_10, 122 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_11, 123 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_12, 124 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_13, 125 EFUSE_INFO_RF_5G_BW40M_C_TSSI_DE_14, 126 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_1, 127 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_2, 128 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_3, 129 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_4, 130 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_5, 131 EFUSE_INFO_RF_2G_CCK_D_TSSI_DE_6, 132 EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_1, 133 EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_2, 134 EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_3, 135 EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_4, 136 EFUSE_INFO_RF_2G_BW40M_D_TSSI_DE_5, 137 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_1, 138 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_2, 139 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_3, 140 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_4, 141 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_5, 142 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_6, 143 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_7, 144 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_8, 145 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_9, 146 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_10, 147 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_11, 148 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_12, 149 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_13, 150 EFUSE_INFO_RF_5G_BW40M_D_TSSI_DE_14, 151 EFUSE_INFO_RF_THERMAL_A, 152 EFUSE_INFO_RF_THERMAL_B, 153 EFUSE_INFO_RF_THERMAL_C, 154 EFUSE_INFO_RF_THERMAL_D, 155 EFUSE_INFO_RF_XTAL, 156 /*RX Gain K*/ 157 EFUSE_INFO_RF_RX_GAIN_K_A_2G_CCK, 158 EFUSE_INFO_RF_RX_GAIN_K_A_2G_OFMD, 159 EFUSE_INFO_RF_RX_GAIN_K_A_5GL, 160 EFUSE_INFO_RF_RX_GAIN_K_A_5GM, 161 EFUSE_INFO_RF_RX_GAIN_K_A_5GH, 162 EFUSE_INFO_RF_MAX, 163 /* BTCOEX Part */ 164 EFUSE_INFO_BTCOEX_COEX, 165 EFUSE_INFO_BTCOEX_ANT_NUM, 166 EFUSE_INFO_BTCOEX_ANT_PATH, 167 EFUSE_INFO_BTCOEX_MAX, 168 }; 169 170 enum rtw_cv { 171 CAV, 172 CBV, 173 CCV, 174 CDV, 175 CEV, 176 CFV, 177 CGV, 178 CTV, 179 CMAXV, 180 }; 181 182 enum rtw_fv { 183 FTV, 184 FUV, 185 FSV, 186 }; 187 188 enum rtw_dv_sel { 189 DAV, 190 DDV, 191 }; 192 193 enum hal_pwr_by_rate_setting { 194 PW_BY_RATE_ON = 0, 195 PW_BY_RATE_ALL_SAME = 1 196 }; 197 198 enum hal_pwr_limit_type { 199 PWLMT_BY_EFUSE = 0, 200 PWLMT_DISABLE = 1, 201 PWBYRATE_AND_PWLMT = 2 202 }; 203 204 enum rtw_mac_gfunc { 205 RTW_MAC_GPIO_WL_PD, 206 RTW_MAC_GPIO_BT_PD, 207 RTW_MAC_GPIO_WL_EXTWOL, 208 RTW_MAC_GPIO_BT_GPIO, 209 RTW_MAC_GPIO_WL_SDIO_INT, 210 RTW_MAC_GPIO_BT_SDIO_INT, 211 RTW_MAC_GPIO_WL_FLASH, 212 RTW_MAC_GPIO_BT_FLASH, 213 RTW_MAC_GPIO_SIC, 214 RTW_MAC_GPIO_LTE_UART, 215 RTW_MAC_GPIO_LTE_3W, 216 RTW_MAC_GPIO_WL_PTA, 217 RTW_MAC_GPIO_BT_PTA, 218 RTW_MAC_GPIO_MAILBOX, 219 RTW_MAC_GPIO_WL_LED, 220 RTW_MAC_GPIO_OSC, 221 RTW_MAC_GPIO_XTAL_CLK, 222 RTW_MAC_GPIO_EXT_XTAL_CLK, 223 RTW_MAC_GPIO_DBG_GNT, 224 RTW_MAC_GPIO_WL_RFE_CTRL, 225 RTW_MAC_GPIO_BT_UART_RQB, 226 RTW_MAC_GPIO_BT_WAKE_HOST, 227 RTW_MAC_GPIO_HOST_WAKE_BT, 228 RTW_MAC_GPIO_DBG, 229 RTW_MAC_GPIO_WL_UART_TX, 230 RTW_MAC_GPIO_WL_UART_RX, 231 RTW_MAC_GPIO_WL_JTAG, 232 RTW_MAC_GPIO_SW_IO, 233 234 /* keep last */ 235 RTW_MAC_GPIO_LAST, 236 RTW_MAC_GPIO_MAX = RTW_MAC_GPIO_LAST, 237 RTW_MAC_GPIO_INVALID = RTW_MAC_GPIO_LAST, 238 RTW_MAC_GPIO_DFLT = RTW_MAC_GPIO_LAST, 239 }; 240 241 242 #ifdef CONFIG_FW_IO_OFLD_SUPPORT 243 enum rtw_mac_src_cmd_ofld { 244 RTW_MAC_BB_CMD_OFLD = 0, 245 RTW_MAC_RF_CMD_OFLD, 246 RTW_MAC_MAC_CMD_OFLD, 247 RTW_MAC_OTHER_CMD_OFLD 248 }; 249 enum rtw_mac_cmd_type_ofld { 250 RTW_MAC_WRITE_OFLD = 0, 251 RTW_MAC_COMPARE_OFLD, 252 RTW_MAC_DELAY_OFLD 253 }; 254 enum rtw_mac_rf_path { 255 RTW_MAC_RF_PATH_A = 0, //Radio Path A 256 RTW_MAC_RF_PATH_B, //Radio Path B 257 RTW_MAC_RF_PATH_C, //Radio Path C 258 RTW_MAC_RF_PATH_D, //Radio Path D 259 }; 260 struct rtw_mac_cmd { 261 enum rtw_mac_src_cmd_ofld src; 262 enum rtw_mac_cmd_type_ofld type; 263 u8 lc; 264 enum rtw_mac_rf_path rf_path; 265 u16 offset; 266 u16 id; 267 u32 value; 268 u32 mask; 269 }; 270 enum rtw_fw_ofld_cap { 271 FW_CAP_IO_OFLD = BIT(0), 272 }; 273 #endif 274 275 enum wl_func { 276 EFUSE_WL_FUNC_NONE = 0, 277 EFUSE_WL_FUNC_DRAGON = 0xe, 278 EFUSE_WL_FUNC_GENERAL = 0xf 279 }; 280 281 enum hw_stype{ 282 EFUSE_HW_STYPE_NONE = 0x0, 283 EFUSE_HW_STYPE_GENERAL = 0xf 284 }; 285 286 struct rtw_hal_mac_ax_cctl_info { 287 /* dword 0 */ 288 u32 datarate:9; 289 u32 force_txop:1; 290 u32 data_bw:2; 291 u32 data_gi_ltf:3; 292 u32 darf_tc_index:1; 293 u32 arfr_ctrl:4; 294 u32 acq_rpt_en:1; 295 u32 mgq_rpt_en:1; 296 u32 ulq_rpt_en:1; 297 u32 twtq_rpt_en:1; 298 u32 rsvd0:1; 299 u32 disrtsfb:1; 300 u32 disdatafb:1; 301 u32 tryrate:1; 302 u32 ampdu_density:4; 303 /* dword 1 */ 304 u32 data_rty_lowest_rate:9; 305 u32 ampdu_time_sel:1; 306 u32 ampdu_len_sel:1; 307 u32 rts_txcnt_lmt_sel:1; 308 u32 rts_txcnt_lmt:4; 309 u32 rtsrate:9; 310 u32 rsvd1:2; 311 u32 vcs_stbc:1; 312 u32 rts_rty_lowest_rate:4; 313 /* dword 2 */ 314 u32 data_tx_cnt_lmt:6; 315 u32 data_txcnt_lmt_sel:1; 316 u32 max_agg_num_sel:1; 317 u32 rts_en:1; 318 u32 cts2self_en:1; 319 u32 cca_rts:2; 320 u32 hw_rts_en:1; 321 u32 rts_drop_data_mode:2; 322 u32 rsvd2:1; 323 u32 ampdu_max_len:11; 324 u32 ul_mu_dis:1; 325 u32 ampdu_max_time:4; 326 /* dword 3 */ 327 u32 max_agg_num:8; 328 u32 ba_bmap:2; 329 u32 rsvd3:6; 330 u32 vo_lftime_sel:3; 331 u32 vi_lftime_sel:3; 332 u32 be_lftime_sel:3; 333 u32 bk_lftime_sel:3; 334 u32 sectype:4; 335 /* dword 4 */ 336 u32 multi_port_id:3; 337 u32 bmc:1; 338 u32 mbssid:4; 339 u32 navusehdr:1; 340 u32 txpwr_mode:3; 341 u32 data_dcm:1; 342 u32 data_er:1; 343 u32 data_ldpc:1; 344 u32 data_stbc:1; 345 u32 a_ctrl_bqr:1; 346 u32 a_ctrl_uph:1; 347 u32 a_ctrl_bsr:1; 348 u32 a_ctrl_cas:1; 349 u32 data_bw_er:1; 350 u32 lsig_txop_en:1; 351 u32 rsvd4:5; 352 u32 ctrl_cnt_vld:1; 353 u32 ctrl_cnt:4; 354 /* dword 5 */ 355 u32 resp_ref_rate:9; 356 u32 rsvd5:3; 357 u32 all_ack_support:1; 358 u32 bsr_queue_size_format:1; 359 u32 rsvd6:1; 360 u32 rsvd7:1; 361 u32 ntx_path_en:4; 362 u32 path_map_a:2; 363 u32 path_map_b:2; 364 u32 path_map_c:2; 365 u32 path_map_d:2; 366 u32 antsel_a:1; 367 u32 antsel_b:1; 368 u32 antsel_c:1; 369 u32 antsel_d:1; 370 /* dword 6 */ 371 u32 addr_cam_index:8; 372 u32 paid:9; 373 u32 uldl:1; 374 u32 doppler_ctrl:2; 375 u32 nominal_pkt_padding:2; 376 u32 nominal_pkt_padding40:2; 377 u32 txpwr_tolerence:4; 378 u32 rsvd9:2; 379 u32 nominal_pkt_padding80:2; 380 /* dword 7 */ 381 u32 nc:3; 382 u32 nr:3; 383 u32 ng:2; 384 u32 cb:2; 385 u32 cs:2; 386 u32 csi_txbf_en:1; 387 u32 csi_stbc_en:1; 388 u32 csi_ldpc_en:1; 389 u32 csi_para_en:1; 390 u32 csi_fix_rate:9; 391 u32 csi_gi_ltf:3; 392 u32 nominal_pkt_padding160:2; 393 u32 csi_bw:2; 394 }; 395 396 #endif /* _HAL_GENERAL_DEF_H_*/ 397 398