xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/include/rtw_ht.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2019 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _RTW_HT_H_
16*4882a593Smuzhiyun #define _RTW_HT_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #define HT_CAP_IE_LEN 26
19*4882a593Smuzhiyun #define HT_OP_IE_LEN 22
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun struct ht_priv {
22*4882a593Smuzhiyun 	u8	ht_option;
23*4882a593Smuzhiyun 	u8	ampdu_enable;/* for enable Tx A-MPDU */
24*4882a593Smuzhiyun 	u8	tx_amsdu_enable;/* for enable Tx A-MSDU */
25*4882a593Smuzhiyun 	u8	bss_coexist;/* for 20/40 Bss coexist */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun 	/* u8	baddbareq_issued[16]; */
28*4882a593Smuzhiyun 	u32	tx_amsdu_maxlen; /* 1: 8k, 0:4k ; default:8k, for tx */
29*4882a593Smuzhiyun 	u32	rx_ampdu_maxlen; /* for rx reordering ctrl win_sz, updated when join_callback. */
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 	u8	rx_ampdu_min_spacing;
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun 	u8	ch_offset;/* PRIME_CHNL_OFFSET */
34*4882a593Smuzhiyun 	u8	sgi_20m;
35*4882a593Smuzhiyun 	u8	sgi_40m;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* for processing Tx A-MPDU */
38*4882a593Smuzhiyun 	u8	agg_enable_bitmap;
39*4882a593Smuzhiyun 	/* u8	ADDBA_retry_count; */
40*4882a593Smuzhiyun 	u8	candidate_tid_bitmap;
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	u8	ldpc_cap;
43*4882a593Smuzhiyun 	u8	stbc_cap;
44*4882a593Smuzhiyun 	u8	beamform_cap;
45*4882a593Smuzhiyun 	u8	smps_cap; /*spatial multiplexing power save mode. 0:static SMPS, 1:dynamic SMPS, 3:SMPS disabled, 2:reserved*/
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	u8 op_present:1; /* ht_op is present */
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun 	struct rtw_ieee80211_ht_cap ht_cap;
50*4882a593Smuzhiyun 	u8 ht_op[HT_OP_IE_LEN];
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun #ifdef ROKU_PRIVATE
55*4882a593Smuzhiyun struct ht_priv_infra_ap {
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun 	/*Infra mode, only store AP's info , not intersection of STA and AP*/
58*4882a593Smuzhiyun 	u8	channel_width_infra_ap;
59*4882a593Smuzhiyun 	u8	sgi_20m_infra_ap;
60*4882a593Smuzhiyun 	u8	sgi_40m_infra_ap;
61*4882a593Smuzhiyun 	u8	ldpc_cap_infra_ap;
62*4882a593Smuzhiyun 	u8	stbc_cap_infra_ap;
63*4882a593Smuzhiyun 	u8	MCS_set_infra_ap[16];
64*4882a593Smuzhiyun 	u8	Rx_ss_infra_ap;
65*4882a593Smuzhiyun 	u16	rx_highest_data_rate_infra_ap;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun #endif /* ROKU_PRIVATE */
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun typedef enum AGGRE_SIZE {
70*4882a593Smuzhiyun 	HT_AGG_SIZE_8K = 0,
71*4882a593Smuzhiyun 	HT_AGG_SIZE_16K = 1,
72*4882a593Smuzhiyun 	HT_AGG_SIZE_32K = 2,
73*4882a593Smuzhiyun 	HT_AGG_SIZE_64K = 3,
74*4882a593Smuzhiyun 	VHT_AGG_SIZE_128K = 4,
75*4882a593Smuzhiyun 	VHT_AGG_SIZE_256K = 5,
76*4882a593Smuzhiyun 	VHT_AGG_SIZE_512K = 6,
77*4882a593Smuzhiyun 	VHT_AGG_SIZE_1024K = 7,
78*4882a593Smuzhiyun } AGGRE_SIZE_E, *PAGGRE_SIZE_E;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun #define	LDPC_HT_ENABLE_RX			BIT0
81*4882a593Smuzhiyun #define	LDPC_HT_ENABLE_TX			BIT1
82*4882a593Smuzhiyun #define	LDPC_HT_TEST_TX_ENABLE		BIT2
83*4882a593Smuzhiyun #define	LDPC_HT_CAP_TX				BIT3
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun #define	STBC_HT_ENABLE_RX			BIT0
86*4882a593Smuzhiyun #define	STBC_HT_ENABLE_TX			BIT1
87*4882a593Smuzhiyun #define	STBC_HT_TEST_TX_ENABLE		BIT2
88*4882a593Smuzhiyun #define	STBC_HT_CAP_TX				BIT3
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun /* ------------------------------------------------------------
91*4882a593Smuzhiyun  * The HT Control field
92*4882a593Smuzhiyun  * ------------------------------------------------------------ */
93*4882a593Smuzhiyun #define SET_HT_CTRL_CSI_STEERING(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+2, 6, 2, _val)
94*4882a593Smuzhiyun #define SET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart))+3, 0, 1, _val)
95*4882a593Smuzhiyun #define GET_HT_CTRL_NDP_ANNOUNCEMENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+3, 0, 1)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* 20/40 BSS Coexist */
98*4882a593Smuzhiyun #define SET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
99*4882a593Smuzhiyun #define GET_EXT_CAPABILITY_ELE_BSS_COEXIST(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* HT Capabilities Info field */
102*4882a593Smuzhiyun #define HT_CAP_ELE_CAP_INFO(_pEleStart)					((u8 *)(_pEleStart))
103*4882a593Smuzhiyun #define GET_HT_CAP_ELE_LDPC_CAP(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 1)
104*4882a593Smuzhiyun #define GET_HT_CAP_ELE_CHL_WIDTH(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 1, 1)
105*4882a593Smuzhiyun #define GET_HT_CAP_ELE_SM_PS(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 2, 2)
106*4882a593Smuzhiyun #define GET_HT_CAP_ELE_GREENFIELD(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 4, 1)
107*4882a593Smuzhiyun #define GET_HT_CAP_ELE_SHORT_GI20M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 5, 1)
108*4882a593Smuzhiyun #define GET_HT_CAP_ELE_SHORT_GI40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 6, 1)
109*4882a593Smuzhiyun #define GET_HT_CAP_ELE_TX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 7, 1)
110*4882a593Smuzhiyun #define GET_HT_CAP_ELE_RX_STBC(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 0, 2)
111*4882a593Smuzhiyun #define GET_HT_CAP_ELE_DELAYED_BA(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 2, 1)
112*4882a593Smuzhiyun #define GET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 3, 1)
113*4882a593Smuzhiyun #define GET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 4, 1)
114*4882a593Smuzhiyun #define GET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 6, 1)
115*4882a593Smuzhiyun #define GET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+1, 7, 1)
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun #define SET_HT_CAP_ELE_LDPC_CAP(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 1, _val)
118*4882a593Smuzhiyun #define SET_HT_CAP_ELE_CHL_WIDTH(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 1, 1, _val)
119*4882a593Smuzhiyun #define SET_HT_CAP_ELE_SM_PS(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 2, 2, _val)
120*4882a593Smuzhiyun #define SET_HT_CAP_ELE_GREENFIELD(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 4, 1, _val)
121*4882a593Smuzhiyun #define SET_HT_CAP_ELE_SHORT_GI20M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 5, 1, _val)
122*4882a593Smuzhiyun #define SET_HT_CAP_ELE_SHORT_GI40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 6, 1, _val)
123*4882a593Smuzhiyun #define SET_HT_CAP_ELE_TX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 7, 1, _val)
124*4882a593Smuzhiyun #define SET_HT_CAP_ELE_RX_STBC(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
125*4882a593Smuzhiyun #define SET_HT_CAP_ELE_DELAYED_BA(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
126*4882a593Smuzhiyun #define SET_HT_CAP_ELE_MAX_AMSDU_LENGTH(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
127*4882a593Smuzhiyun #define SET_HT_CAP_ELE_DSSS_CCK_40M(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 4, 1, _val)
128*4882a593Smuzhiyun #define SET_HT_CAP_ELE_FORTY_INTOLERANT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 6, 1, _val)
129*4882a593Smuzhiyun #define SET_HT_CAP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 7, 1, _val)
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* A-MPDU Parameters field */
132*4882a593Smuzhiyun #define HT_CAP_ELE_AMPDU_PARA(_pEleStart)				(((u8 *)(_pEleStart))+2)
133*4882a593Smuzhiyun #define GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart)	LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 0, 2)
134*4882a593Smuzhiyun #define GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+2, 2, 3)
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun #define HT_AMPDU_PARA_FMT "%02x " \
137*4882a593Smuzhiyun 	"MAX AMPDU len:%u bytes, MIN MPDU Start Spacing:%u"
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #define HT_AMPDU_PARA_ARG(x) \
140*4882a593Smuzhiyun 	*((u8 *)(x)) \
141*4882a593Smuzhiyun 	, (1 << (13+GET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(((u8 *)x)-2)))-1 \
142*4882a593Smuzhiyun 	, GET_HT_CAP_ELE_MIN_MPDU_S_SPACE(((u8 *)x)-2)
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun #define SET_HT_CAP_ELE_MAX_AMPDU_LEN_EXP(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
145*4882a593Smuzhiyun #define SET_HT_CAP_ELE_MIN_MPDU_S_SPACE(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 3, _val)
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun /* Supported MCS Set field */
148*4882a593Smuzhiyun #define HT_CAP_ELE_SUP_MCS_SET(_pEleStart)				(((u8 *)(_pEleStart))+3)
149*4882a593Smuzhiyun #define HT_CAP_ELE_RX_MCS_MAP(_pEleStart)				HT_CAP_ELE_SUP_MCS_SET(_pEleStart)
150*4882a593Smuzhiyun #define GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(_pEleStart)	LE_BITS_TO_2BYTE(((u8 *)(_pEleStart))+13, 0, 10)
151*4882a593Smuzhiyun #define GET_HT_CAP_ELE_TX_MCS_DEF(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 0, 1)
152*4882a593Smuzhiyun #define GET_HT_CAP_ELE_TRX_MCS_NEQ(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 1, 1)
153*4882a593Smuzhiyun #define GET_HT_CAP_ELE_TX_MAX_SS(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 2, 2)
154*4882a593Smuzhiyun #define GET_HT_CAP_ELE_TX_UEQM(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart))+15, 4, 1)
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun #define HT_RX_MCS_BMP_FMT "%02x %02x %02x %02x %02x%02x%02x%02x%02x%02x"
157*4882a593Smuzhiyun #define HT_RX_MCS_BMP_ARG(x) ((u8 *)(x))[0], ((u8 *)(x))[1], ((u8 *)(x))[2], ((u8 *)(x))[3], ((u8 *)(x))[4], ((u8 *)(x))[5], \
158*4882a593Smuzhiyun 	((u8 *)(x))[6], ((u8 *)(x))[7], ((u8 *)(x))[8], ((u8 *)(x))[9]
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun #define HT_SUP_MCS_SET_FMT HT_RX_MCS_BMP_FMT \
161*4882a593Smuzhiyun 	/* "\n%02x%02x%02x%02x%02x%02x" */\
162*4882a593Smuzhiyun 	" %uMbps %s%s%s"
163*4882a593Smuzhiyun #define HT_SUP_MCS_SET_ARG(x) HT_RX_MCS_BMP_ARG(x) \
164*4882a593Smuzhiyun 	/*,((u8 *)(x))[10], ((u8 *)(x))[11], ((u8 *)(x))[12], ((u8 *)(x))[13], ((u8 *)(x))[14], ((u8 *)(x))[15] */\
165*4882a593Smuzhiyun 	, GET_HT_CAP_ELE_RX_HIGHEST_DATA_RATE(((u8 *)x)-3) \
166*4882a593Smuzhiyun 	, GET_HT_CAP_ELE_TX_MCS_DEF(((u8 *)x)-3) ? "TX_MCS_DEF " : "" \
167*4882a593Smuzhiyun 	, GET_HT_CAP_ELE_TRX_MCS_NEQ(((u8 *)x)-3) ? "TRX_MCS_NEQ " : "" \
168*4882a593Smuzhiyun 	, GET_HT_CAP_ELE_TX_UEQM(((u8 *)x)-3) ? "TX_UEQM " : ""
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* TXBF Capabilities */
171*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_RECEIVE_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 3, 1, ((u8)_val))
172*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_TRANSMIT_NDP_CAP(_pEleStart, _val)				SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 4, 1, ((u8)_val))
173*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 10, 1, ((u8)_val))
174*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 15, 2, ((u8)_val))
175*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 23, 2, ((u8)_val))
176*4882a593Smuzhiyun #define SET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart, _val)	SET_BITS_TO_LE_4BYTE(((u8 *)(_pEleStart))+21, 27, 2, ((u8)_val))
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #define GET_HT_CAP_TXBF_EXPLICIT_COMP_STEERING_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 10, 1)
180*4882a593Smuzhiyun #define GET_HT_CAP_TXBF_EXPLICIT_COMP_FEEDBACK_CAP(_pEleStart)			LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 15, 2)
181*4882a593Smuzhiyun #define GET_HT_CAP_TXBF_COMP_STEERING_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 23, 2)
182*4882a593Smuzhiyun #define GET_HT_CAP_TXBF_CHNL_ESTIMATION_NUM_ANTENNAS(_pEleStart)		LE_BITS_TO_4BYTE(((u8 *)(_pEleStart))+21, 27, 2)
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /* HT Operation element */
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #define GET_HT_OP_ELE_PRI_CHL(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)), 0, 8)
187*4882a593Smuzhiyun #define SET_HT_OP_ELE_PRI_CHL(_pEleStart, _val)				SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)), 0, 8, _val)
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* HT Operation Info field */
190*4882a593Smuzhiyun #define HT_OP_ELE_OP_INFO(_pEleStart)						(((u8 *)(_pEleStart)) + 1)
191*4882a593Smuzhiyun #define GET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2)
192*4882a593Smuzhiyun #define GET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1)
193*4882a593Smuzhiyun #define GET_HT_OP_ELE_RIFS_MODE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1)
194*4882a593Smuzhiyun #define GET_HT_OP_ELE_HT_PROTECT(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2)
195*4882a593Smuzhiyun #define GET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1)
196*4882a593Smuzhiyun #define GET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart)		LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1)
197*4882a593Smuzhiyun #define GET_HT_OP_ELE_DUAL_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1)
198*4882a593Smuzhiyun #define GET_HT_OP_ELE_DUAL_CTS(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1)
199*4882a593Smuzhiyun #define GET_HT_OP_ELE_STBC_BEACON(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1)
200*4882a593Smuzhiyun #define GET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart)			LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1)
201*4882a593Smuzhiyun #define GET_HT_OP_ELE_PCO_ACTIVE(_pEleStart)				LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1)
202*4882a593Smuzhiyun #define GET_HT_OP_ELE_PCO_PHASE(_pEleStart)					LE_BITS_TO_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1)
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #define SET_HT_OP_ELE_2ND_CHL_OFFSET(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 0, 2, _val)
205*4882a593Smuzhiyun #define SET_HT_OP_ELE_STA_CHL_WIDTH(_pEleStart, _val)		SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 2, 1, _val)
206*4882a593Smuzhiyun #define SET_HT_OP_ELE_RIFS_MODE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 1, 3, 1, _val)
207*4882a593Smuzhiyun #define SET_HT_OP_ELE_HT_PROTECT(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 0, 2, _val)
208*4882a593Smuzhiyun #define SET_HT_OP_ELE_NON_GREEN_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 2, 1, _val)
209*4882a593Smuzhiyun #define SET_HT_OP_ELE_OBSS_NON_HT_PRESENT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 2, 4, 1, _val)
210*4882a593Smuzhiyun #define SET_HT_OP_ELE_DUAL_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 6, 1, _val)
211*4882a593Smuzhiyun #define SET_HT_OP_ELE_DUAL_CTS(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 4, 7, 1, _val)
212*4882a593Smuzhiyun #define SET_HT_OP_ELE_STBC_BEACON(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 0, 1, _val)
213*4882a593Smuzhiyun #define SET_HT_OP_ELE_LSIG_TXOP_PROTECT(_pEleStart, _val)	SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 1, 1, _val)
214*4882a593Smuzhiyun #define SET_HT_OP_ELE_PCO_ACTIVE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 2, 1, _val)
215*4882a593Smuzhiyun #define SET_HT_OP_ELE_PCO_PHASE(_pEleStart, _val)			SET_BITS_TO_LE_1BYTE(((u8 *)(_pEleStart)) + 5, 3, 1, _val)
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun #endif /* _RTL871X_HT_H_ */
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