1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __GSPI_OPS_H__ 16*4882a593Smuzhiyun #define __GSPI_OPS_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* follwing defination is based on 19*4882a593Smuzhiyun * GSPI spec of RTL8723, we temp 20*4882a593Smuzhiyun * suppose that it will be the same 21*4882a593Smuzhiyun * for diff chips of GSPI, if not 22*4882a593Smuzhiyun * we should move it to HAL folder */ 23*4882a593Smuzhiyun #define SPI_LOCAL_DOMAIN 0x0 24*4882a593Smuzhiyun #define WLAN_IOREG_DOMAIN 0x8 25*4882a593Smuzhiyun #define FW_FIFO_DOMAIN 0x4 26*4882a593Smuzhiyun #define TX_HIQ_DOMAIN 0xc 27*4882a593Smuzhiyun #define TX_MIQ_DOMAIN 0xd 28*4882a593Smuzhiyun #define TX_LOQ_DOMAIN 0xe 29*4882a593Smuzhiyun #define RX_RXFIFO_DOMAIN 0x1f 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* IO Bus domain address mapping */ 32*4882a593Smuzhiyun #define DEFUALT_OFFSET 0x0 33*4882a593Smuzhiyun #define SPI_LOCAL_OFFSET 0x10250000 34*4882a593Smuzhiyun #define WLAN_IOREG_OFFSET 0x10260000 35*4882a593Smuzhiyun #define FW_FIFO_OFFSET 0x10270000 36*4882a593Smuzhiyun #define TX_HIQ_OFFSET 0x10310000 37*4882a593Smuzhiyun #define TX_MIQ_OFFSET 0x1032000 38*4882a593Smuzhiyun #define TX_LOQ_OFFSET 0x10330000 39*4882a593Smuzhiyun #define RX_RXOFF_OFFSET 0x10340000 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* SPI Local registers */ 42*4882a593Smuzhiyun #define SPI_REG_TX_CTRL 0x0000 /* SPI Tx Control */ 43*4882a593Smuzhiyun #define SPI_REG_STATUS_RECOVERY 0x0004 44*4882a593Smuzhiyun #define SPI_REG_INT_TIMEOUT 0x0006 45*4882a593Smuzhiyun #define SPI_REG_HIMR 0x0014 /* SPI Host Interrupt Mask */ 46*4882a593Smuzhiyun #define SPI_REG_HISR 0x0018 /* SPI Host Interrupt Service Routine */ 47*4882a593Smuzhiyun #define SPI_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ 48*4882a593Smuzhiyun #define SPI_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ 49*4882a593Smuzhiyun #define SPI_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ 50*4882a593Smuzhiyun #define SPI_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ 51*4882a593Smuzhiyun #define SPI_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ 52*4882a593Smuzhiyun #define SPI_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ 53*4882a593Smuzhiyun #define SPI_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ 54*4882a593Smuzhiyun #define SPI_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ 55*4882a593Smuzhiyun #define SPI_REG_HSUS_CTRL 0x0086 /* SPI HCI Suspend Control */ 56*4882a593Smuzhiyun #define SPI_REG_HIMR_ON 0x0090 /* SPI Host Extension Interrupt Mask Always */ 57*4882a593Smuzhiyun #define SPI_REG_HISR_ON 0x0091 /* SPI Host Extension Interrupt Status Always */ 58*4882a593Smuzhiyun #define SPI_REG_CFG 0x00F0 /* SPI Configuration Register */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define SPI_TX_CTRL (SPI_REG_TX_CTRL | SPI_LOCAL_OFFSET) 61*4882a593Smuzhiyun #define SPI_STATUS_RECOVERY (SPI_REG_STATUS_RECOVERY | SPI_LOCAL_OFFSET) 62*4882a593Smuzhiyun #define SPI_INT_TIMEOUT (SPI_REG_INT_TIMEOUT | SPI_LOCAL_OFFSET) 63*4882a593Smuzhiyun #define SPI_HIMR (SPI_REG_HIMR | SPI_LOCAL_OFFSET) 64*4882a593Smuzhiyun #define SPI_HISR (SPI_REG_HISR | SPI_LOCAL_OFFSET) 65*4882a593Smuzhiyun #define SPI_RX0_REQ_LEN_1_BYTE (SPI_REG_RX0_REQ_LEN | SPI_LOCAL_OFFSET) 66*4882a593Smuzhiyun #define SPI_FREE_TXPG (SPI_REG_FREE_TXPG | SPI_LOCAL_OFFSET) 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define SPI_HIMR_DISABLED 0 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* SPI HIMR MASK diff with SDIO */ 71*4882a593Smuzhiyun #define SPI_HISR_RX_REQUEST BIT(0) 72*4882a593Smuzhiyun #define SPI_HISR_AVAL BIT(1) 73*4882a593Smuzhiyun #define SPI_HISR_TXERR BIT(2) 74*4882a593Smuzhiyun #define SPI_HISR_RXERR BIT(3) 75*4882a593Smuzhiyun #define SPI_HISR_TXFOVW BIT(4) 76*4882a593Smuzhiyun #define SPI_HISR_RXFOVW BIT(5) 77*4882a593Smuzhiyun #define SPI_HISR_TXBCNOK BIT(6) 78*4882a593Smuzhiyun #define SPI_HISR_TXBCNERR BIT(7) 79*4882a593Smuzhiyun #define SPI_HISR_BCNERLY_INT BIT(16) 80*4882a593Smuzhiyun #define SPI_HISR_ATIMEND BIT(17) 81*4882a593Smuzhiyun #define SPI_HISR_ATIMEND_E BIT(18) 82*4882a593Smuzhiyun #define SPI_HISR_CTWEND BIT(19) 83*4882a593Smuzhiyun #define SPI_HISR_C2HCMD BIT(20) 84*4882a593Smuzhiyun #define SPI_HISR_CPWM1 BIT(21) 85*4882a593Smuzhiyun #define SPI_HISR_CPWM2 BIT(22) 86*4882a593Smuzhiyun #define SPI_HISR_HSISR_IND BIT(23) 87*4882a593Smuzhiyun #define SPI_HISR_GTINT3_IND BIT(24) 88*4882a593Smuzhiyun #define SPI_HISR_GTINT4_IND BIT(25) 89*4882a593Smuzhiyun #define SPI_HISR_PSTIMEOUT BIT(26) 90*4882a593Smuzhiyun #define SPI_HISR_OCPINT BIT(27) 91*4882a593Smuzhiyun #define SPI_HISR_TSF_BIT32_TOGGLE BIT(29) 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun #define MASK_SPI_HISR_CLEAR (SPI_HISR_TXERR |\ 94*4882a593Smuzhiyun SPI_HISR_RXERR |\ 95*4882a593Smuzhiyun SPI_HISR_TXFOVW |\ 96*4882a593Smuzhiyun SPI_HISR_RXFOVW |\ 97*4882a593Smuzhiyun SPI_HISR_TXBCNOK |\ 98*4882a593Smuzhiyun SPI_HISR_TXBCNERR |\ 99*4882a593Smuzhiyun SPI_HISR_C2HCMD |\ 100*4882a593Smuzhiyun SPI_HISR_CPWM1 |\ 101*4882a593Smuzhiyun SPI_HISR_CPWM2 |\ 102*4882a593Smuzhiyun SPI_HISR_HSISR_IND |\ 103*4882a593Smuzhiyun SPI_HISR_GTINT3_IND |\ 104*4882a593Smuzhiyun SPI_HISR_GTINT4_IND |\ 105*4882a593Smuzhiyun SPI_HISR_PSTIMEOUT |\ 106*4882a593Smuzhiyun SPI_HISR_OCPINT) 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define REG_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 8, x)/* (x<<(unsigned int)24) */ 109*4882a593Smuzhiyun #define REG_ADDR_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x)/* (x<<(unsigned int)16) */ 110*4882a593Smuzhiyun #define REG_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */ 111*4882a593Smuzhiyun #define REG_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */ 112*4882a593Smuzhiyun #define REG_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */ 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun #define FIFO_LEN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 0, 16, x)/* (x<<(unsigned int)24) 115*4882a593Smuzhiyun * #define FIFO_ADDR_FORMAT(pcmd,x) SET_BITS_TO_LE_4BYTE(pcmd, 8, 16, x) */ /* (x<<(unsigned int)16) */ 116*4882a593Smuzhiyun #define FIFO_DOMAIN_ID_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 24, 5, x)/* (x<<(unsigned int)0) */ 117*4882a593Smuzhiyun #define FIFO_FUN_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 29, 2, x)/* (x<<(unsigned int)5) */ 118*4882a593Smuzhiyun #define FIFO_RW_FORMAT(pcmd, x) SET_BITS_TO_LE_4BYTE(pcmd, 31, 1, x)/* (x<<(unsigned int)7) */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* get status dword0 */ 122*4882a593Smuzhiyun #define GET_STATUS_PUB_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 24, 8) 123*4882a593Smuzhiyun #define GET_STATUS_HI_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 18, 6) 124*4882a593Smuzhiyun #define GET_STATUS_MID_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 12, 6) 125*4882a593Smuzhiyun #define GET_STATUS_LOW_PAGE_NUM(status) LE_BITS_TO_4BYTE(status, 6, 6) 126*4882a593Smuzhiyun #define GET_STATUS_HISR_HI6BIT(status) LE_BITS_TO_4BYTE(status, 0, 6) 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* get status dword1 */ 129*4882a593Smuzhiyun #define GET_STATUS_HISR_MID8BIT(status) LE_BITS_TO_4BYTE(status + 4, 24, 8) 130*4882a593Smuzhiyun #define GET_STATUS_HISR_LOW8BIT(status) LE_BITS_TO_4BYTE(status + 4, 16, 8) 131*4882a593Smuzhiyun #define GET_STATUS_ERROR(status) LE_BITS_TO_4BYTE(status + 4, 17, 1) 132*4882a593Smuzhiyun #define GET_STATUS_INT(status) LE_BITS_TO_4BYTE(status + 4, 16, 1) 133*4882a593Smuzhiyun #define GET_STATUS_RX_LENGTH(status) LE_BITS_TO_4BYTE(status + 4, 0, 16) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #define RXDESC_SIZE 24 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct spi_more_data { 140*4882a593Smuzhiyun unsigned long more_data; 141*4882a593Smuzhiyun unsigned long len; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* __GSPI_OPS_H__ */ 145