1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2020 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _PHL_CHNLPLAN_6GHZ_H_ 16*4882a593Smuzhiyun #define _PHL_CHNLPLAN_6GHZ_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * 6 GHz channel group from UNII-5 to UNII-8 21*4882a593Smuzhiyun * channel index diff is 4 : minimum working bandwidth : 20 MHz 22*4882a593Smuzhiyun * => next channel index = current index + 4 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun struct chdef_6ghz { 26*4882a593Smuzhiyun /* ch_def index */ 27*4882a593Smuzhiyun u8 idx; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * UNII-5 support channel list, ch1 ~ ch93, total : 24 31*4882a593Smuzhiyun * bit0 stands for ch1 32*4882a593Smuzhiyun * bit1 stands for ch5 33*4882a593Smuzhiyun * bit2 stands for ch9 34*4882a593Smuzhiyun * ... 35*4882a593Smuzhiyun * bit23 stands for ch93 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun u8 support_ch_u5[3]; 38*4882a593Smuzhiyun u8 passive_u5[3]; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* 41*4882a593Smuzhiyun * UNII-6 support channel list, ch97 ~ ch117, total : 6 42*4882a593Smuzhiyun * bit0 stands for ch97 43*4882a593Smuzhiyun * bit1 stands for ch101 44*4882a593Smuzhiyun * bit2 stands for ch105 45*4882a593Smuzhiyun * bit3 stands for ch109 46*4882a593Smuzhiyun * bit4 stands for ch113 47*4882a593Smuzhiyun * bit5 stands for ch117 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun u8 support_ch_u6; 50*4882a593Smuzhiyun u8 passive_u6; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * UNII-7 support channel list, ch121 ~ ch189, total : 18 54*4882a593Smuzhiyun * bit0 stands for ch121 55*4882a593Smuzhiyun * bit1 stands for ch125 56*4882a593Smuzhiyun * bit2 stands for ch129 57*4882a593Smuzhiyun * ... 58*4882a593Smuzhiyun * bit17 stands for ch189 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun u8 support_ch_u7[3]; 61*4882a593Smuzhiyun u8 passive_u7[3]; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * UNII-8 support channel list, ch193 ~ ch237, total : 12 65*4882a593Smuzhiyun * bit0 stands for ch193 66*4882a593Smuzhiyun * bit1 stands for ch197 67*4882a593Smuzhiyun * bit2 stands for ch201 68*4882a593Smuzhiyun * ... 69*4882a593Smuzhiyun * bit10 stands for ch233 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun u8 support_ch_u8[2]; 72*4882a593Smuzhiyun u8 passive_u8[2]; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct regulatory_domain_mapping_6g { 76*4882a593Smuzhiyun u8 domain_code; 77*4882a593Smuzhiyun u8 regulation; 78*4882a593Smuzhiyun u8 ch_idx; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define MAX_CHDEF_6GHZ 6 82*4882a593Smuzhiyun #define MAX_RD_MAP_NUM_6GHZ 6 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* _PHL_CHNLPLAN_6GHZ_H_ */ 86