1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2020 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26 #ifndef __HALRF_H__ 27 #define __HALRF_H__ 28 29 /*@--------------------------[Define] ---------------------------------------*/ 30 31 /*H2C cmd ID*/ 32 /*Class 8*/ 33 /*Class 9*/ 34 /*Class a*/ 35 #define FWCMD_H2C_BACKUP_RFK 0 36 #define FWCMD_H2C_RELOAD_RFK 1 37 #define FWCMD_H2C_GET_MCCCH 2 38 #define FWCMD_H2C_DPK_OFFLOAD 3 39 #define FWCMD_H2C_IQK_OFFLOAD 4 40 41 /*@--------------------------[Enum]------------------------------------------*/ 42 enum halrf_func_idx { 43 RF00_PWR_TRK = 0, 44 RF01_IQK = 1, 45 RF02_LCK = 2, 46 RF03_DPK = 3, 47 RF04_TXGAPK = 4, 48 RF05_DACK = 5, 49 RF06_DPK_TRK = 6, 50 RF07_2GBAND_SHIFT = 7, 51 RF08_RXDCK = 8, 52 RF09_RFK = 9, 53 RF10_RF_INIT = 10, 54 RF11_RF_POWER = 11, 55 RF12_RXGAINK = 12, 56 RF13_THER_TRIM = 13, 57 RF14_PABIAS_TRIM = 14, 58 RF15_TSSI_TRIM = 15, 59 RF16_PSD = 16, 60 RF17_TSSI_TRK = 17, 61 RF18_XTAL_TRK = 18, 62 RF19_TX_SHAPE = 19 63 }; 64 65 enum halrf_rf_mode { 66 RF_SHUT_DOWN = 0x0, 67 RF_STANDBY = 0x1, 68 RF_TX = 0x2, 69 RF_RX = 0x3, 70 RF_TXIQK = 0x4, 71 RF_DPK = 0x5, 72 RF_RXK1 = 0x6, 73 RF_RXK2 = 0x7 74 }; 75 76 enum halrf_rfe_src_sel { 77 HALRF_PAPE_RFM = 0, 78 HALRF_GNT_BT_INV = 1, 79 HALRF_LNA0N = 2, 80 HALRF_LNAON_RFM = 3, 81 HALRF_TRSW_RFM = 4, 82 HALRF_TRSW_RFM_B = 5, 83 HALRF_GNT_BT = 6, 84 HALRF_ZERO = 7, 85 HALRF_ANTSEL_0 = 8, 86 HALRF_ANTSEL_1 = 9, 87 HALRF_ANTSEL_2 = 0xa, 88 HALRF_ANTSEL_3 = 0xb, 89 HALRF_ANTSEL_4 = 0xc, 90 HALRF_ANTSEL_5 = 0xd, 91 HALRF_ANTSEL_6 = 0xe, 92 HALRF_ANTSEL_7 = 0xf 93 }; 94 95 /*@=[HALRF supportability]=======================================*/ 96 enum halrf_ability { 97 HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), 98 HAL_RF_IQK = BIT(RF01_IQK), 99 HAL_RF_LCK = BIT(RF02_LCK), 100 HAL_RF_DPK = BIT(RF03_DPK), 101 HAL_RF_TXGAPK = BIT(RF04_TXGAPK), 102 HAL_RF_DACK = BIT(RF05_DACK), 103 HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK), 104 HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT), 105 HAL_RF_RXDCK = BIT(RF08_RXDCK), 106 HAL_RF_RXGAINK = BIT(RF12_RXGAINK), 107 HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM), 108 HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM), 109 HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM), 110 HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK), 111 HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK), 112 HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE) 113 }; 114 115 /*@=[HALRF Debug Component]=====================================*/ 116 enum halrf_dbg_comp { 117 DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK), 118 DBG_RF_IQK = BIT(RF01_IQK), 119 DBG_RF_LCK = BIT(RF02_LCK), 120 DBG_RF_DPK = BIT(RF03_DPK), 121 DBG_RF_TXGAPK = BIT(RF04_TXGAPK), 122 DBG_RF_DACK = BIT(RF05_DACK), 123 DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK), 124 DBG_RF_RXDCK = BIT(RF08_RXDCK), 125 DBG_RF_RFK = BIT(RF09_RFK), 126 DBG_RF_INIT = BIT(RF10_RF_INIT), 127 DBG_RF_POWER = BIT(RF11_RF_POWER), 128 DBG_RF_RXGAINK = BIT(RF12_RXGAINK), 129 DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM), 130 DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM), 131 DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM), 132 DBG_RF_PSD = BIT(RF16_PSD), 133 DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK), 134 DBG_RF_FW = BIT(28), 135 DBG_RF_MP = BIT(29), 136 DBG_RF_TMP = BIT(30), 137 DBG_RF_CHK = BIT(31) 138 }; 139 140 141 /*@--------------------------[Structure]-------------------------------------*/ 142 143 struct rfk_location { 144 enum band_type cur_band; 145 enum channel_width cur_bw; 146 u8 cur_ch; 147 }; 148 149 struct halrf_fem_info { 150 u8 elna_2g; /*@with 2G eLNA NO/Yes = 0/1*/ 151 u8 elna_5g; /*@with 5G eLNA NO/Yes = 0/1*/ 152 u8 elna_6g; /*@with 6G eLNA NO/Yes = 0/1*/ 153 u8 epa_2g; /*@with 2G ePA NO/Yes = 0/1*/ 154 u8 epa_5g; /*@with 5G ePA NO/Yes = 0/1*/ 155 u8 epa_6g; /*@with 6G ePA NO/Yes = 0/1*/ 156 }; 157 158 #if 1 /* all rf operation usage (header) */ 159 160 /* clang-format on */ 161 #define RF_PATH_MAX_NUM (8) 162 #define RF_TASK_RECORD_MAX_TIMES (16) 163 #define RF_BACKUP_MAC_REG_MAX_NUM (16) 164 #define RF_BACKUP_BB_REG_MAX_NUM (16) 165 #define RF_BACKUP_RF_REG_MAX_NUM (16) 166 167 struct halrf_iqk_ops { 168 u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx); 169 bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy, u8 path); 170 void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy, u8 path); 171 void (*iqk_preset)(struct rf_info *rf, u8 path); 172 void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); 173 void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); 174 void (*iqk_restore)(struct rf_info *rf, u8 path); 175 void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path); 176 }; 177 178 struct rfk_iqk_info { 179 struct halrf_iqk_ops *rf_iqk_ops; 180 u8 rf_max_path_num; 181 u32 rf_iqk_version; 182 u8 rf_iqk_ch_num; 183 u8 rf_iqk_path_num; 184 185 const u32 *backup_mac_reg; 186 u32 backup_mac_reg_num; 187 const u32 *backup_bb_reg; 188 u32 backup_bb_reg_num; 189 const u32 *backup_rf_reg; 190 u32 backup_rf_reg_num; 191 }; 192 /* clang-format off */ 193 #endif /* all rf operation usage (header) */ 194 195 #ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT 196 struct halrf_fw_offload { 197 enum rtw_mac_src_cmd_ofld src; 198 enum rtw_mac_cmd_type_ofld type; 199 u8 lc; 200 enum rtw_mac_rf_path rf_path; 201 u16 offset; 202 u16 id; 203 u32 value; 204 u32 mask; 205 }; 206 #endif 207 208 struct halrf_rx_dck_info { 209 bool is_afe; 210 struct rfk_location loc[KPATH]; /*max RF path*/ 211 }; 212 213 struct rf_info { 214 struct rtw_phl_com_t *phl_com; 215 struct rtw_hal_com_t *hal_com; 216 /*[Common Info]*/ 217 u32 ic_type; 218 u8 num_rf_path; 219 /*[System Info]*/ 220 bool rf_init_ready; 221 u32 rf_sys_up_time; 222 bool rf_watchdog_en; 223 bool rf_ic_api_en; 224 /*[DM Info]*/ 225 u32 support_ability; 226 u32 manual_support_ability; 227 /*[FW Info]*/ 228 u32 fw_dbg_component; 229 /*[Drv Dbg Info]*/ 230 u32 dbg_component; 231 u8 cmn_dbg_msg_period; 232 u8 cmn_dbg_msg_cnt; 233 /*[BTC / RFK Info ]*/ 234 bool rfk_is_processing; 235 bool is_bt_iqk_timeout; 236 /*[initial]*/ 237 u8 pre_rxbb_bw[KPATH]; 238 /*[TSSI Info]*/ 239 bool is_tssi_mode[4]; /*S0/S1*/ 240 /*[Thermal Trigger]*/ 241 bool is_thermal_trigger; 242 /*[Do Coex]*/ 243 bool is_coex; 244 /*[watchdog]*/ 245 bool is_watchdog_stop; 246 /*[thermal rek indictor]*/ 247 bool rfk_do_thr_rek; 248 /*reg check*/ 249 u32 rfk_reg[2048]; 250 u32 rfc_reg[2][10]; 251 u32 rfk_check_fail_count; 252 /*fast channel switch*/ 253 u8 ther_init; 254 u32 fcs_rfk_ok_map; 255 u8 pre_chl_idx; 256 u8 pre_ther_idx; 257 /* [Check NCTL Done status Read Times] */ 258 u32 nctl_ck_times[2]; /* 0xbff8 0x80fc*/ 259 u32 fw_ofld_enable; 260 261 /*@=== [HALRF Structure] ============================================*/ 262 struct halrf_pwr_track_info pwr_track; 263 struct halrf_tssi_info tssi; 264 struct halrf_xtal_info xtal_track; 265 struct halrf_iqk_info iqk; 266 struct halrf_dpk_info dpk; 267 struct halrf_rx_dck_info rx_dck; 268 struct halrf_dack_info dack; 269 struct halrf_gapk_info gapk; 270 struct halrf_pwr_info pwr_info; 271 struct halrf_radio_info radio_info; 272 struct halrf_fem_info fem; 273 struct rf_dbg_cmd_info rf_dbg_cmd_i; 274 struct halrf_kfree_info kfree_info; 275 struct halrf_psd_data psd; 276 struct rfk_location iqk_loc[2]; /*S0/S1*/ 277 struct rfk_location dpk_loc[2]; /*S0/S1*/ 278 struct rfk_location gapk_loc[2]; /*S0/S1*/ 279 struct rfk_iqk_info *rfk_iqk_info; 280 #ifdef HALRF_CONFIG_FW_IO_OFLD_SUPPORT 281 struct halrf_fw_offload fwofld; 282 #endif 283 }; 284 285 /*@--------------------------[Prptotype]-------------------------------------*/ 286 287 288 #endif 289 290