1 /** @file */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of version 2 of the GNU General Public License as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 ******************************************************************************/ 16 17 #ifndef __HALMAC_PCIE_REG_H__ 18 #define __HALMAC_PCIE_REG_H__ 19 20 /* PCIE PHY register */ 21 #define RAC_CTRL_PPR 0x00 22 #define RAC_ANA10 0x10 23 #define RAC_ANA19 0x19 24 25 #define RAC_REG_REV2 0x1B 26 #define BAC_CMU_EN_DLY_SH 12 27 #define BAC_CMU_EN_DLY_MSK 0xF 28 29 #define RAC_REG_FLD_0 0x1D 30 #define BAC_AUTOK_N_SH 2 31 #define BAC_AUTOK_N_MSK 0x3 32 33 #define RAC_ANA1F 0x1F 34 #define RAC_SET_PPR 0x20 35 #define RAC_TRG_PPR 0x21 36 #define RAC_ANA24 0x24 37 #define RAC_ANA26 0x26 38 39 #define RAC_CTRL_PPR_V1 0x30 40 #define BAC_AUTOK_DIV_SH 14 41 #define BAC_AUTOK_DIV_MSK 0x3 42 #define BAC_AUTOK_EN BIT(13) 43 #define BAC_AUTOK_ONCE_EN BIT(12) 44 #define BAC_AUTOK_HW_TAR_SH 0 45 #define BAC_AUTOK_HW_TAR_MSK 0xFFF 46 47 #define RAC_SET_PPR_V1 0x31 48 #define BAC_AUTOK_MGN_SH 12 49 #define BAC_AUTOK_MGN_MSK 0xF 50 #define BAC_AUTOK_TAR_SH 0 51 #define BAC_AUTOK_TAR_MSK 0xFFF 52 53 /* PCIE CFG register */ 54 #define PCIE_L1_STS 0x80 55 #define PCIE_PHY_RATE 0x82 56 #define PCIE_L1SS_CTRL 0x718 57 #define PCIE_L1_CTRL 0x719 58 #define PCIE_ACK_NFTS 0x70D 59 #define PCIE_COM_CLK_NFTS 0x70E 60 #define PCIE_FTS 0x80C 61 #define PCIE_ASPM_CTRL 0x70F 62 #define PCIE_CLK_CTRL 0x725 63 #define CFG_RST_MSTATE 0xB48 64 #define PCIE_L1SS_CAP 0x160 65 #define PCIE_L1SS_SUP 0x164 66 #define PCIE_L1SS_STS 0x168 67 68 /* PCIE CFG bit */ 69 #define PCIE_BIT_STS_L0S BIT(0) 70 #define PCIE_BIT_STS_L1 BIT(1) 71 #define PCIE_BIT_WAKE BIT(2) 72 #define PCIE_BIT_L1 BIT(3) 73 #define PCIE_BIT_CLK BIT(4) 74 #define PCIE_BIT_L0S BIT(7) 75 #define PCIE_BIT_L1SS BIT(5) 76 #define PCIE_BIT_L1SSSUP BIT(4) 77 78 /* PCIE ASPM mask*/ 79 #define SHFT_L1DLY 3 80 #define SHFT_L0SDLY 0 81 #define PCIE_ASPMDLY_MASK 0x07 82 #define PCIE_L1SS_MASK 0x0F 83 84 /* PCIE Capability */ 85 #define PCIE_L1SS_ID 0x001E 86 87 /* PCIE MAC register */ 88 #define LINK_CTRL2_REG_OFFSET 0xA0 89 #define GEN2_CTRL_OFFSET 0x80C 90 #define LINK_STATUS_REG_OFFSET 0x82 91 92 #define PCIE_GEN1_SPEED 0x01 93 #define PCIE_GEN2_SPEED 0x02 94 95 #endif/* __HALMAC_PCIE_REG_H__ */ 96