1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2019 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 *****************************************************************************/ 15 #ifndef _RTW_MP_H_ 16 #define _RTW_MP_H_ 17 18 #include <drv_types.h> 19 20 #define RTWPRIV_VER_INFO 1 21 22 #define MAX_MP_XMITBUF_SZ 2048 23 #define NR_MP_XMITFRAME 8 24 #define MP_READ_REG_MAX_OFFSET 0x4FFF 25 26 #define TX_POWER_BASE 4 /* dbm * 4 */ 27 #define TX_POWER_CODE_WORD_BASE 8 /* dbm * 8 */ 28 29 struct mp_xmit_frame { 30 _list list; 31 32 struct pkt_attrib attrib; 33 34 struct sk_buff *pkt; 35 36 int frame_tag; 37 38 _adapter *padapter; 39 40 #ifdef CONFIG_USB_HCI 41 42 /* insert urb, irp, and irpcnt info below... */ 43 /* max frag_cnt = 8 */ 44 u8 *mem_addr; 45 u32 sz[8]; 46 u8 bpending[8]; 47 sint ac_tag[8]; 48 sint last[8]; 49 uint irpcnt; 50 uint fragcnt; 51 #endif /* CONFIG_USB_HCI */ 52 53 uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; 54 }; 55 56 struct mp_wiparam { 57 u32 bcompleted; 58 u32 act_type; 59 u32 io_offset; 60 u32 io_value; 61 }; 62 63 typedef void(*wi_act_func)(void *padapter); 64 65 struct mp_tx { 66 u8 stop; 67 u32 count, sended; 68 u8 payload; 69 struct pkt_attrib attrib; 70 /* struct tx_desc desc; */ 71 /* u8 resvdtx[7]; */ 72 u8 desc[TXDESC_SIZE]; 73 u8 *pallocated_buf; 74 u8 *buf; 75 u32 buf_size, write_size; 76 _thread_hdl_ PktTxThread; 77 }; 78 79 #define MP_MAX_LINES 1000 80 #define MP_MAX_LINES_BYTES 256 81 82 83 typedef struct _RT_PMAC_PKT_INFO { 84 u8 MCS; 85 u8 Nss; 86 u8 Nsts; 87 u32 N_sym; 88 u8 SIGA2B3; 89 } RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO; 90 91 typedef struct _RT_PMAC_TX_INFO { 92 u8 bEnPMacTx:1; /* 0: Disable PMac 1: Enable PMac */ 93 u8 Mode:3; /* 0: Packet TX 3:Continuous TX */ 94 u8 Ntx:4; /* 0-7 */ 95 u8 TX_RATE; /* MPT_RATE_E */ 96 u8 TX_RATE_HEX; 97 u8 TX_SC; 98 u8 bSGI:1; 99 u8 bSPreamble:1; 100 u8 bSTBC:1; 101 u8 bLDPC:1; 102 u8 NDP_sound:1; 103 u8 BandWidth:3; /* 0: 20 1:40 2:80Mhz */ 104 u8 m_STBC; /* bSTBC + 1 */ 105 u16 PacketPeriod; 106 u32 PacketCount; 107 u32 PacketLength; 108 u8 PacketPattern; 109 u16 SFD; 110 u8 SignalField; 111 u8 ServiceField; 112 u16 LENGTH; 113 u8 CRC16[2]; 114 u8 LSIG[3]; 115 u8 HT_SIG[6]; 116 u8 VHT_SIG_A[6]; 117 u8 VHT_SIG_B[4]; 118 u8 VHT_SIG_B_CRC; 119 u8 VHT_Delimiter[4]; 120 u8 MacAddress[6]; 121 } RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO; 122 123 struct rtw_mp_giltf_data { 124 u8 gi; 125 u8 ltf; 126 char type_str[8]; 127 }; 128 129 typedef void (*MPT_WORK_ITEM_HANDLER)(void *adapter); 130 typedef struct _MPT_CONTEXT { 131 /* Indicate if we have started Mass Production Test. */ 132 BOOLEAN bMassProdTest; 133 134 /* Indicate if the driver is unloading or unloaded. */ 135 BOOLEAN bMptDrvUnload; 136 137 _sema MPh2c_Sema; 138 _timer MPh2c_timeout_timer; 139 /* Event used to sync H2c for BT control */ 140 141 BOOLEAN MptH2cRspEvent; 142 BOOLEAN MptBtC2hEvent; 143 BOOLEAN bMPh2c_timeout; 144 145 /* 8190 PCI does not support NDIS_WORK_ITEM. */ 146 /* Work Item for Mass Production Test. */ 147 /* NDIS_WORK_ITEM MptWorkItem; 148 * RT_WORK_ITEM MptWorkItem; */ 149 /* Event used to sync the case unloading driver and MptWorkItem is still in progress. 150 * NDIS_EVENT MptWorkItemEvent; */ 151 /* To protect the following variables. 152 * NDIS_SPIN_LOCK MptWorkItemSpinLock; */ 153 /* Indicate a MptWorkItem is scheduled and not yet finished. */ 154 BOOLEAN bMptWorkItemInProgress; 155 /* An instance which implements function and context of MptWorkItem. */ 156 MPT_WORK_ITEM_HANDLER CurrMptAct; 157 158 /* 1=Start, 0=Stop from UI. */ 159 u32 MptTestStart; 160 /* _TEST_MODE, defined in MPT_Req2.h */ 161 u32 MptTestItem; 162 /* Variable needed in each implementation of CurrMptAct. */ 163 u32 MptActType; /* Type of action performed in CurrMptAct. */ 164 /* The Offset of IO operation is depend of MptActType. */ 165 u32 MptIoOffset; 166 /* The Value of IO operation is depend of MptActType. */ 167 u32 MptIoValue; 168 /* The RfPath of IO operation is depend of MptActType. */ 169 170 u32 mpt_rf_path; 171 172 u8 MptChannelToSw; /* Channel to switch. */ 173 u8 MptInitGainToSet; /* Initial gain to set. */ 174 /* u32 bMptAntennaA; */ /* TRUE if we want to use antenna A. */ 175 u32 MptBandWidth; /* bandwidth to switch. */ 176 177 u32 mpt_rate_index;/* rate index. */ 178 179 /* Register value kept for Single Carrier Tx test. */ 180 u8 btMpCckTxPower; 181 /* Register value kept for Single Carrier Tx test. */ 182 u8 btMpOfdmTxPower; 183 /* For MP Tx Power index */ 184 u8 TxPwrLevel[4]; /* rf-A, rf-B*/ 185 u32 RegTxPwrLimit; 186 /* Content of RCR Regsiter for Mass Production Test. */ 187 u32 MptRCR; 188 /* TRUE if we only receive packets with specific pattern. */ 189 BOOLEAN bMptFilterPattern; 190 /* Rx OK count, statistics used in Mass Production Test. */ 191 u32 MptRxOkCnt; 192 /* Rx CRC32 error count, statistics used in Mass Production Test. */ 193 u32 MptRxCrcErrCnt; 194 195 BOOLEAN bCckContTx; /* TRUE if we are in CCK Continuous Tx test. */ 196 BOOLEAN bOfdmContTx; /* TRUE if we are in OFDM Continuous Tx test. */ 197 /* TRUE if we have start Continuous Tx test. */ 198 BOOLEAN is_start_cont_tx; 199 200 /* TRUE if we are in Single Carrier Tx test. */ 201 BOOLEAN bSingleCarrier; 202 /* TRUE if we are in Carrier Suppression Tx Test. */ 203 204 BOOLEAN is_carrier_suppression; 205 206 /* TRUE if we are in Single Tone Tx test. */ 207 208 BOOLEAN is_single_tone; 209 210 211 /* ACK counter asked by K.Y.. */ 212 BOOLEAN bMptEnableAckCounter; 213 u32 MptAckCounter; 214 215 /* SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! */ 216 /* s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */ 217 /* s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */ 218 /* s32 RfReadLine[2]; */ 219 220 u8 APK_bound[2]; /* for APK path A/path B */ 221 BOOLEAN bMptIndexEven; 222 223 u8 backup0xc50; 224 u8 backup0xc58; 225 u8 backup0xc30; 226 u8 backup0x52_RF_A; 227 u8 backup0x52_RF_B; 228 229 u32 backup0x58_RF_A; 230 u32 backup0x58_RF_B; 231 232 u8 h2cReqNum; 233 u8 c2hBuf[32]; 234 235 u8 btInBuf[100]; 236 u32 mptOutLen; 237 u8 mptOutBuf[100]; 238 RT_PMAC_TX_INFO PMacTxInfo; 239 RT_PMAC_PKT_INFO PMacPktInfo; 240 u8 HWTxmode; 241 242 BOOLEAN bldpc; 243 BOOLEAN bstbc; 244 } MPT_CONTEXT, *PMPT_CONTEXT; 245 /* #endif */ 246 247 248 /* #define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) */ 249 enum { 250 WRITE_REG = 1, 251 READ_REG, 252 WRITE_RF, 253 READ_RF, 254 MP_START, 255 MP_STOP, 256 MP_RATE, 257 MP_CHANNEL, 258 MP_TRXSC_OFFSET, 259 MP_BANDWIDTH, 260 MP_TXPOWER, 261 MP_ANT_TX, 262 MP_ANT_RX, 263 MP_CTX, 264 MP_QUERY, 265 MP_ARX, 266 MP_PSD, 267 MP_PWRTRK, 268 MP_THER, 269 MP_IOCTL, 270 EFUSE_GET, 271 EFUSE_SET, 272 MP_RESET_STATS, 273 MP_DUMP, 274 MP_PHYPARA, 275 MP_SetRFPathSwh, 276 MP_QueryDrvStats, 277 CTA_TEST, 278 MP_DISABLE_BT_COEXIST, 279 MP_PwrCtlDM, 280 MP_GETVER, 281 MP_MON, 282 EFUSE_BT_MASK, 283 EFUSE_MASK, 284 EFUSE_FILE, 285 EFUSE_FILE_STORE, 286 MP_TX, 287 MP_RX, 288 MP_IQK, 289 MP_LCK, 290 MP_HW_TX_MODE, 291 MP_GET_TXPOWER_INX, 292 MP_CUSTOMER_STR, 293 MP_PWRLMT, 294 MP_PWRBYRATE, 295 BT_EFUSE_FILE, 296 MP_SWRFPath, 297 MP_LINK, 298 MP_DPK_TRK, 299 MP_DPK, 300 MP_GET_TSSIDE, 301 MP_SET_TSSIDE, 302 MP_GET_PHL_TEST, 303 MP_SET_PHL_TEST, 304 MP_SET_PHL_TX_PATTERN, 305 MP_SET_PHL_PLCP_TX_DATA, 306 MP_SET_PHL_PLCP_TX_USER, 307 MP_SET_PHL_TX_METHOD, 308 MP_SET_PHL_CONIFG_PHY_NUM, 309 MP_PHL_RFK, 310 MP_PHL_BTC_PATH, 311 MP_GET_HE, 312 MP_UUID, 313 MP_GPIO, 314 MP_NULL, 315 #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE 316 VENDOR_IE_SET , 317 VENDOR_IE_GET , 318 #endif 319 #if defined(RTW_PHL_TX) || defined(RTW_PHL_RX) || defined(CONFIG_PHL_TEST_SUITE) 320 PHL_TEST_SET, 321 PHL_TEST_GET, 322 #endif 323 #ifdef CONFIG_WOWLAN 324 MP_WOW_ENABLE, 325 MP_WOW_SET_PATTERN, 326 #endif 327 #ifdef CONFIG_AP_WOWLAN 328 MP_AP_WOW_ENABLE, 329 #endif 330 MP_SD_IREAD, 331 MP_SD_IWRITE, 332 }; 333 334 struct rtw_plcp_user { 335 u8 plcp_usr_idx; 336 u16 plcp_mcs; 337 u8 coding; 338 u8 dcm; 339 u8 aid; 340 u32 plcp_txlen; /*apep*/ 341 u32 ru_alloc; 342 u8 plcp_nss; 343 u8 txbf; 344 u8 pwr_boost_db; 345 }; 346 347 struct mp_priv { 348 _adapter *papdater; 349 350 /* Testing Flag */ 351 u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */ 352 353 u32 prev_fw_state; 354 355 /* OID cmd handler */ 356 struct mp_wiparam workparam; 357 /* u8 act_in_progress; */ 358 359 /* Tx Section */ 360 u8 TID; 361 u32 tx_pktcount; 362 u32 pktInterval; 363 u32 pktLength; 364 struct mp_tx tx; 365 366 /* Rx Section */ 367 u32 rx_bssidpktcount; 368 u32 rx_pktcount; 369 u32 rx_pktcount_filter_out; 370 u32 rx_crcerrpktcount; 371 u32 rx_pktloss; 372 BOOLEAN rx_bindicatePkt; 373 struct recv_stat rxstat; 374 BOOLEAN brx_filter_beacon; 375 376 /* RF/BB relative */ 377 u8 channel; 378 u8 bandwidth; 379 u8 prime_channel_offset; 380 u8 txpoweridx; 381 s16 txpowerdbm; 382 u16 rateidx; 383 s16 pre_refcw_cck_pwridxa; 384 s16 pre_refcw_cck_pwridxb; 385 s16 pre_refcw_ofdm_pwridxa; 386 s16 pre_refcw_ofdm_pwridxb; 387 388 u32 preamble; 389 /* u8 modem; */ 390 u32 CrystalCap; 391 /* u32 curr_crystalcap; */ 392 393 u8 antenna_tx; 394 u8 antenna_rx; 395 u8 antenna_trx; 396 /* u8 curr_rfpath; */ 397 398 u8 check_mp_pkt; 399 400 u8 bSetTxPower; 401 /* uint ForcedDataRate; */ 402 u8 mp_dm; 403 u8 mac_filter[ETH_ALEN]; 404 u8 bmac_filter; 405 406 /* RF PATH Setting for WLG WLA BTG BT */ 407 u8 rf_path_cfg; 408 u8 btc_path; /* BTC_MODE_NORMAL, BTC_MODE_WL,BTC_MODE_BT */ 409 410 struct wlan_network mp_network; 411 NDIS_802_11_MAC_ADDRESS network_macaddr; 412 413 u8 *pallocated_mp_xmitframe_buf; 414 u8 *pmp_xmtframe_buf; 415 _queue free_mp_xmitqueue; 416 u32 free_mp_xmitframe_cnt; 417 BOOLEAN bSetRxBssid; 418 BOOLEAN bTxBufCkFail; 419 BOOLEAN bRTWSmbCfg; 420 BOOLEAN bloopback; 421 BOOLEAN bloadefusemap; 422 BOOLEAN bloadBTefusemap; 423 BOOLEAN bprocess_mp_mode; 424 425 MPT_CONTEXT mpt_ctx; 426 427 u8 *TXradomBuffer; 428 u8 mp_keep_btc_mode; 429 u8 mplink_buf[2048]; 430 u32 mplink_rx_len; 431 BOOLEAN mplink_brx; 432 BOOLEAN mplink_btx; 433 434 bool tssitrk_on; 435 u8 tssi_mode; 436 u8 rtw_mp_cur_phy; 437 u8 rtw_mp_dbcc; 438 s16 path_pwr_offset[4]; /* rf-A, rf-B*/ 439 u8 rtw_mp_tx_method; 440 u16 rtw_mp_tx_time; 441 u8 rtw_mp_tx_state; 442 u8 rtw_mp_pmact_patt_idx; 443 u8 rtw_mp_pmact_ppdu_type; 444 u8 rtw_mp_data_bandwidth; 445 u8 rtw_mp_stbc; 446 u8 rtw_mp_plcp_gi; 447 u8 rtw_mp_plcp_ltf; 448 u8 rtw_mp_he_sigb; 449 u8 rtw_mp_he_sigb_dcm; 450 u32 rtw_mp_plcp_tx_time; 451 u8 rtw_mp_plcp_tx_mode; 452 453 u8 rtw_mp_he_er_su_ru_106_en; 454 u8 rtw_mp_trxsc; 455 u16 rtw_mp_plcp_rualloc; 456 u8 rtw_mp_plcp_tx_user; 457 u32 rtw_mp_ru_tone; 458 u8 ru_tone_sel_list[6]; 459 u8 ru_alloc_list[68]; 460 461 struct rtw_mp_giltf_data st_giltf[5]; 462 struct rtw_plcp_user mp_plcp_user[4]; 463 u8 mp_plcp_useridx; 464 465 u8 keep_ips_status; 466 u8 keep_lps_status; 467 u8 tx_shape_idx; 468 u8 gpio_id; 469 u8 gpio_enable; 470 }; 471 472 #define PPDU_TYPE_STR(idx)\ 473 (idx == RTW_MP_TYPE_CCK) ? "CCK" :\ 474 (idx == RTW_MP_TYPE_LEGACY) ? "LEGACY" :\ 475 (idx == RTW_MP_TYPE_HT_MF) ? "HT_MF" :\ 476 (idx == RTW_MP_TYPE_HT_GF) ? "HT_GF" :\ 477 (idx == RTW_MP_TYPE_VHT) ? "VHT" :\ 478 (idx == RTW_MP_TYPE_HE_SU) ? "HE_SU" :\ 479 (idx == RTW_MP_TYPE_HE_ER_SU) ? "HE_ER_SU" :\ 480 (idx == RTW_MP_TYPE_HE_MU_OFDMA) ? "HE_MU" :\ 481 (idx == RTW_MP_TYPE_HE_TB) ? "HE_TB" :\ 482 "UNknow" 483 484 485 typedef struct _IOCMD_STRUCT_ { 486 u8 cmdclass; 487 u16 value; 488 u8 index; 489 } IOCMD_STRUCT; 490 491 struct rf_reg_param { 492 u32 path; 493 u32 offset; 494 u32 value; 495 }; 496 497 struct bb_reg_param { 498 u32 offset; 499 u32 value; 500 }; 501 502 /* *********************************************************************** */ 503 504 #define LOWER _TRUE 505 #define RAISE _FALSE 506 507 /* Hardware Registers */ 508 #if 0 509 #if 0 510 #define IOCMD_CTRL_REG 0x102502C0 511 #define IOCMD_DATA_REG 0x102502C4 512 #else 513 #define IOCMD_CTRL_REG 0x10250370 514 #define IOCMD_DATA_REG 0x10250374 515 #endif 516 517 #define IOCMD_GET_THERMAL_METER 0xFD000028 518 519 #define IOCMD_CLASS_BB_RF 0xF0 520 #define IOCMD_BB_READ_IDX 0x00 521 #define IOCMD_BB_WRITE_IDX 0x01 522 #define IOCMD_RF_READ_IDX 0x02 523 #define IOCMD_RF_WRIT_IDX 0x03 524 #endif 525 #define BB_REG_BASE_ADDR 0x800 526 527 /* MP variables */ 528 #if 0 529 #define _2MAC_MODE_ 0 530 #define _LOOPBOOK_MODE_ 1 531 #endif 532 533 typedef enum _MP_MODE_ { 534 MP_OFF, 535 MP_ON, 536 MP_ERR, 537 MP_CONTINUOUS_TX, 538 MP_SINGLE_CARRIER_TX, 539 MP_CARRIER_SUPPRISSION_TX, 540 MP_SINGLE_TONE_TX, 541 MP_PACKET_TX, 542 MP_PACKET_RX 543 } MP_MODE; 544 545 typedef enum _TEST_MODE { 546 TEST_NONE , 547 PACKETS_TX , 548 PACKETS_RX , 549 CONTINUOUS_TX , 550 OFDM_Single_Tone_TX , 551 CCK_Carrier_Suppression_TX 552 } TEST_MODE; 553 554 typedef enum _MPT_BANDWIDTH { 555 MPT_BW_20MHZ = 0, 556 MPT_BW_40MHZ_DUPLICATE = 1, 557 MPT_BW_40MHZ_ABOVE = 2, 558 MPT_BW_40MHZ_BELOW = 3, 559 MPT_BW_40MHZ = 4, 560 MPT_BW_80MHZ = 5, 561 MPT_BW_80MHZ_20_ABOVE = 6, 562 MPT_BW_80MHZ_20_BELOW = 7, 563 MPT_BW_80MHZ_20_BOTTOM = 8, 564 MPT_BW_80MHZ_20_TOP = 9, 565 MPT_BW_80MHZ_40_ABOVE = 10, 566 MPT_BW_80MHZ_40_BELOW = 11, 567 } MPT_BANDWIDTHE, *PMPT_BANDWIDTH; 568 569 #define MAX_RF_PATH_NUMS RF_PATH_MAX 570 571 572 extern u8 mpdatarate[NumRates]; 573 574 /* MP set force data rate base on the definition. */ 575 typedef enum _MPT_RATE_INDEX { 576 /* CCK rate. */ 577 MPT_RATE_1M = 1 , /* 0 */ 578 MPT_RATE_2M, 579 MPT_RATE_55M, 580 MPT_RATE_11M, /* 3 */ 581 582 /* OFDM rate. */ 583 MPT_RATE_6M, /* 4 */ 584 MPT_RATE_9M, 585 MPT_RATE_12M, 586 MPT_RATE_18M, 587 MPT_RATE_24M, 588 MPT_RATE_36M, 589 MPT_RATE_48M, 590 MPT_RATE_54M, /* 11 */ 591 592 /* HT rate. */ 593 MPT_RATE_MCS0, /* 12 */ 594 MPT_RATE_MCS1, 595 MPT_RATE_MCS2, 596 MPT_RATE_MCS3, 597 MPT_RATE_MCS4, 598 MPT_RATE_MCS5, 599 MPT_RATE_MCS6, 600 MPT_RATE_MCS7, /* 19 */ 601 MPT_RATE_MCS8, 602 MPT_RATE_MCS9, 603 MPT_RATE_MCS10, 604 MPT_RATE_MCS11, 605 MPT_RATE_MCS12, 606 MPT_RATE_MCS13, 607 MPT_RATE_MCS14, 608 MPT_RATE_MCS15, /* 27 */ 609 MPT_RATE_MCS16, 610 MPT_RATE_MCS17, /* #29 */ 611 MPT_RATE_MCS18, 612 MPT_RATE_MCS19, 613 MPT_RATE_MCS20, 614 MPT_RATE_MCS21, 615 MPT_RATE_MCS22, /* #34 */ 616 MPT_RATE_MCS23, 617 MPT_RATE_MCS24, 618 MPT_RATE_MCS25, 619 MPT_RATE_MCS26, 620 MPT_RATE_MCS27, /* #39 */ 621 MPT_RATE_MCS28, /* #40 */ 622 MPT_RATE_MCS29, /* #41 */ 623 MPT_RATE_MCS30, /* #42 */ 624 MPT_RATE_MCS31, /* #43 */ 625 /* VHT rate. Total: 20*/ 626 MPT_RATE_VHT1SS_MCS0 = 100,/* #44*/ 627 MPT_RATE_VHT1SS_MCS1, /* # */ 628 MPT_RATE_VHT1SS_MCS2, 629 MPT_RATE_VHT1SS_MCS3, 630 MPT_RATE_VHT1SS_MCS4, 631 MPT_RATE_VHT1SS_MCS5, 632 MPT_RATE_VHT1SS_MCS6, /* # */ 633 MPT_RATE_VHT1SS_MCS7, 634 MPT_RATE_VHT1SS_MCS8, 635 MPT_RATE_VHT1SS_MCS9, /* #53 */ 636 MPT_RATE_VHT2SS_MCS0, /* #54 */ 637 MPT_RATE_VHT2SS_MCS1, 638 MPT_RATE_VHT2SS_MCS2, 639 MPT_RATE_VHT2SS_MCS3, 640 MPT_RATE_VHT2SS_MCS4, 641 MPT_RATE_VHT2SS_MCS5, 642 MPT_RATE_VHT2SS_MCS6, 643 MPT_RATE_VHT2SS_MCS7, 644 MPT_RATE_VHT2SS_MCS8, 645 MPT_RATE_VHT2SS_MCS9, /* #63 */ 646 MPT_RATE_VHT3SS_MCS0, 647 MPT_RATE_VHT3SS_MCS1, 648 MPT_RATE_VHT3SS_MCS2, 649 MPT_RATE_VHT3SS_MCS3, 650 MPT_RATE_VHT3SS_MCS4, 651 MPT_RATE_VHT3SS_MCS5, 652 MPT_RATE_VHT3SS_MCS6, /* #126 */ 653 MPT_RATE_VHT3SS_MCS7, 654 MPT_RATE_VHT3SS_MCS8, 655 MPT_RATE_VHT3SS_MCS9, 656 MPT_RATE_VHT4SS_MCS0, 657 MPT_RATE_VHT4SS_MCS1, /* #131 */ 658 MPT_RATE_VHT4SS_MCS2, 659 MPT_RATE_VHT4SS_MCS3, 660 MPT_RATE_VHT4SS_MCS4, 661 MPT_RATE_VHT4SS_MCS5, 662 MPT_RATE_VHT4SS_MCS6, /* #136 */ 663 MPT_RATE_VHT4SS_MCS7, 664 MPT_RATE_VHT4SS_MCS8, 665 MPT_RATE_VHT4SS_MCS9, 666 MPT_RATE_LAST 667 } MPT_RATE_E, *PMPT_RATE_E; 668 669 #define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */ 670 671 #define MPT_IS_CCK_RATE(_value) (MPT_RATE_1M <= _value && _value <= MPT_RATE_11M) 672 #define MPT_IS_OFDM_RATE(_value) (MPT_RATE_6M <= _value && _value <= MPT_RATE_54M) 673 #define MPT_IS_HT_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31) 674 #define MPT_IS_HT_1S_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7) 675 #define MPT_IS_HT_2S_RATE(_value) (MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15) 676 #define MPT_IS_HT_3S_RATE(_value) (MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23) 677 #define MPT_IS_HT_4S_RATE(_value) (MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31) 678 679 #define MPT_IS_VHT_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) 680 #define MPT_IS_VHT_1S_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9) 681 #define MPT_IS_VHT_2S_RATE(_value) (MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9) 682 #define MPT_IS_VHT_3S_RATE(_value) (MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9) 683 #define MPT_IS_VHT_4S_RATE(_value) (MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) 684 685 #define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \ 686 (MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9)) 687 #define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \ 688 (MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9)) 689 #define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \ 690 (MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9)) 691 692 typedef enum _POWER_MODE_ { 693 POWER_LOW = 0, 694 POWER_NORMAL 695 } POWER_MODE; 696 697 /* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */ 698 typedef enum _OFDM_TX_MODE { 699 OFDM_ALL_OFF = 0, 700 OFDM_ContinuousTx = 1, 701 OFDM_SingleCarrier = 2, 702 OFDM_SingleTone = 4, 703 } OFDM_TX_MODE; 704 705 706 #define RX_PKT_BROADCAST 1 707 #define RX_PKT_DEST_ADDR 2 708 #define RX_PKT_PHY_MATCH 3 709 710 typedef enum _ENCRY_CTRL_STATE_ { 711 HW_CONTROL, /* hw encryption& decryption */ 712 SW_CONTROL, /* sw encryption& decryption */ 713 HW_ENCRY_SW_DECRY, /* hw encryption & sw decryption */ 714 SW_ENCRY_HW_DECRY /* sw encryption & hw decryption */ 715 } ENCRY_CTRL_STATE; 716 717 typedef enum _MPT_TXPWR_DEF { 718 MPT_CCK, 719 MPT_OFDM, /* L and HT OFDM */ 720 MPT_OFDM_AND_HT, 721 MPT_HT, 722 MPT_VHT 723 } MPT_TXPWR_DEF; 724 725 726 #define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31) 727 #define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9) 728 #define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M) 729 #define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M) 730 731 typedef enum _mp_tx_pkt_payload{ 732 MP_TX_Payload_00 = 0, 733 MP_TX_Payload_a5, 734 MP_TX_Payload_5a, 735 MP_TX_Payload_ff, 736 MP_TX_Payload_prbs9, 737 MP_TX_Payload_default_random 738 } mp_tx_pkt_payload; 739 740 /*************************************************************************/ 741 #if 0 742 extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); 743 extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); 744 #endif 745 enum rtw_mp_tx_method { 746 RTW_MP_SW_TX = 0, 747 RTW_MP_PMACT_TX, 748 RTW_MP_TMACT_TX, 749 RTW_MP_FW_PMACT_TX, 750 }; 751 752 enum rtw_mp_tx_cmd { 753 RTW_MP_TX_NONE = 0, 754 RTW_MP_TX_PACKETS, 755 RTW_MP_TX_CONTINUOUS, 756 RTW_MP_TX_SINGLE_TONE, 757 RTW_MP_TX_CCK_Carrier_Suppression, 758 RTW_MP_TX_CONFIG_PLCP_COMMON_INFO, 759 RTW_MP_TX_CMD_PHY_OK, 760 RTW_MP_TX_CONFIG_PLCP_PATTERN, 761 RTW_MP_TX_CONFIG_PLCP_USER_INFO, 762 RTW_MP_TX_MODE_SWITCH, 763 RTW_MP_TX_F2P, 764 RTW_MP_TX_TB_TEST, 765 RTW_MP_TX_DPD_BYPASS, 766 RTW_MP_TX_CHECK_TX_IDLE, 767 RTW_MP_TX_CMD_MAX, 768 }; 769 770 enum rtw_mp_pmac_mode { 771 RTW_MP_PMAC_NONE_TEST, 772 RTW_MP_PMAC_PKTS_TX, 773 RTW_MP_PMAC_PKTS_RX, 774 RTW_MP_PMAC_CONT_TX, 775 RTW_MP_PMAC_FW_TRIG_TX, 776 RTW_MP_PMAC_OFDM_SINGLE_TONE_TX, 777 RTW_MP_PMAC_CCK_CARRIER_SIPPRESSION_TX 778 }; 779 780 enum rtw_mp_ppdu_type { 781 RTW_MP_TYPE_CCK = 0, 782 RTW_MP_TYPE_LEGACY, 783 RTW_MP_TYPE_HT_MF, 784 RTW_MP_TYPE_HT_GF, 785 RTW_MP_TYPE_VHT, 786 RTW_MP_TYPE_HE_SU, 787 RTW_MP_TYPE_HE_ER_SU, 788 RTW_MP_TYPE_HE_MU_OFDMA, 789 RTW_MP_TYPE_HE_TB 790 }; 791 792 /* mp command class */ 793 enum rtw_mp_class { 794 RTW_MP_CLASS_CONFIG = 0, 795 RTW_MP_CLASS_TX = 1, 796 RTW_MP_CLASS_RX = 2, 797 RTW_MP_CLASS_EFUSE = 3, 798 RTW_MP_CLASS_REG = 4, 799 RTW_MP_CLASS_TXPWR = 5, 800 RTW_MP_CLASS_CAL = 6, 801 RTW_MP_CLASS_FLASH = 7, 802 RTW_MP_CLASS_MAX, 803 }; 804 805 /* mp rx command */ 806 enum rtw_mp_rx_cmd { 807 RTW_MP_RX_CMD_PHY_CRC_OK = 0, 808 RTW_MP_RX_CMD_PHY_CRC_ERR = 1, 809 RTW_MP_RX_CMD_MAC_CRC_OK = 2, 810 RTW_MP_RX_CMD_MAC_CRC_ERR = 3, 811 RTW_MP_RX_CMD_DRV_CRC_OK = 4, 812 RTW_MP_RX_CMD_DRV_CRC_ERR = 5, 813 RTW_MP_RX_CMD_GET_RSSI = 6, 814 RTW_MP_RX_CMD_GET_RXEVM = 7, 815 RTW_MP_RX_CMD_GET_PHYSTS = 8, 816 RTW_MP_RX_CMD_TRIGGER_RXEVM = 9, 817 RTW_MP_RX_CMD_SET_GAIN_OFFSET = 10, 818 RTW_MP_RX_CMD_MAX, 819 820 }; 821 822 /* mp config command */ 823 enum rtw_mp_config_cmdid { 824 RTW_MP_CONFIG_CMD_GET_BW, 825 RTW_MP_CONFIG_CMD_GET_RF_STATUS, 826 RTW_MP_CONFIG_CMD_SET_RATE_IDX, 827 RTW_MP_CONFIG_CMD_SET_RF_TXRX_PATH, 828 RTW_MP_CONFIG_CMD_SET_RESET_PHY_COUNT, 829 RTW_MP_CONFIG_CMD_SET_RESET_MAC_COUNT, 830 RTW_MP_CONFIG_CMD_SET_RESET_DRV_COUNT, 831 RTW_MP_CONFIG_CMD_PBC, 832 RTW_MP_CONFIG_CMD_START_DUT, 833 RTW_MP_CONFIG_CMD_STOP_DUT, 834 RTW_MP_CONFIG_CMD_GET_MIMPO_RSSI, 835 RTW_MP_CONFIG_CMD_GET_BOARD_TYPE, 836 RTW_MP_CONFIG_CMD_GET_MODULATION, 837 RTW_MP_CONFIG_CMD_GET_RF_MODE, 838 RTW_MP_CONFIG_CMD_GET_RF_PATH, 839 RTW_MP_CONFIG_CMD_SET_MODULATION, 840 RTW_MP_CONFIG_CMD_GET_DEVICE_INFO, 841 RTW_MP_CONFIG_CMD_SET_PHY_INDEX, 842 RTW_MP_CONFIG_CMD_GET_MAC_ADDR, 843 RTW_MP_CONFIG_CMD_SET_MAC_ADDR, 844 RTW_MP_CONFIG_CMD_SET_CH_BW, 845 RTW_MP_CONFIG_CMD_GET_TX_NSS, 846 RTW_MP_CONFIG_CMD_GET_RX_NSS, 847 RTW_MP_CONFIG_CMD_SWITCH_BT_PATH, 848 RTW_MP_CONFIG_CMD_GET_RFE_TYPE, 849 RTW_MP_CONFIG_CMD_GET_DEV_IDX, 850 RTW_MP_CONFIG_CMD_TRIGGER_FW_CONFLICT, 851 RTW_MP_CONFIG_CMD_GET_UUID, 852 RTW_MP_CONFIG_CMD_SET_GPIO, 853 RTW_MP_CONFIG_CMD_MAX, 854 }; 855 856 typedef enum _mp_ant_path { 857 MP_ANTENNA_NONE = 0, 858 MP_ANTENNA_D = 1, 859 MP_ANTENNA_C = 2, 860 MP_ANTENNA_CD = 3, 861 MP_ANTENNA_B = 4, 862 MP_ANTENNA_BD = 5, 863 MP_ANTENNA_BC = 6, 864 MP_ANTENNA_BCD = 7, 865 MP_ANTENNA_A = 8, 866 MP_ANTENNA_AD = 9, 867 MP_ANTENNA_AC = 10, 868 MP_ANTENNA_ACD = 11, 869 MP_ANTENNA_AB = 12, 870 MP_ANTENNA_ABD = 13, 871 MP_ANTENNA_ABC = 14, 872 MP_ANTENNA_ABCD = 15 873 } mp_ant_path; 874 875 #define RTW_MP_TEST_NAME_LEN 32 876 #define RTW_MP_TEST_RPT_RSN_LEN 32 877 878 struct rtw_mp_test_rpt { 879 char name[RTW_MP_TEST_NAME_LEN]; 880 u8 status; 881 char rsn[RTW_MP_TEST_RPT_RSN_LEN]; 882 u32 total_time; // in ms 883 }; 884 885 struct rtw_mp_cmd_arg { 886 u8 mp_class; 887 u8 cmd; 888 u8 cmd_ok; 889 }; 890 891 struct rtw_mp_config_arg { 892 u8 mp_class; 893 u8 cmd; 894 u8 cmd_ok; 895 u8 status; 896 u8 channel; 897 u8 bandwidth; 898 u8 rate_idx; 899 u8 ant_tx; 900 u8 ant_rx; 901 u8 rf_path; 902 u8 get_rfstats; 903 u8 modulation; 904 u8 bustype; 905 u32 chipid; 906 u8 cur_phy; 907 u8 mac_addr[6]; 908 u8 sc_idx; 909 u8 dbcc_en; 910 u8 btc_mode; 911 u8 rfe_type; 912 u8 dev_id; 913 u32 offset; 914 u8 voltag; 915 u32 uuid; 916 u8 gpio_id; 917 u8 gpio_enable; 918 }; 919 920 struct rtw_mp_tx_arg { 921 u8 mp_class; 922 u8 cmd; 923 u8 cmd_ok; 924 u8 status; 925 u8 tx_method; 926 u8 plcp_ppdu_type; /*offline gen*/ 927 u16 plcp_case_id; /*offline gen*/ 928 u8 bCarrierSuppression; 929 u8 is_cck; 930 u8 start_tx; 931 u16 tx_cnt; 932 u16 period; /* us */ 933 u16 tx_time; /* us */ 934 u32 tx_ok; 935 u8 tx_path; 936 u8 tx_mode; /* mode: 0 = tmac, 1 = pmac */ 937 u8 tx_concurrent_en; /* concurrent tx */ 938 u8 dpd_bypass; 939 /* plcp info */ 940 u32 dbw; /*0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80*/ 941 u32 source_gen_mode; 942 u32 locked_clk; 943 u32 dyn_bw; 944 u32 ndp_en; 945 u32 long_preamble_en; /*bmode*/ 946 u32 stbc; 947 u32 gi; /*0:0.4,1:0.8,2:1.6,3:3.2*/ 948 u32 tb_l_len; 949 u32 tb_ru_tot_sts_max; 950 u32 vht_txop_not_allowed; 951 u32 tb_disam; 952 u32 doppler; 953 u32 he_ltf_type; /*0:1x,1:2x,2:4x*/ 954 u32 ht_l_len; 955 u32 preamble_puncture; 956 u32 he_mcs_sigb;/*0~5*/ 957 u32 he_dcm_sigb; 958 u32 he_sigb_compress_en; 959 u32 max_tx_time_0p4us; 960 u32 ul_flag; 961 u32 tb_ldpc_extra; 962 u32 bss_color; 963 u32 sr; 964 u32 beamchange_en; 965 u32 he_er_u106ru_en; 966 u32 ul_srp1; 967 u32 ul_srp2; 968 u32 ul_srp3; 969 u32 ul_srp4; 970 u32 mode; 971 u32 group_id; 972 u32 ppdu_type;/*0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB*/ 973 u32 txop; 974 u32 tb_strt_sts; 975 u32 tb_pre_fec_padding_factor; 976 u32 cbw; 977 u32 txsc; 978 u32 tb_mumimo_mode_en; 979 u32 nominal_t_pe; /* def = 2*/ 980 u32 ness; /* def = 0*/ 981 u32 n_user; 982 u32 tb_rsvd;/*def = 0*/ 983 /* plcp user info */ 984 u32 plcp_usr_idx; 985 u32 mcs; 986 u32 mpdu_len; 987 u32 n_mpdu; 988 u32 fec; 989 u32 dcm; 990 u32 aid; 991 u32 scrambler_seed; /* rand (1~255)*/ 992 u32 random_init_seed; /* rand (1~255)*/ 993 u32 apep; 994 u32 ru_alloc; 995 u32 nss; 996 u32 txbf; 997 u32 pwr_boost_db; 998 //struct mp_plcp_param_t plcp_param; /*online gen*/ 999 u32 data_rate; 1000 u8 plcp_sts; 1001 1002 /*HE-TB Test*/ 1003 u8 bSS_id_addr0; 1004 u8 bSS_id_addr1; 1005 u8 bSS_id_addr2; 1006 u8 bSS_id_addr3; 1007 u8 bSS_id_addr4; 1008 u8 bSS_id_addr5; 1009 u8 is_link_mode; 1010 1011 /* f2p cmd */ 1012 u32 pref_AC_0; 1013 u32 aid12_0; 1014 u32 ul_mcs_0; 1015 u32 macid_0; 1016 u32 ru_pos_0; 1017 u32 ul_fec_code_0; 1018 u32 ul_dcm_0; 1019 u32 ss_alloc_0; 1020 u32 ul_tgt_rssi_0; 1021 u32 pref_AC_1; 1022 u32 aid12_1; 1023 u32 ul_mcs_1; 1024 u32 macid_1; 1025 u32 ru_pos_1; 1026 u32 ul_fec_code_1; 1027 u32 ul_dcm_1; 1028 u32 ss_alloc_1; 1029 u32 ul_tgt_rssi_1; 1030 u32 pref_AC_2; 1031 u32 aid12_2; 1032 u32 ul_mcs_2; 1033 u32 macid_2; 1034 u32 ru_pos_2; 1035 u32 ul_fec_code_2; 1036 u32 ul_dcm_2; 1037 u32 ss_alloc_2; 1038 u32 ul_tgt_rssi_2; 1039 u32 pref_AC_3; 1040 u32 aid12_3; 1041 u32 ul_mcs_3; 1042 u32 macid_3; 1043 u32 ru_pos_3; 1044 u32 ul_fec_code_3; 1045 u32 ul_dcm_3; 1046 u32 ss_alloc_3; 1047 u32 ul_tgt_rssi_3; 1048 u32 ul_bw; 1049 u32 gi_ltf; 1050 u32 num_he_ltf; 1051 u32 ul_stbc; 1052 u32 pkt_doppler; 1053 u32 ap_tx_power; 1054 u32 user_num; 1055 u32 pktnum; 1056 u32 pri20_bitmap; 1057 u32 datarate; 1058 u32 mulport_id; 1059 u32 pwr_ofset; 1060 u32 f2p_mode; 1061 u32 frexch_type; 1062 u32 sigb_len; 1063 /* dword 0 */ 1064 u32 cmd_qsel; 1065 u32 ls; 1066 u32 fs; 1067 u32 total_number; 1068 u32 seq; 1069 u32 length; 1070 /* dword 1 */ 1071 /* dword 0 */ 1072 u32 cmd_type; 1073 u32 cmd_sub_type; 1074 u32 dl_user_num; 1075 u32 bw; 1076 u32 tx_power; 1077 /* dword 1 */ 1078 u32 fw_define; 1079 u32 ss_sel_mode; 1080 u32 next_qsel; 1081 u32 twt_group; 1082 u32 dis_chk_slp; 1083 u32 ru_mu_2_su; 1084 u32 dl_t_pe; 1085 /* dword 2 */ 1086 u32 sigb_ch1_len; 1087 u32 sigb_ch2_len; 1088 u32 sigb_sym_num; 1089 u32 sigb_ch2_ofs; 1090 u32 dis_htp_ack; 1091 u32 tx_time_ref; 1092 u32 pri_user_idx; 1093 /* dword 3 */ 1094 u32 ampdu_max_txtime; 1095 u32 d3_group_id; 1096 u32 twt_chk_en; 1097 u32 twt_port_id; 1098 /* dword 4 */ 1099 u32 twt_start_time; 1100 /* dword 5 */ 1101 u32 twt_end_time; 1102 /* dword 6 */ 1103 u32 apep_len; 1104 u32 tri_pad; 1105 u32 ul_t_pe; 1106 u32 rf_gain_idx; 1107 u32 fixed_gain_en; 1108 u32 ul_gi_ltf; 1109 u32 ul_doppler; 1110 u32 d6_ul_stbc; 1111 /* dword 7 */ 1112 u32 ul_mid_per; 1113 u32 ul_cqi_rrp_tri; 1114 u32 sigb_dcm; 1115 u32 sigb_comp; 1116 u32 d7_doppler; 1117 u32 d7_stbc; 1118 u32 mid_per; 1119 u32 gi_ltf_size; 1120 u32 sigb_mcs; 1121 /* dword 8 */ 1122 u32 macid_u0; 1123 u32 ac_type_u0; 1124 u32 mu_sta_pos_u0; 1125 u32 dl_rate_idx_u0; 1126 u32 dl_dcm_en_u0; 1127 u32 ru_alo_idx_u0; 1128 /* dword 9 */ 1129 u32 pwr_boost_u0; 1130 u32 agg_bmp_alo_u0; 1131 u32 ampdu_max_txnum_u0; 1132 u32 user_define_u0; 1133 u32 user_define_ext_u0; 1134 /* dword 10 */ 1135 u32 ul_addr_idx_u0; 1136 u32 ul_dcm_u0; 1137 u32 ul_fec_cod_u0; 1138 u32 ul_ru_rate_u0; 1139 u32 ul_ru_alo_idx_u0; 1140 /* dword 11 */ 1141 /* dword 12 */ 1142 u32 macid_u1; 1143 u32 ac_type_u1; 1144 u32 mu_sta_pos_u1; 1145 u32 dl_rate_idx_u1; 1146 u32 dl_dcm_en_u1; 1147 u32 ru_alo_idx_u1; 1148 /* dword 13 */ 1149 u32 pwr_boost_u1; 1150 u32 agg_bmp_alo_u1; 1151 u32 ampdu_max_txnum_u1; 1152 u32 user_define_u1; 1153 u32 user_define_ext_u1; 1154 /* dword 14 */ 1155 u32 ul_addr_idx_u1; 1156 u32 ul_dcm_u1; 1157 u32 ul_fec_cod_u1; 1158 u32 ul_ru_rate_u1; 1159 u32 ul_ru_alo_idx_u1; 1160 /* dword 15 */ 1161 /* dword 16 */ 1162 u32 macid_u2; 1163 u32 ac_type_u2; 1164 u32 mu_sta_pos_u2; 1165 u32 dl_rate_idx_u2; 1166 u32 dl_dcm_en_u2; 1167 u32 ru_alo_idx_u2; 1168 /* dword 17 */ 1169 u32 pwr_boost_u2; 1170 u32 agg_bmp_alo_u2; 1171 u32 ampdu_max_txnum_u2; 1172 u32 user_define_u2; 1173 u32 user_define_ext_u2; 1174 /* dword 18 */ 1175 u32 ul_addr_idx_u2; 1176 u32 ul_dcm_u2; 1177 u32 ul_fec_cod_u2; 1178 u32 ul_ru_rate_u2; 1179 u32 ul_ru_alo_idx_u2; 1180 /* dword 19 */ 1181 /* dword 20 */ 1182 u32 macid_u3; 1183 u32 ac_type_u3; 1184 u32 mu_sta_pos_u3; 1185 u32 dl_rate_idx_u3; 1186 u32 dl_dcm_en_u3; 1187 u32 ru_alo_idx_u3; 1188 /* dword 21 */ 1189 u32 pwr_boost_u3; 1190 u32 agg_bmp_alo_u3; 1191 u32 ampdu_max_txnum_u3; 1192 u32 user_define_u3; 1193 u32 user_define_ext_u3; 1194 /* dword 22 */ 1195 u32 ul_addr_idx_u3; 1196 u32 ul_dcm_u3; 1197 u32 ul_fec_cod_u3; 1198 u32 ul_ru_rate_u3; 1199 u32 ul_ru_alo_idx_u3; 1200 /* dword 23 */ 1201 /* dword 24 */ 1202 u32 pkt_id_0; 1203 u32 valid_0; 1204 u32 ul_user_num_0; 1205 /* dword 25 */ 1206 u32 pkt_id_1; 1207 u32 valid_1; 1208 u32 ul_user_num_1; 1209 /* dword 26 */ 1210 u32 pkt_id_2; 1211 u32 valid_2; 1212 u32 ul_user_num_2; 1213 /* dword 27 */ 1214 u32 pkt_id_3; 1215 u32 valid_3; 1216 u32 ul_user_num_3; 1217 /* dword 28 */ 1218 u32 pkt_id_4; 1219 u32 valid_4; 1220 u32 ul_user_num_4; 1221 /* dword 29 */ 1222 u32 pkt_id_5; 1223 u32 valid_5; 1224 u32 ul_user_num_5; 1225 /* tx state*/ 1226 u8 tx_state; 1227 }; 1228 1229 1230 struct rtw_mp_rx_arg { 1231 u8 mp_class; 1232 u8 cmd; 1233 u8 cmd_ok; 1234 u8 status; 1235 u32 rx_ok; 1236 u32 rx_err; 1237 u8 rssi; 1238 u8 rx_path; 1239 u8 rx_evm; 1240 u8 user; 1241 u8 strm; 1242 u8 rxevm_table; 1243 u8 enable; 1244 u32 phy0_user0_rxevm; 1245 u32 phy0_user1_rxevm; 1246 u32 phy0_user2_rxevm; 1247 u32 phy0_user3_rxevm; 1248 u32 phy1_user0_rxevm; 1249 u32 phy1_user1_rxevm; 1250 u32 phy1_user2_rxevm; 1251 u32 phy1_user3_rxevm; 1252 s8 offset; 1253 u8 rf_path; 1254 u8 iscck; 1255 s16 rssi_ex; 1256 }; 1257 1258 /* mp tx power command */ 1259 enum rtw_mp_txpwr_cmd { 1260 RTW_MP_TXPWR_CMD_READ_PWR_TABLE = 0, 1261 RTW_MP_TXPWR_CMD_GET_PWR_TRACK_STATUS = 1, 1262 RTW_MP_TXPWR_CMD_SET_PWR_TRACK_STATUS = 2, 1263 RTW_MP_TXPWR_CMD_SET_TXPWR = 3, 1264 RTW_MP_TXPWR_CMD_GET_TXPWR = 4, 1265 RTW_MP_TXPWR_CMD_GET_TXPWR_INDEX = 5, 1266 RTW_MP_TXPWR_CMD_GET_THERMAL = 6, 1267 RTW_MP_TXPWR_CMD_GET_TSSI = 7, 1268 RTW_MP_TXPWR_CMD_SET_TSSI = 8, 1269 RTW_MP_TXPWR_CMD_GET_TXPWR_REF = 9, 1270 RTW_MP_TXPWR_CMD_GET_TXPWR_REF_CW = 10, 1271 RTW_MP_TXPWR_CMD_SET_TXPWR_INDEX = 11, 1272 RTW_MP_TXPWR_CMD_GET_TXINFOPWR = 12, 1273 RTW_MP_TXPWR_CMD_SET_RFMODE = 13, 1274 RTW_MP_TXPWR_CMD_SET_TSSI_OFFSET = 14, 1275 RTW_MP_TXPWR_CMD_GET_ONLINE_TSSI_DE = 15, 1276 RTW_MP_TXPWR_CMD_SET_PWR_LMT_EN = 16, 1277 RTW_MP_TXPWR_CMD_GET_PWR_LMT_EN = 17, 1278 RTW_MP_TXPWR_CMD_SET_TX_POW_PATTERN_SHARP = 18, 1279 RTW_MP_TXPWR_CMD_SET_TX_POW_TABLE_SWITCH = 19, 1280 RTW_MP_TXPWR_CMD_MAX, 1281 }; 1282 1283 enum rtw_mp_tssi_pwrtrk_type{ 1284 RTW_MP_TSSI_OFF = 0, 1285 RTW_MP_TSSI_ON, 1286 RTW_MP_TSSI_CAL 1287 }; 1288 1289 struct rtw_mp_txpwr_arg { 1290 u8 mp_class; 1291 u8 cmd; 1292 u8 cmd_ok; 1293 u8 status; 1294 s16 txpwr; 1295 u16 txpwr_index; 1296 u8 txpwr_track_status; 1297 u8 txpwr_status; 1298 u32 tssi; 1299 u8 thermal; 1300 u8 rfpath; 1301 u8 ofdm; 1302 u8 tx_path; 1303 u16 rate; 1304 u8 bandwidth; 1305 u8 channel; 1306 s16 table_item; /*get an element of power table*/ 1307 u8 dcm; 1308 u8 beamforming; 1309 u8 offset; 1310 s16 txpwr_ref; 1311 u8 is_cck; 1312 u8 rf_mode; 1313 u32 tssi_de_offset; 1314 s32 dbm; 1315 s32 pout; 1316 s32 online_tssi_de; 1317 bool pwr_lmt_en; 1318 u8 sharp_id; 1319 }; 1320 1321 /* mp reg command */ 1322 enum rtw_mp_reg_cmd { 1323 RTW_MP_REG_CMD_READ_MAC = 0, 1324 RTW_MP_REG_CMD_WRITE_MAC = 1, 1325 RTW_MP_REG_CMD_READ_RF = 2, 1326 RTW_MP_REG_CMD_WRITE_RF = 3, 1327 RTW_MP_REG_CMD_READ_SYN = 4, 1328 RTW_MP_REG_CMD_WRITE_SYN = 5, 1329 RTW_MP_REG_CMD_READ_BB = 6, 1330 RTW_MP_REG_CMD_WRITE_BB = 7, 1331 RTW_MP_REG_CMD_SET_XCAP = 8, 1332 RTW_MP_REG_CMD_GET_XCAP = 9, 1333 RTW_MP_REG_CMD_MAX, 1334 }; 1335 1336 struct rtw_mp_reg_arg { 1337 u8 mp_class; 1338 u8 cmd; 1339 u8 cmd_ok; 1340 u8 status; 1341 u32 io_offset; 1342 u32 io_value; 1343 u8 io_type; 1344 u8 ofdm; 1345 u8 rfpath; 1346 u8 sc_xo; 1347 u8 xsi_offset; 1348 u8 xsi_value; 1349 }; 1350 1351 struct rtw_mp_cal_arg { 1352 u8 mp_class; 1353 u8 cmd; 1354 u8 cmd_ok; 1355 u8 status; 1356 u8 cal_type; 1357 u8 enable; 1358 u8 rfpath; 1359 u16 io_value; 1360 u8 channel; 1361 u8 bandwidth; 1362 s32 xdbm; 1363 u8 path; 1364 u8 iq_path; 1365 u32 avg; 1366 u32 fft; 1367 s32 point; 1368 u32 upoint; 1369 u32 start_point; 1370 u32 stop_point; 1371 u32 buf; 1372 u32 outbuf[450]; 1373 }; 1374 1375 enum rtw_mp_cal_cmd { 1376 RTW_MP_CAL_CMD_TRIGGER_CAL = 0, 1377 RTW_MP_CAL_CMD_SET_CAPABILITY_CAL = 1, 1378 RTW_MP_CAL_CMD_GET_CAPABILITY_CAL = 2, 1379 RTW_MP_CAL_CMD_GET_TSSI_DE_VALUE = 3, 1380 RTW_MP_CAL_CMD_SET_TSSI_DE_TX_VERIFY = 4, 1381 RTW_MP_CAL_CMD_GET_TXPWR_FINAL_ABS = 5, 1382 RTW_MP_CAL_CMD_TRIGGER_DPK_TRACKING = 6, 1383 RTW_MP_CAL_CMD_SET_TSSI_AVG = 7, 1384 RTW_MP_CAL_CMD_PSD_INIT = 8, 1385 RTW_MP_CAL_CMD_PSD_RESTORE = 9, 1386 RTW_MP_CAL_CMD_PSD_GET_POINT_DATA = 10, 1387 RTW_MP_CAL_CMD_PSD_QUERY = 11, 1388 RTW_MP_CAL_CMD_MAX, 1389 }; 1390 1391 enum rtw_mp_calibration_type { 1392 RTW_MP_CAL_CHL_RFK = 0, 1393 RTW_MP_CAL_DACK = 1, 1394 RTW_MP_CAL_IQK = 2, 1395 RTW_MP_CAL_LCK = 3, 1396 RTW_MP_CAL_DPK = 4, 1397 RTW_MP_CAL_DPK_TRACK = 5, 1398 RTW_MP_CAL_TSSI = 6, 1399 RTW_MP_CAL_GAPK = 7, 1400 RTW_MP_CAL_MAX, 1401 }; 1402 1403 enum RTW_TEST_SUB_MODULE { 1404 RTW_TEST_SUB_MODULE_MP = 0, 1405 RTW_TEST_SUB_MODULE_FPGA = 1, 1406 RTW_TEST_SUB_MODULE_VERIFY = 2, 1407 RTW_TEST_SUB_MODULE_TOOL = 3, 1408 RTW_TEST_SUB_MODULE_TRX = 4, 1409 RTW_TEST_SUB_MODULE_UNKNOWN, 1410 }; 1411 1412 struct rtw_test_module_info { 1413 u8 tm_type; 1414 u8 tm_mode; 1415 }; 1416 1417 #define RTW_MAX_TEST_CMD_BUF 2000 1418 struct rtw_mp_test_cmdbuf { 1419 u8 type; 1420 u8 buf[RTW_MAX_TEST_CMD_BUF]; 1421 u16 len; 1422 }; 1423 1424 enum rtw_mp_nss 1425 { 1426 MP_NSS1, 1427 MP_NSS2, 1428 MP_NSS3, 1429 MP_NSS4 1430 }; 1431 1432 #define RU_TONE_STR(idx)\ 1433 (idx == MP_RU_TONE_26) ? "26-Tone" :\ 1434 (idx == MP_RU_TONE_52) ? "52-Tone" :\ 1435 (idx == MP_RU_TONE_106) ? "106-Tone" :\ 1436 (idx == MP_RU_TONE_242) ? "242-Tone" :\ 1437 (idx == MP_RU_TONE_484) ? "484-Tone" :\ 1438 (idx == MP_RU_TONE_966) ? "966-Tone" :\ 1439 "UNknow" 1440 1441 enum rtw_mp_resourceUnit 1442 { 1443 MP_RU_TONE_26 = 0, 1444 MP_RU_TONE_52, 1445 MP_RU_TONE_106, 1446 MP_RU_TONE_242, 1447 MP_RU_TONE_484, 1448 MP_RU_TONE_966 1449 }; 1450 1451 #define MP_IS_HT_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS31) 1452 #define MP_IS_VHT_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9) 1453 #define MP_IS_CCK_HRATE(_rate) ((_rate) == HRATE_CCK1 || (_rate) == HRATE_CCK2 || \ 1454 (_rate) == HRATE_CCK5_5 || (_rate) == HRATE_CCK11) 1455 1456 #define MP_IS_OFDM_HRATE(_rate) ((_rate) >= HRATE_OFDM6 && (_rate) <= HRATE_OFDM54) 1457 #define MP_IS_HE_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11) 1458 1459 #define MP_IS_HT1SS_HRATE(_rate) ((_rate) >= HRATE_MCS0 && (_rate) <= HRATE_MCS7) 1460 #define MP_IS_HT2SS_HRATE(_rate) ((_rate) >= HRATE_MCS8 && (_rate) <= HRATE_MCS15) 1461 #define MP_IS_HT3SS_HRATE(_rate) ((_rate) >= HRATE_MCS16 && (_rate) <= HRATE_MCS23) 1462 #define MP_IS_HT4SS_HRATE(_rate) ((_rate) >= HRATE_MCS24 && (_rate) <= HRATE_MCS31) 1463 1464 #define MP_IS_VHT1SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS1_MCS0 && (_rate) <= HRATE_VHT_NSS1_MCS9) 1465 #define MP_IS_VHT2SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS2_MCS0 && (_rate) <= HRATE_VHT_NSS2_MCS9) 1466 #define MP_IS_VHT3SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS3_MCS0 && (_rate) <= HRATE_VHT_NSS3_MCS9) 1467 #define MP_IS_VHT4SS_HRATE(_rate) ((_rate) >= HRATE_VHT_NSS4_MCS0 && (_rate) <= HRATE_VHT_NSS4_MCS9) 1468 1469 #define MP_IS_HE1SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS1_MCS0 && (_rate) <= HRATE_HE_NSS1_MCS11) 1470 #define MP_IS_HE2SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS2_MCS0 && (_rate) <= HRATE_HE_NSS2_MCS11) 1471 #define MP_IS_HE3SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS3_MCS0 && (_rate) <= HRATE_HE_NSS3_MCS11) 1472 #define MP_IS_HE4SS_HRATE(_rate) ((_rate) >= HRATE_HE_NSS4_MCS0 && (_rate) <= HRATE_HE_NSS4_MCS11) 1473 1474 #define MP_IS_1T_HRATE(_rate) (MP_IS_CCK_HRATE((_rate)) || MP_IS_OFDM_HRATE((_rate)) \ 1475 || MP_IS_HT1SS_HRATE((_rate)) || MP_IS_VHT1SS_HRATE((_rate)) \ 1476 || MP_IS_HE1SS_HRATE((_rate))) 1477 1478 #define MP_IS_2T_HRATE(_rate) (MP_IS_HT2SS_HRATE((_rate)) || MP_IS_VHT2SS_HRATE((_rate)) \ 1479 || MP_IS_HE2SS_HRATE((_rate))) 1480 1481 #define MP_IS_3T_HRATE(_rate) (MP_IS_HT3SS_HRATE((_rate)) || MP_IS_VHT3SS_HRATE((_rate)) \ 1482 || MP_IS_HE3SS_HRATE((_rate))) 1483 1484 #define MP_IS_4T_HRATE(_rate) (MP_IS_HT4SS_HRATE((_rate)) || MP_IS_VHT4SS_HRATE((_rate)) \ 1485 || MP_IS_HE4SS_HRATE((_rate))) 1486 1487 1488 1489 void rtw_mp_get_phl_cmd(_adapter *padapter, void* buf, u32 buflen); 1490 void rtw_mp_set_phl_cmd(_adapter *padapter, void* buf, u32 buflen); 1491 1492 bool rtw_mp_phl_config_arg(_adapter *padapter, enum rtw_mp_config_cmdid cmdid); 1493 void rtw_mp_phl_rx_physts(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, bool bstart); 1494 void rtw_mp_phl_rx_rssi(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg); 1495 void rtw_mp_phl_rx_gain_offset(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg, u8 path_num); 1496 void rtw_mp_phl_query_rx(_adapter *padapter, struct rtw_mp_rx_arg *rx_arg ,u8 rx_qurey_type); 1497 u8 rtw_mp_phl_txpower(_adapter *padapter, struct rtw_mp_txpwr_arg *ptxpwr_arg, u8 cmdid); 1498 void rtw_mp_set_crystal_cap(_adapter *padapter, u32 xcapvalue); 1499 u8 rtw_mp_phl_calibration(_adapter *padapter, struct rtw_mp_cal_arg *pcal_arg, u8 cmdid); 1500 u8 rtw_mp_phl_reg(_adapter *padapter, struct rtw_mp_reg_arg *reg_arg, u8 cmdid); 1501 1502 1503 u8 rtw_update_giltf(_adapter *padapter); 1504 void rtw_mp_update_coding(_adapter *padapter); 1505 u8 rtw_mp_update_ru_tone(_adapter *padapter); 1506 u8 rtw_mp_update_ru_alloc(_adapter *padapter); 1507 1508 bool rtw_mp_is_cck_rate(u16 rate); 1509 1510 extern s32 init_mp_priv(_adapter *padapter); 1511 extern void free_mp_priv(struct mp_priv *pmp_priv); 1512 extern s32 MPT_InitializeAdapter(_adapter *padapter, u8 Channel); 1513 extern void MPT_DeInitAdapter(_adapter *padapter); 1514 extern s32 mp_start_test(_adapter *padapter); 1515 extern void mp_stop_test(_adapter *padapter); 1516 1517 1518 extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); 1519 extern u32 read_rfreg(_adapter *padapter, u8 rfpath, u32 addr); 1520 extern void write_rfreg(_adapter *padapter, u8 rfpath, u32 addr, u32 val); 1521 #ifdef CONFIG_ANTENNA_DIVERSITY 1522 u8 rtw_mp_set_antdiv(_adapter *padapter, BOOLEAN bMain); 1523 #endif 1524 void SetChannel(_adapter *adapter); 1525 void SetBandwidth(_adapter *adapter); 1526 int rtw_mp_txpoweridx(_adapter *adapter); 1527 u16 rtw_mp_txpower_dbm(_adapter *adapter, u8 rf_path); 1528 u16 rtw_mp_get_pwrtab_dbm(_adapter *adapter, u8 rfpath); 1529 1530 void SetAntenna(_adapter *adapter); 1531 void SetDataRate(_adapter *adapter); 1532 s32 SetThermalMeter(_adapter *adapter, u8 target_ther); 1533 void GetThermalMeter(_adapter *adapter, u8 rfpath ,u8 *value); 1534 void GetUuid(_adapter *adapter, u32 *uuid); 1535 void SetGpio(_adapter *padapter); 1536 void rtw_mp_continuous_tx(_adapter *adapter, u8 bstart); 1537 void rtw_mp_singlecarrier_tx(_adapter *adapter, u8 bstart); 1538 void rtw_mp_singletone_tx(_adapter *adapter, u8 bstart); 1539 void rtw_mp_carriersuppr_tx(_adapter *adapter, u8 bstart); 1540 void rtw_mp_txpwr_level(_adapter *adapter); 1541 void fill_txdesc_for_mp(_adapter *padapter, u8 *ptxdesc); 1542 void rtw_set_phl_packet_tx(_adapter *padapter, u8 bStart); 1543 u8 rtw_phl_mp_tx_cmd(_adapter *padapter, enum rtw_mp_tx_cmd cmdid, 1544 enum rtw_mp_tx_method tx_method, boolean bstart); 1545 1546 void rtw_mp_set_packet_tx(_adapter *padapter); 1547 void rtw_mp_reset_phy_count(_adapter *adapter); 1548 1549 s32 SetPowerTracking(_adapter *padapter, u8 enable); 1550 void GetPowerTracking(_adapter *padapter, u8 *enable); 1551 u32 mp_query_psd(_adapter *adapter, u8 *data); 1552 void rtw_mp_trigger_iqk(_adapter *padapter); 1553 void rtw_mp_trigger_lck(_adapter *padapter); 1554 void rtw_mp_trigger_dpk(_adapter *padapter); 1555 u8 rtw_mp_mode_check(_adapter *padapter); 1556 bool rtw_is_mp_tssitrk_on(_adapter *adapter); 1557 1558 void mpt_ProSetPMacTx(_adapter *adapter); 1559 void MP_PHY_SetRFPathSwitch(_adapter *adapter , BOOLEAN bMain); 1560 void mp_phy_switch_rf_path_set(_adapter *adapter , u8 *pstate); 1561 u8 MP_PHY_QueryRFPathSwitch(_adapter *adapter); 1562 u32 mpt_ProQueryCalTxPower(_adapter *adapter, u8 RfPath); 1563 u8 mpt_to_mgnt_rate(u32 MptRateIdx); 1564 u16 rtw_mp_rate_parse(_adapter *adapter, u8 *target_str); 1565 u32 mp_join(_adapter *padapter, u8 mode); 1566 u32 hal_mpt_query_phytxok(_adapter *adapter); 1567 u32 mpt_get_tx_power_finalabs_val(_adapter *padapter, u8 rf_path); 1568 void mpt_trigger_tssi_tracking(_adapter *adapter, u8 rf_path); 1569 u8 rtw_mpt_set_power_limit_en(_adapter *padapter, bool en_val); 1570 bool rtw_mpt_get_power_limit_en(_adapter *padapter); 1571 1572 u32 rtw_mp_get_tssi_de(_adapter *padapter, u8 rf_path); 1573 s32 rtw_mp_get_online_tssi_de(_adapter *padapter, s32 out_pwr, s32 tgdbm, u8 rf_path); 1574 u8 rtw_mp_set_tsside2verify(_adapter *padapter, u32 tssi_de, u8 rf_path); 1575 u8 rtw_mp_set_tssi_offset(_adapter *padapter, u32 tssi_offset, u8 rf_path); 1576 u8 rtw_mp_set_tssi_pwrtrk(_adapter *padapter, u8 tssi_state); 1577 u8 rtw_mp_get_tssi_pwrtrk(_adapter *padapter); 1578 u8 rtw_mp_set_tx_shape_idx(_adapter *padapter); 1579 1580 void rtw_mp_cal_trigger(_adapter *padapter, u8 cal_tye); 1581 void rtw_mp_cal_capab(_adapter *padapter, u8 cal_tye, u8 benable); 1582 1583 void 1584 PMAC_Get_Pkt_Param( 1585 PRT_PMAC_TX_INFO pPMacTxInfo, 1586 PRT_PMAC_PKT_INFO pPMacPktInfo 1587 ); 1588 void 1589 CCK_generator( 1590 PRT_PMAC_TX_INFO pPMacTxInfo, 1591 PRT_PMAC_PKT_INFO pPMacPktInfo 1592 ); 1593 void 1594 PMAC_Nsym_generator( 1595 PRT_PMAC_TX_INFO pPMacTxInfo, 1596 PRT_PMAC_PKT_INFO pPMacPktInfo 1597 ); 1598 void 1599 L_SIG_generator( 1600 u32 N_SYM, /* Max: 750*/ 1601 PRT_PMAC_TX_INFO pPMacTxInfo, 1602 PRT_PMAC_PKT_INFO pPMacPktInfo 1603 ); 1604 1605 void HT_SIG_generator( 1606 PRT_PMAC_TX_INFO pPMacTxInfo, 1607 PRT_PMAC_PKT_INFO pPMacPktInfo); 1608 1609 void VHT_SIG_A_generator( 1610 PRT_PMAC_TX_INFO pPMacTxInfo, 1611 PRT_PMAC_PKT_INFO pPMacPktInfo); 1612 1613 void VHT_SIG_B_generator( 1614 PRT_PMAC_TX_INFO pPMacTxInfo); 1615 1616 void VHT_Delimiter_generator( 1617 PRT_PMAC_TX_INFO pPMacTxInfo); 1618 1619 1620 int rtw_mp_write_reg(struct net_device *dev, 1621 struct iw_request_info *info, 1622 struct iw_point *wrqu, char *extra); 1623 int rtw_mp_read_reg(struct net_device *dev, 1624 struct iw_request_info *info, 1625 struct iw_point *wrqu, char *extra); 1626 int rtw_mp_write_rf(struct net_device *dev, 1627 struct iw_request_info *info, 1628 struct iw_point *wrqu, char *extra); 1629 int rtw_mp_read_rf(struct net_device *dev, 1630 struct iw_request_info *info, 1631 struct iw_point *wrqu, char *extra); 1632 int rtw_mp_start(struct net_device *dev, 1633 struct iw_request_info *info, 1634 struct iw_point *wrqu, char *extra); 1635 int rtw_mp_stop(struct net_device *dev, 1636 struct iw_request_info *info, 1637 struct iw_point *wrqu, char *extra); 1638 int rtw_mp_rate(struct net_device *dev, 1639 struct iw_request_info *info, 1640 struct iw_point *wrqu, char *extra); 1641 int rtw_mp_channel(struct net_device *dev, 1642 struct iw_request_info *info, 1643 struct iw_point *wrqu, char *extra); 1644 int rtw_mp_trxsc_offset(struct net_device *dev, 1645 struct iw_request_info *info, 1646 struct iw_point *wrqu, char *extra); 1647 int rtw_mp_bandwidth(struct net_device *dev, 1648 struct iw_request_info *info, 1649 struct iw_point *wrqu, char *extra); 1650 int rtw_mp_txpower_index(struct net_device *dev, 1651 struct iw_request_info *info, 1652 struct iw_point *wrqu, char *extra); 1653 int rtw_mp_txpower(struct net_device *dev, 1654 struct iw_request_info *info, 1655 struct iw_point *wrqu, char *extra); 1656 int rtw_mp_ant_tx(struct net_device *dev, 1657 struct iw_request_info *info, 1658 struct iw_point *wrqu, char *extra); 1659 int rtw_mp_ant_rx(struct net_device *dev, 1660 struct iw_request_info *info, 1661 struct iw_point *wrqu, char *extra); 1662 int rtw_set_ctx_destAddr(struct net_device *dev, 1663 struct iw_request_info *info, 1664 struct iw_point *wrqu, char *extra); 1665 int rtw_mp_ctx(struct net_device *dev, 1666 struct iw_request_info *info, 1667 struct iw_point *wrqu, char *extra); 1668 int rtw_mp_disable_bt_coexist(struct net_device *dev, 1669 struct iw_request_info *info, 1670 union iwreq_data *wrqu, char *extra); 1671 int rtw_mp_disable_bt_coexist(struct net_device *dev, 1672 struct iw_request_info *info, 1673 union iwreq_data *wrqu, char *extra); 1674 int rtw_mp_arx(struct net_device *dev, 1675 struct iw_request_info *info, 1676 struct iw_point *wrqu, char *extra); 1677 int rtw_mp_trx_query(struct net_device *dev, 1678 struct iw_request_info *info, 1679 struct iw_point *wrqu, char *extra); 1680 int rtw_mp_pwrtrk(struct net_device *dev, 1681 struct iw_request_info *info, 1682 struct iw_point *wrqu, char *extra); 1683 int rtw_mp_psd(struct net_device *dev, 1684 struct iw_request_info *info, 1685 struct iw_point *wrqu, char *extra); 1686 int rtw_mp_thermal(struct net_device *dev, 1687 struct iw_request_info *info, 1688 struct iw_point *wrqu, char *extra); 1689 int rtw_mp_UUID(struct net_device *dev, 1690 struct iw_request_info *info, 1691 struct iw_point *wrqu, char *extra); 1692 int rtw_mp_reset_stats(struct net_device *dev, 1693 struct iw_request_info *info, 1694 struct iw_point *wrqu, char *extra); 1695 int rtw_mp_dump(struct net_device *dev, 1696 struct iw_request_info *info, 1697 struct iw_point *wrqu, char *extra); 1698 int rtw_mp_phypara(struct net_device *dev, 1699 struct iw_request_info *info, 1700 struct iw_point *wrqu, char *extra); 1701 int rtw_mp_SetRFPath(struct net_device *dev, 1702 struct iw_request_info *info, 1703 struct iw_point *wrqu, char *extra); 1704 int rtw_mp_switch_rf_path(struct net_device *dev, 1705 struct iw_request_info *info, 1706 struct iw_point *wrqu, char *extra); 1707 int rtw_mp_link(struct net_device *dev, 1708 struct iw_request_info *info, 1709 struct iw_point *wrqu, char *extra); 1710 int rtw_mp_QueryDrv(struct net_device *dev, 1711 struct iw_request_info *info, 1712 union iwreq_data *wrqu, char *extra); 1713 int rtw_mp_PwrCtlDM(struct net_device *dev, 1714 struct iw_request_info *info, 1715 struct iw_point *wrqu, char *extra); 1716 int rtw_mp_getver(struct net_device *dev, 1717 struct iw_request_info *info, 1718 union iwreq_data *wrqu, char *extra); 1719 int rtw_mp_mon(struct net_device *dev, 1720 struct iw_request_info *info, 1721 union iwreq_data *wrqu, char *extra); 1722 int rtw_mp_pwrlmt(struct net_device *dev, 1723 struct iw_request_info *info, 1724 union iwreq_data *wrqu, char *extra); 1725 int rtw_mp_dpk_track(struct net_device *dev, 1726 struct iw_request_info *info, 1727 union iwreq_data *wrqu, char *extra); 1728 int rtw_mp_dpk(struct net_device *dev, 1729 struct iw_request_info *info, 1730 union iwreq_data *wrqu, char *extra); 1731 #if 0 1732 int rtw_efuse_mask_file(struct net_device *dev, 1733 struct iw_request_info *info, 1734 union iwreq_data *wrqu, char *extra); 1735 int rtw_bt_efuse_mask_file(struct net_device *dev, 1736 struct iw_request_info *info, 1737 union iwreq_data *wrqu, char *extra); 1738 1739 int rtw_efuse_file_map(struct net_device *dev, 1740 struct iw_request_info *info, 1741 union iwreq_data *wrqu, char *extra); 1742 int rtw_efuse_file_map_store(struct net_device *dev, 1743 struct iw_request_info *info, 1744 union iwreq_data *wrqu, char *extra); 1745 int rtw_bt_efuse_file_map(struct net_device *dev, 1746 struct iw_request_info *info, 1747 union iwreq_data *wrqu, char *extra); 1748 #endif 1749 1750 int rtw_mp_SetBT(struct net_device *dev, 1751 struct iw_request_info *info, 1752 union iwreq_data *wrqu, char *extra); 1753 int rtw_mp_pretx_proc(_adapter *padapter, u8 bStartTest, char *extra); 1754 int rtw_mp_tx(struct net_device *dev, 1755 struct iw_request_info *info, 1756 union iwreq_data *wrqu, char *extra); 1757 int rtw_mp_rx(struct net_device *dev, 1758 struct iw_request_info *info, 1759 union iwreq_data *wrqu, char *extra); 1760 int rtw_mp_hwtx(struct net_device *dev, 1761 struct iw_request_info *info, 1762 union iwreq_data *wrqu, char *extra); 1763 u8 rtw_mp_hwrate2mptrate(u8 rate); 1764 int rtw_mp_iqk(struct net_device *dev, 1765 struct iw_request_info *info, 1766 struct iw_point *wrqu, char *extra); 1767 int rtw_mp_lck(struct net_device *dev, 1768 struct iw_request_info *info, 1769 struct iw_point *wrqu, char *extra); 1770 int rtw_mp_get_tsside(struct net_device *dev, 1771 struct iw_request_info *info, 1772 struct iw_point *wrqu, char *extra); 1773 int rtw_mp_set_tsside(struct net_device *dev, 1774 struct iw_request_info *info, 1775 struct iw_point *wrqu, char *extra); 1776 1777 int rtw_priv_mp_set(struct net_device *dev, 1778 struct iw_request_info *info, 1779 union iwreq_data *wdata, char *extra); 1780 1781 int rtw_priv_mp_get(struct net_device *dev, 1782 struct iw_request_info *info, 1783 union iwreq_data *wdata, char *extra); 1784 1785 int rtw_mp_set_phl_io(struct net_device *dev, 1786 struct iw_request_info *info, 1787 struct iw_point *wrqu, char *extra); 1788 1789 int rtw_mp_get_phl_io(struct net_device *dev, 1790 struct iw_request_info *info, 1791 struct iw_point *wrqu, char *extra); 1792 1793 int rtw_mp_tx_pattern_idx(struct net_device *dev, 1794 struct iw_request_info *info, 1795 union iwreq_data *wrqu, char *extra); 1796 1797 int rtw_mp_tx_plcp_tx_data(struct net_device *dev, 1798 struct iw_request_info *info, 1799 union iwreq_data *wrqu, char *extra); 1800 1801 int rtw_mp_tx_plcp_tx_user(struct net_device *dev, 1802 struct iw_request_info *info, 1803 union iwreq_data *wrqu, char *extra); 1804 1805 int rtw_mp_tx_method(struct net_device *dev, 1806 struct iw_request_info *info, 1807 union iwreq_data *wrqu, char *extra); 1808 1809 int rtw_mp_config_phy(struct net_device *dev, 1810 struct iw_request_info *info, 1811 union iwreq_data *wrqu, char *extra); 1812 1813 int rtw_mp_phl_rfk(struct net_device *dev, 1814 struct iw_request_info *info, 1815 union iwreq_data *wrqu, char *extra); 1816 int rtw_mp_phl_btc_path(struct net_device *dev, 1817 struct iw_request_info *info, 1818 union iwreq_data *wrqu, char *extra); 1819 int rtw_mp_get_he(struct net_device *dev, 1820 struct iw_request_info *info, 1821 union iwreq_data *wrqu, char *extra); 1822 1823 #endif /* _RTW_MP_H_ */ 1824