xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8822cs/include/rtw_xmit.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2019 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef _RTW_XMIT_H_
16*4882a593Smuzhiyun #define _RTW_XMIT_H_
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
20*4882a593Smuzhiyun 	#ifdef CONFIG_TX_AGGREGATION
21*4882a593Smuzhiyun 		#ifdef CONFIG_RTL8822C
22*4882a593Smuzhiyun 			#ifdef CONFIG_SDIO_TX_FORMAT_DUMMY_AUTO
23*4882a593Smuzhiyun 				#define MAX_XMITBUF_SZ	(51200)
24*4882a593Smuzhiyun 			#else
25*4882a593Smuzhiyun 				#define MAX_XMITBUF_SZ	(32764)
26*4882a593Smuzhiyun 			#endif
27*4882a593Smuzhiyun 		#else
28*4882a593Smuzhiyun 			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
29*4882a593Smuzhiyun 		#endif
30*4882a593Smuzhiyun 		/* #define SDIO_TX_AGG_MAX	5 */
31*4882a593Smuzhiyun 	#else
32*4882a593Smuzhiyun 		#define MAX_XMITBUF_SZ (1664)
33*4882a593Smuzhiyun 		#define SDIO_TX_AGG_MAX	1
34*4882a593Smuzhiyun 	#endif
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun 	#if defined CONFIG_SDIO_HCI
37*4882a593Smuzhiyun 		#define NR_XMITBUFF	(16)
38*4882a593Smuzhiyun 		#define SDIO_TX_DIV_NUM (2)
39*4882a593Smuzhiyun 	#endif
40*4882a593Smuzhiyun 	#if defined(CONFIG_GSPI_HCI)
41*4882a593Smuzhiyun 		#define NR_XMITBUFF	(128)
42*4882a593Smuzhiyun 	#endif
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #elif defined (CONFIG_USB_HCI)
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	#ifdef CONFIG_USB_TX_AGGREGATION
47*4882a593Smuzhiyun 		#if defined(CONFIG_PLATFORM_ARM_SUNxI) || defined(CONFIG_PLATFORM_ARM_SUN6I) || defined(CONFIG_PLATFORM_ARM_SUN7I) || defined(CONFIG_PLATFORM_ARM_SUN8I) || defined(CONFIG_PLATFORM_ARM_SUN50IW1P1)
48*4882a593Smuzhiyun 			#define MAX_XMITBUF_SZ (12288)  /* 12k 1536*8 */
49*4882a593Smuzhiyun 		#elif defined (CONFIG_PLATFORM_MSTAR)
50*4882a593Smuzhiyun 			#define MAX_XMITBUF_SZ	7680	/* 7.5k */
51*4882a593Smuzhiyun 		#else
52*4882a593Smuzhiyun 			#define MAX_XMITBUF_SZ	(20480)	/* 20k */
53*4882a593Smuzhiyun 		#endif
54*4882a593Smuzhiyun 	#else
55*4882a593Smuzhiyun 		#define MAX_XMITBUF_SZ	(2048)
56*4882a593Smuzhiyun 	#endif
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	#ifdef CONFIG_SINGLE_XMIT_BUF
59*4882a593Smuzhiyun 		#define NR_XMITBUFF	(1)
60*4882a593Smuzhiyun 	#else
61*4882a593Smuzhiyun 		#define NR_XMITBUFF	(4)
62*4882a593Smuzhiyun 	#endif /* CONFIG_SINGLE_XMIT_BUF */
63*4882a593Smuzhiyun #elif defined (CONFIG_PCI_HCI)
64*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU
65*4882a593Smuzhiyun 	#define MAX_XMITBUF_SZ	(3500)
66*4882a593Smuzhiyun #else
67*4882a593Smuzhiyun 	#define MAX_XMITBUF_SZ	(1664)
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING
70*4882a593Smuzhiyun 	#define NR_XMITBUFF	(256)
71*4882a593Smuzhiyun #else
72*4882a593Smuzhiyun 	#define NR_XMITBUFF	(128)
73*4882a593Smuzhiyun #endif
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
78*4882a593Smuzhiyun 	#define XMITBUF_ALIGN_SZ 4
79*4882a593Smuzhiyun #else
80*4882a593Smuzhiyun 	#ifdef USB_XMITBUF_ALIGN_SZ
81*4882a593Smuzhiyun 		#define XMITBUF_ALIGN_SZ (USB_XMITBUF_ALIGN_SZ)
82*4882a593Smuzhiyun 	#else
83*4882a593Smuzhiyun 		#define XMITBUF_ALIGN_SZ 512
84*4882a593Smuzhiyun 	#endif
85*4882a593Smuzhiyun #endif
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /* xmit extension buff defination */
89*4882a593Smuzhiyun #define MAX_XMIT_EXTBUF_SZ	(1536)
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #ifdef CONFIG_SINGLE_XMIT_BUF
92*4882a593Smuzhiyun 	#define NR_XMIT_EXTBUFF	(1)
93*4882a593Smuzhiyun #elif defined(CONFIG_RTW_MGMT_QUEUE)
94*4882a593Smuzhiyun 	#define NR_XMIT_EXTBUFF	(64)
95*4882a593Smuzhiyun #else
96*4882a593Smuzhiyun 	#define NR_XMIT_EXTBUFF	(32)
97*4882a593Smuzhiyun #endif
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A
100*4882a593Smuzhiyun 	#define MAX_CMDBUF_SZ	(512 * 18)
101*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723D) && defined(CONFIG_LPS_POFF)
102*4882a593Smuzhiyun 	#define MAX_CMDBUF_SZ	(128*70) /*(8960)*/
103*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822C) && defined(CONFIG_WAR_OFFLOAD)
104*4882a593Smuzhiyun 	#define MAX_CMDBUF_SZ	(128*128) /*(16k) */
105*4882a593Smuzhiyun #else
106*4882a593Smuzhiyun 	#define MAX_CMDBUF_SZ	(5120)	/* (4096) */
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun #define MAX_BEACON_LEN	512
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun #define MAX_NUMBLKS		(1)
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun #define XMIT_VO_QUEUE (0)
114*4882a593Smuzhiyun #define XMIT_VI_QUEUE (1)
115*4882a593Smuzhiyun #define XMIT_BE_QUEUE (2)
116*4882a593Smuzhiyun #define XMIT_BK_QUEUE (3)
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define VO_QUEUE_INX		0
119*4882a593Smuzhiyun #define VI_QUEUE_INX		1
120*4882a593Smuzhiyun #define BE_QUEUE_INX		2
121*4882a593Smuzhiyun #define BK_QUEUE_INX		3
122*4882a593Smuzhiyun #define BCN_QUEUE_INX		4
123*4882a593Smuzhiyun #define MGT_QUEUE_INX		5
124*4882a593Smuzhiyun #define TXCMD_QUEUE_INX		6
125*4882a593Smuzhiyun #define HIGH_QUEUE_INX		7
126*4882a593Smuzhiyun /* keep high queue to be the last one, so we can extend HIQ to port 1, 2, ... */
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun #ifndef CONFIG_PORT_BASED_HIQ
129*4882a593Smuzhiyun #define HW_QUEUE_ENTRY	8
130*4882a593Smuzhiyun #else
131*4882a593Smuzhiyun #define HI_QUEUE_INX(n)	(HIGH_QUEUE_INX + (n))
132*4882a593Smuzhiyun #define HW_QUEUE_ENTRY	(8 + CONFIG_IFACE_NUMBER - 1)
133*4882a593Smuzhiyun #endif
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
136*4882a593Smuzhiyun 	#ifdef CONFIG_TRX_BD_ARCH
137*4882a593Smuzhiyun 		#define TX_BD_NUM			(128+1)	/* +1 result from ring buffer */
138*4882a593Smuzhiyun 	#else
139*4882a593Smuzhiyun 		#define TXDESC_NUM			128
140*4882a593Smuzhiyun 	#endif
141*4882a593Smuzhiyun #endif
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun #define WEP_IV(pattrib_iv, dot11txpn, keyidx)\
144*4882a593Smuzhiyun 	do {\
145*4882a593Smuzhiyun 		dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0 : (dot11txpn.val + 1);\
146*4882a593Smuzhiyun 		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
147*4882a593Smuzhiyun 		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
148*4882a593Smuzhiyun 		pattrib_iv[2] = dot11txpn._byte_.TSC2;\
149*4882a593Smuzhiyun 		pattrib_iv[3] = ((keyidx & 0x3)<<6);\
150*4882a593Smuzhiyun 	} while (0)
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun #define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\
154*4882a593Smuzhiyun 	do {\
155*4882a593Smuzhiyun 		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
156*4882a593Smuzhiyun 		pattrib_iv[0] = dot11txpn._byte_.TSC1;\
157*4882a593Smuzhiyun 		pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\
158*4882a593Smuzhiyun 		pattrib_iv[2] = dot11txpn._byte_.TSC0;\
159*4882a593Smuzhiyun 		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
160*4882a593Smuzhiyun 		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
161*4882a593Smuzhiyun 		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
162*4882a593Smuzhiyun 		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
163*4882a593Smuzhiyun 		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
164*4882a593Smuzhiyun 	} while (0)
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun #define AES_IV(pattrib_iv, dot11txpn, keyidx)\
167*4882a593Smuzhiyun 	do {\
168*4882a593Smuzhiyun 		dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0 : (dot11txpn.val + 1);\
169*4882a593Smuzhiyun 		pattrib_iv[0] = dot11txpn._byte_.TSC0;\
170*4882a593Smuzhiyun 		pattrib_iv[1] = dot11txpn._byte_.TSC1;\
171*4882a593Smuzhiyun 		pattrib_iv[2] = 0;\
172*4882a593Smuzhiyun 		pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\
173*4882a593Smuzhiyun 		pattrib_iv[4] = dot11txpn._byte_.TSC2;\
174*4882a593Smuzhiyun 		pattrib_iv[5] = dot11txpn._byte_.TSC3;\
175*4882a593Smuzhiyun 		pattrib_iv[6] = dot11txpn._byte_.TSC4;\
176*4882a593Smuzhiyun 		pattrib_iv[7] = dot11txpn._byte_.TSC5;\
177*4882a593Smuzhiyun 	} while (0)
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun #define GCMP_IV(a, b, c) AES_IV(a, b, c)
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun /* Check if AMPDU Tx is supported or not. If it is supported,
182*4882a593Smuzhiyun * it need to check "amsdu in ampdu" is supported or not.
183*4882a593Smuzhiyun * (ampdu_en, amsdu_ampdu_en) =
184*4882a593Smuzhiyun * (0, x) : AMPDU is not enable, but AMSDU is valid to send.
185*4882a593Smuzhiyun * (1, 0) : AMPDU is enable, AMSDU in AMPDU is not enable. So, AMSDU is not valid to send.
186*4882a593Smuzhiyun * (1, 1) : AMPDU and AMSDU in AMPDU are enable. So, AMSDU is valid to send.
187*4882a593Smuzhiyun */
188*4882a593Smuzhiyun #define IS_AMSDU_AMPDU_NOT_VALID(pattrib)\
189*4882a593Smuzhiyun 	 ((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun #define IS_AMSDU_AMPDU_VALID(pattrib)\
192*4882a593Smuzhiyun 	 !((pattrib->ampdu_en == _TRUE) && (pattrib->amsdu_ampdu_en == _FALSE))
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
195*4882a593Smuzhiyun #define HWXMIT_ENTRY 5
196*4882a593Smuzhiyun #else
197*4882a593Smuzhiyun #define HWXMIT_ENTRY 4
198*4882a593Smuzhiyun #endif
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun enum DEQUEUE_TYPE {
201*4882a593Smuzhiyun 	UNI_BMC_DATA,
202*4882a593Smuzhiyun 	UNI_MGMT,
203*4882a593Smuzhiyun 	ALL_FRAME
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun /* For Buffer Descriptor ring architecture */
207*4882a593Smuzhiyun #if defined(BUF_DESC_ARCH) || defined(CONFIG_TRX_BD_ARCH)
208*4882a593Smuzhiyun 	#if defined(CONFIG_RTL8192E)
209*4882a593Smuzhiyun 		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
210*4882a593Smuzhiyun 	#elif defined(CONFIG_RTL8814A)
211*4882a593Smuzhiyun 		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
212*4882a593Smuzhiyun 	#else
213*4882a593Smuzhiyun 		#define TX_BUFFER_SEG_NUM	1 /* 0:2 seg, 1: 4 seg, 2: 8 seg. */
214*4882a593Smuzhiyun 	#endif
215*4882a593Smuzhiyun #endif
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) ||\
218*4882a593Smuzhiyun 	defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8192E) ||\
219*4882a593Smuzhiyun 	defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8703B) ||\
220*4882a593Smuzhiyun 	defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) ||\
221*4882a593Smuzhiyun 	defined(CONFIG_RTL8710B) || defined(CONFIG_RTL8192F) ||\
222*4882a593Smuzhiyun 	defined(CONFIG_RTL8723F)
223*4882a593Smuzhiyun 	#define TXDESC_SIZE 40
224*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)
225*4882a593Smuzhiyun 	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8822B */
226*4882a593Smuzhiyun #elif defined(CONFIG_RTL8821C)
227*4882a593Smuzhiyun 	#define TXDESC_SIZE 48		/* HALMAC_TX_DESC_SIZE_8821C */
228*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814B)
229*4882a593Smuzhiyun 	#define TXDESC_SIZE (16 + 32)
230*4882a593Smuzhiyun #else
231*4882a593Smuzhiyun 	#define TXDESC_SIZE 32 /* old IC (ex: 8188E) */
232*4882a593Smuzhiyun #endif
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE
235*4882a593Smuzhiyun 	#define EARLY_MODE_INFO_SIZE	8
236*4882a593Smuzhiyun #endif
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
240*4882a593Smuzhiyun 	#define TXDESC_OFFSET TXDESC_SIZE
241*4882a593Smuzhiyun #endif
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
244*4882a593Smuzhiyun 	#ifdef USB_PACKET_OFFSET_SZ
245*4882a593Smuzhiyun 		#define PACKET_OFFSET_SZ (USB_PACKET_OFFSET_SZ)
246*4882a593Smuzhiyun 	#else
247*4882a593Smuzhiyun 		#define PACKET_OFFSET_SZ (8)
248*4882a593Smuzhiyun 	#endif
249*4882a593Smuzhiyun 	#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ)
250*4882a593Smuzhiyun #endif
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
253*4882a593Smuzhiyun 	#if defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C) || defined(CONFIG_RTL8822C) || defined(CONFIG_TRX_BD_ARCH)
254*4882a593Smuzhiyun 		/* this section is defined for buffer descriptor ring architecture */
255*4882a593Smuzhiyun 		#define TX_WIFI_INFO_SIZE (TXDESC_SIZE) /* it may add 802.11 hdr or others... */
256*4882a593Smuzhiyun 		/* tx desc and payload are in the same buf */
257*4882a593Smuzhiyun 		#define TXDESC_OFFSET (TX_WIFI_INFO_SIZE)
258*4882a593Smuzhiyun 	#else
259*4882a593Smuzhiyun 		/* tx desc and payload are NOT in the same buf */
260*4882a593Smuzhiyun 		#define TXDESC_OFFSET (0)
261*4882a593Smuzhiyun 		/* 8188ee/8723be/8812ae/8821ae has extra PCI DMA info in tx desc */
262*4882a593Smuzhiyun 		#define TX_DESC_NEXT_DESC_OFFSET	(TXDESC_SIZE + 8)
263*4882a593Smuzhiyun 	#endif
264*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun enum TXDESC_SC {
267*4882a593Smuzhiyun 	SC_DONT_CARE = 0x00,
268*4882a593Smuzhiyun 	SC_UPPER = 0x01,
269*4882a593Smuzhiyun 	SC_LOWER = 0x02,
270*4882a593Smuzhiyun 	SC_DUPLICATE = 0x03
271*4882a593Smuzhiyun };
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
274*4882a593Smuzhiyun 	#ifndef CONFIG_TRX_BD_ARCH	/* CONFIG_TRX_BD_ARCH doesn't need this */
275*4882a593Smuzhiyun 		#define TXDESC_64_BYTES
276*4882a593Smuzhiyun 	#endif
277*4882a593Smuzhiyun #elif defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8723B) \
278*4882a593Smuzhiyun 	|| defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV) || defined(CONFIG_RTL8723D) \
279*4882a593Smuzhiyun 	|| defined(CONFIG_RTL8192F) || defined(CONFIG_RTL8723F)
280*4882a593Smuzhiyun 	#define TXDESC_40_BYTES
281*4882a593Smuzhiyun #endif
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH
284*4882a593Smuzhiyun struct tx_buf_desc {
285*4882a593Smuzhiyun #ifdef CONFIG_64BIT_DMA
286*4882a593Smuzhiyun #define TX_BUFFER_SEG_SIZE	4	/* in unit of DWORD */
287*4882a593Smuzhiyun #else
288*4882a593Smuzhiyun #define TX_BUFFER_SEG_SIZE	2	/* in unit of DWORD */
289*4882a593Smuzhiyun #endif
290*4882a593Smuzhiyun 	unsigned int dword[TX_BUFFER_SEG_SIZE * (2 << TX_BUFFER_SEG_NUM)];
291*4882a593Smuzhiyun } __packed;
292*4882a593Smuzhiyun #elif (defined(CONFIG_RTL8192E) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8822C)) && defined(CONFIG_PCI_HCI) /* 8192ee or 8814ae */
293*4882a593Smuzhiyun /* 8192EE_TODO */
294*4882a593Smuzhiyun struct tx_desc {
295*4882a593Smuzhiyun 	unsigned int txdw0;
296*4882a593Smuzhiyun 	unsigned int txdw1;
297*4882a593Smuzhiyun 	unsigned int txdw2;
298*4882a593Smuzhiyun 	unsigned int txdw3;
299*4882a593Smuzhiyun 	unsigned int txdw4;
300*4882a593Smuzhiyun 	unsigned int txdw5;
301*4882a593Smuzhiyun 	unsigned int txdw6;
302*4882a593Smuzhiyun 	unsigned int txdw7;
303*4882a593Smuzhiyun };
304*4882a593Smuzhiyun #else
305*4882a593Smuzhiyun struct tx_desc {
306*4882a593Smuzhiyun 	unsigned int txdw0;
307*4882a593Smuzhiyun 	unsigned int txdw1;
308*4882a593Smuzhiyun 	unsigned int txdw2;
309*4882a593Smuzhiyun 	unsigned int txdw3;
310*4882a593Smuzhiyun 	unsigned int txdw4;
311*4882a593Smuzhiyun 	unsigned int txdw5;
312*4882a593Smuzhiyun 	unsigned int txdw6;
313*4882a593Smuzhiyun 	unsigned int txdw7;
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #if defined(TXDESC_40_BYTES) || defined(TXDESC_64_BYTES)
316*4882a593Smuzhiyun 	unsigned int txdw8;
317*4882a593Smuzhiyun 	unsigned int txdw9;
318*4882a593Smuzhiyun #endif /* TXDESC_40_BYTES */
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun #ifdef TXDESC_64_BYTES
321*4882a593Smuzhiyun 	unsigned int txdw10;
322*4882a593Smuzhiyun 	unsigned int txdw11;
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun 	/* 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now,  our descriptor */
325*4882a593Smuzhiyun 	/* size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute */
326*4882a593Smuzhiyun 	/* memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor */
327*4882a593Smuzhiyun 	/* number or enlarge descriptor size as 64 bytes. */
328*4882a593Smuzhiyun 	unsigned int txdw12;
329*4882a593Smuzhiyun 	unsigned int txdw13;
330*4882a593Smuzhiyun 	unsigned int txdw14;
331*4882a593Smuzhiyun 	unsigned int txdw15;
332*4882a593Smuzhiyun #endif
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun #endif
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun #ifndef CONFIG_TRX_BD_ARCH
337*4882a593Smuzhiyun union txdesc {
338*4882a593Smuzhiyun 	struct tx_desc txdesc;
339*4882a593Smuzhiyun 	unsigned int value[TXDESC_SIZE >> 2];
340*4882a593Smuzhiyun };
341*4882a593Smuzhiyun #endif
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
344*4882a593Smuzhiyun #define PCI_MAX_TX_QUEUE_COUNT	HW_QUEUE_ENTRY
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun struct rtw_tx_ring {
347*4882a593Smuzhiyun 	unsigned char	qid;
348*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH
349*4882a593Smuzhiyun 	struct tx_buf_desc	*buf_desc;
350*4882a593Smuzhiyun #else
351*4882a593Smuzhiyun 	struct tx_desc	*desc;
352*4882a593Smuzhiyun #endif
353*4882a593Smuzhiyun 	dma_addr_t	dma;
354*4882a593Smuzhiyun 	unsigned int	idx;
355*4882a593Smuzhiyun 	unsigned int	entries;
356*4882a593Smuzhiyun 	_queue		queue;
357*4882a593Smuzhiyun 	u32		qlen;
358*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH
359*4882a593Smuzhiyun 	u16		hw_rp_cache;
360*4882a593Smuzhiyun #endif
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun #define TX_BAK_FRMAE_CNT	10
366*4882a593Smuzhiyun #define TX_BAK_DESC_LEN	48	/* byte */
367*4882a593Smuzhiyun #define TX_BAK_DATA_LEN		30	/* byte */
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun struct rtw_tx_desc_backup {
370*4882a593Smuzhiyun 	int tx_bak_rp;
371*4882a593Smuzhiyun 	int tx_bak_wp;
372*4882a593Smuzhiyun 	u8 tx_bak_desc[TX_BAK_DESC_LEN];
373*4882a593Smuzhiyun 	u8 tx_bak_data_hdr[TX_BAK_DATA_LEN];
374*4882a593Smuzhiyun 	u8 tx_desc_size;
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun #endif
377*4882a593Smuzhiyun #endif
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun struct	hw_xmit	{
380*4882a593Smuzhiyun 	/* _lock xmit_lock; */
381*4882a593Smuzhiyun 	/* _list	pending; */
382*4882a593Smuzhiyun 	_queue *sta_queue;
383*4882a593Smuzhiyun 	/* struct hw_txqueue *phwtxqueue; */
384*4882a593Smuzhiyun 	/* sint	txcmdcnt; */
385*4882a593Smuzhiyun 	int	accnt;
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun struct pkt_attrib {
389*4882a593Smuzhiyun 	u8	type;
390*4882a593Smuzhiyun 	u8	subtype;
391*4882a593Smuzhiyun 	u8	bswenc;
392*4882a593Smuzhiyun 	u8	dhcp_pkt;
393*4882a593Smuzhiyun 	u16	ether_type;
394*4882a593Smuzhiyun 	u16	seqnum;
395*4882a593Smuzhiyun 	u8	hw_ssn_sel;	/* for HW_SEQ0,1,2,3 */
396*4882a593Smuzhiyun 	u16	pkt_hdrlen;	/* the original 802.3 pkt header len */
397*4882a593Smuzhiyun 	u16	hdrlen;		/* the WLAN Header Len */
398*4882a593Smuzhiyun 	u32	pktlen;		/* the original 802.3 pkt raw_data len (not include ether_hdr data) */
399*4882a593Smuzhiyun 	u32	last_txcmdsz;
400*4882a593Smuzhiyun 	u8	nr_frags;
401*4882a593Smuzhiyun 	u8	encrypt;	/* when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith */
402*4882a593Smuzhiyun 	u8	bmc_camid;
403*4882a593Smuzhiyun 	u8	iv_len;
404*4882a593Smuzhiyun 	u8	icv_len;
405*4882a593Smuzhiyun 	u8	iv[18];
406*4882a593Smuzhiyun 	u8	icv[16];
407*4882a593Smuzhiyun 	u8	priority;
408*4882a593Smuzhiyun 	u8	ack_policy;
409*4882a593Smuzhiyun 	u8	mac_id;
410*4882a593Smuzhiyun 	u8	vcs_mode;	/* virtual carrier sense method */
411*4882a593Smuzhiyun 	u8	dst[ETH_ALEN];
412*4882a593Smuzhiyun 	u8	src[ETH_ALEN];
413*4882a593Smuzhiyun 	u8	ta[ETH_ALEN];
414*4882a593Smuzhiyun 	u8	ra[ETH_ALEN];
415*4882a593Smuzhiyun #ifdef CONFIG_RTW_WDS
416*4882a593Smuzhiyun 	u8	wds;
417*4882a593Smuzhiyun #endif
418*4882a593Smuzhiyun #ifdef CONFIG_RTW_MESH
419*4882a593Smuzhiyun 	u8	mda[ETH_ALEN];	/* mesh da */
420*4882a593Smuzhiyun 	u8	msa[ETH_ALEN];	/* mesh sa */
421*4882a593Smuzhiyun 	u8	meshctrl_len;	/* Length of Mesh Control field */
422*4882a593Smuzhiyun 	u8	mesh_frame_mode;
423*4882a593Smuzhiyun 	#if CONFIG_RTW_MESH_DATA_BMC_TO_UC
424*4882a593Smuzhiyun 	u8 mb2u;
425*4882a593Smuzhiyun 	#endif
426*4882a593Smuzhiyun 	u8 mfwd_ttl;
427*4882a593Smuzhiyun 	u32 mseq;
428*4882a593Smuzhiyun #endif
429*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
430*4882a593Smuzhiyun 	u8	hw_csum;
431*4882a593Smuzhiyun #endif
432*4882a593Smuzhiyun 	u8	key_idx;
433*4882a593Smuzhiyun 	u8	qos_en;
434*4882a593Smuzhiyun 	u8	ht_en;
435*4882a593Smuzhiyun 	u8	raid;/* rate adpative id */
436*4882a593Smuzhiyun 	u8	bwmode;
437*4882a593Smuzhiyun 	u8	ch_offset;/* PRIME_CHNL_OFFSET */
438*4882a593Smuzhiyun 	u8	sgi;/* short GI */
439*4882a593Smuzhiyun 	u8	ampdu_en;/* tx ampdu enable */
440*4882a593Smuzhiyun 	u8	ampdu_spacing; /* ampdu_min_spacing for peer sta's rx */
441*4882a593Smuzhiyun 	u8	amsdu;
442*4882a593Smuzhiyun 	u8	amsdu_ampdu_en;/* tx amsdu in ampdu enable */
443*4882a593Smuzhiyun 	u8	mdata;/* more data bit */
444*4882a593Smuzhiyun 	u8	pctrl;/* per packet txdesc control enable */
445*4882a593Smuzhiyun 	u8	triggered;/* for ap mode handling Power Saving sta */
446*4882a593Smuzhiyun 	u8	qsel;
447*4882a593Smuzhiyun 	u8	order;/* order bit */
448*4882a593Smuzhiyun 	u8	eosp;
449*4882a593Smuzhiyun 	u8	rate;
450*4882a593Smuzhiyun 	u8	intel_proxim;
451*4882a593Smuzhiyun 	u8	retry_ctrl;
452*4882a593Smuzhiyun 	u8   mbssid;
453*4882a593Smuzhiyun 	u8	ldpc;
454*4882a593Smuzhiyun 	u8	stbc;
455*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA
456*4882a593Smuzhiyun 	u8	trigger_frame;
457*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	struct sta_info *psta;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	u8 rtsen;
462*4882a593Smuzhiyun 	u8 cts2self;
463*4882a593Smuzhiyun 	union Keytype	dot11tkiptxmickey;
464*4882a593Smuzhiyun 	/* union Keytype	dot11tkiprxmickey; */
465*4882a593Smuzhiyun 	union Keytype	dot118021x_UncstKey;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun #ifdef CONFIG_TDLS
468*4882a593Smuzhiyun 	u8 direct_link;
469*4882a593Smuzhiyun 	struct sta_info *ptdls_sta;
470*4882a593Smuzhiyun #endif /* CONFIG_TDLS */
471*4882a593Smuzhiyun 	u8 key_type;
472*4882a593Smuzhiyun 
473*4882a593Smuzhiyun 	u8 icmp_pkt;
474*4882a593Smuzhiyun 	u8 hipriority_pkt; /* high priority packet */
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING
477*4882a593Smuzhiyun 	u16 txbf_p_aid;/*beamforming Partial_AID*/
478*4882a593Smuzhiyun 	u16 txbf_g_id;/*beamforming Group ID*/
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	/*
481*4882a593Smuzhiyun 	 * 2'b00: Unicast NDPA
482*4882a593Smuzhiyun 	 * 2'b01: Broadcast NDPA
483*4882a593Smuzhiyun 	 * 2'b10: Beamforming Report Poll
484*4882a593Smuzhiyun 	 * 2'b11: Final Beamforming Report Poll
485*4882a593Smuzhiyun 	 */
486*4882a593Smuzhiyun 	u8 bf_pkt_type;
487*4882a593Smuzhiyun #endif
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
490*4882a593Smuzhiyun 	u8 ps_dontq; /* 1: this frame can't be queued at PS state */
491*4882a593Smuzhiyun #endif
492*4882a593Smuzhiyun };
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun #ifdef CONFIG_RTW_WDS
495*4882a593Smuzhiyun #define XATTRIB_GET_WDS(xattrib) ((xattrib)->wds)
496*4882a593Smuzhiyun #else
497*4882a593Smuzhiyun #define XATTRIB_GET_WDS(xattrib) 0
498*4882a593Smuzhiyun #endif
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun #ifdef CONFIG_RTW_MESH
501*4882a593Smuzhiyun #define XATTRIB_GET_MCTRL_LEN(xattrib) ((xattrib)->meshctrl_len)
502*4882a593Smuzhiyun #else
503*4882a593Smuzhiyun #define XATTRIB_GET_MCTRL_LEN(xattrib) 0
504*4882a593Smuzhiyun #endif
505*4882a593Smuzhiyun 
506*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU
507*4882a593Smuzhiyun enum {
508*4882a593Smuzhiyun 	RTW_AMSDU_TIMER_UNSET = 0,
509*4882a593Smuzhiyun 	RTW_AMSDU_TIMER_SETTING,
510*4882a593Smuzhiyun 	RTW_AMSDU_TIMER_TIMEOUT,
511*4882a593Smuzhiyun };
512*4882a593Smuzhiyun #endif
513*4882a593Smuzhiyun 
514*4882a593Smuzhiyun #define WLANHDR_OFFSET	64
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun #define NULL_FRAMETAG		(0x0)
517*4882a593Smuzhiyun #define DATA_FRAMETAG		0x01
518*4882a593Smuzhiyun #define L2_FRAMETAG		0x02
519*4882a593Smuzhiyun #define MGNT_FRAMETAG		0x03
520*4882a593Smuzhiyun #define AMSDU_FRAMETAG	0x04
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun #define EII_FRAMETAG		0x05
523*4882a593Smuzhiyun #define IEEE8023_FRAMETAG  0x06
524*4882a593Smuzhiyun 
525*4882a593Smuzhiyun #define MP_FRAMETAG		0x07
526*4882a593Smuzhiyun 
527*4882a593Smuzhiyun #define TXAGG_FRAMETAG	0x08
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun enum {
530*4882a593Smuzhiyun 	XMITBUF_DATA = 0,
531*4882a593Smuzhiyun 	XMITBUF_MGNT = 1,
532*4882a593Smuzhiyun 	XMITBUF_CMD = 2,
533*4882a593Smuzhiyun };
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun bool rtw_xmit_ac_blocked(_adapter *adapter);
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun struct  submit_ctx {
538*4882a593Smuzhiyun 	systime submit_time; /* */
539*4882a593Smuzhiyun 	u32 timeout_ms; /* <0: not synchronous, 0: wait forever, >0: up to ms waiting */
540*4882a593Smuzhiyun 	int status; /* status for operation */
541*4882a593Smuzhiyun #ifdef PLATFORM_LINUX
542*4882a593Smuzhiyun 	struct completion done;
543*4882a593Smuzhiyun #endif
544*4882a593Smuzhiyun };
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun enum {
547*4882a593Smuzhiyun 	RTW_SCTX_SUBMITTED = -1,
548*4882a593Smuzhiyun 	RTW_SCTX_DONE_SUCCESS = 0,
549*4882a593Smuzhiyun 	RTW_SCTX_DONE_UNKNOWN,
550*4882a593Smuzhiyun 	RTW_SCTX_DONE_TIMEOUT,
551*4882a593Smuzhiyun 	RTW_SCTX_DONE_BUF_ALLOC,
552*4882a593Smuzhiyun 	RTW_SCTX_DONE_BUF_FREE,
553*4882a593Smuzhiyun 	RTW_SCTX_DONE_WRITE_PORT_ERR,
554*4882a593Smuzhiyun 	RTW_SCTX_DONE_TX_DESC_NA,
555*4882a593Smuzhiyun 	RTW_SCTX_DONE_TX_DENY,
556*4882a593Smuzhiyun 	RTW_SCTX_DONE_CCX_PKT_FAIL,
557*4882a593Smuzhiyun 	RTW_SCTX_DONE_DRV_STOP,
558*4882a593Smuzhiyun 	RTW_SCTX_DONE_DEV_REMOVE,
559*4882a593Smuzhiyun 	RTW_SCTX_DONE_CMD_ERROR,
560*4882a593Smuzhiyun 	RTW_SCTX_DONE_CMD_DROP,
561*4882a593Smuzhiyun 	RTX_SCTX_CSTR_WAIT_RPT2,
562*4882a593Smuzhiyun };
563*4882a593Smuzhiyun 
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun void rtw_sctx_init(struct submit_ctx *sctx, int timeout_ms);
566*4882a593Smuzhiyun int rtw_sctx_wait(struct submit_ctx *sctx, const char *msg);
567*4882a593Smuzhiyun void rtw_sctx_done_err(struct submit_ctx **sctx, int status);
568*4882a593Smuzhiyun void rtw_sctx_done(struct submit_ctx **sctx);
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun struct xmit_buf {
571*4882a593Smuzhiyun 	_list	list;
572*4882a593Smuzhiyun 
573*4882a593Smuzhiyun 	_adapter *padapter;
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	u8 *pallocated_buf;
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 	u8 *pbuf;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun 	void *priv_data;
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	u16 buf_tag; /* 0: Normal xmitbuf, 1: extension xmitbuf, 2:cmd xmitbuf */
582*4882a593Smuzhiyun 	u16 flags;
583*4882a593Smuzhiyun 	u32 alloc_sz;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	u32  len;
586*4882a593Smuzhiyun 
587*4882a593Smuzhiyun 	struct submit_ctx *sctx;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
590*4882a593Smuzhiyun 
591*4882a593Smuzhiyun 	/* u32 sz[8]; */
592*4882a593Smuzhiyun 	u32	ff_hwaddr;
593*4882a593Smuzhiyun #ifdef RTW_HALMAC
594*4882a593Smuzhiyun 	u8 bulkout_id; /* for halmac */
595*4882a593Smuzhiyun #endif /* RTW_HALMAC */
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	PURB	pxmit_urb[8];
598*4882a593Smuzhiyun 	dma_addr_t dma_transfer_addr;	/* (in) dma addr for transfer_buffer */
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 	u8 bpending[8];
601*4882a593Smuzhiyun 
602*4882a593Smuzhiyun 	sint last[8];
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun #endif
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
607*4882a593Smuzhiyun 	u8 *phead;
608*4882a593Smuzhiyun 	u8 *pdata;
609*4882a593Smuzhiyun 	u8 *ptail;
610*4882a593Smuzhiyun 	u8 *pend;
611*4882a593Smuzhiyun 	u32 ff_hwaddr;
612*4882a593Smuzhiyun 	u8	pg_num;
613*4882a593Smuzhiyun 	u8	agg_num;
614*4882a593Smuzhiyun #endif
615*4882a593Smuzhiyun 
616*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
617*4882a593Smuzhiyun #ifdef CONFIG_TRX_BD_ARCH
618*4882a593Smuzhiyun 	/*struct tx_buf_desc *buf_desc;*/
619*4882a593Smuzhiyun #else
620*4882a593Smuzhiyun 	struct tx_desc *desc;
621*4882a593Smuzhiyun #endif
622*4882a593Smuzhiyun #endif
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun #ifdef CONFIG_PCIE_DMA_COHERENT
625*4882a593Smuzhiyun 	dma_addr_t dma_bpa;
626*4882a593Smuzhiyun #endif
627*4882a593Smuzhiyun 
628*4882a593Smuzhiyun #if defined(DBG_XMIT_BUF) || defined(DBG_XMIT_BUF_EXT)
629*4882a593Smuzhiyun 	u8 no;
630*4882a593Smuzhiyun #endif
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun };
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun struct xmit_frame {
636*4882a593Smuzhiyun 	_list	list;
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 	struct pkt_attrib attrib;
639*4882a593Smuzhiyun 
640*4882a593Smuzhiyun 	u16 os_qid;
641*4882a593Smuzhiyun 	_pkt *pkt;
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	int	frame_tag;
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun 	_adapter *padapter;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	u8	*buf_addr;
648*4882a593Smuzhiyun 
649*4882a593Smuzhiyun 	struct xmit_buf *pxmitbuf;
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
652*4882a593Smuzhiyun 	u8	pg_num;
653*4882a593Smuzhiyun 	u8	agg_num;
654*4882a593Smuzhiyun #endif
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
657*4882a593Smuzhiyun #ifdef CONFIG_USB_TX_AGGREGATION
658*4882a593Smuzhiyun 	u8	agg_num;
659*4882a593Smuzhiyun #endif
660*4882a593Smuzhiyun 	s8	pkt_offset;
661*4882a593Smuzhiyun #endif
662*4882a593Smuzhiyun 
663*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK
664*4882a593Smuzhiyun 	u8 ack_report;
665*4882a593Smuzhiyun #endif
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	u8 *alloc_addr; /* the actual address this xmitframe allocated */
668*4882a593Smuzhiyun 	u8 ext_tag; /* 0:data, 1:mgmt */
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun };
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun struct tx_servq {
673*4882a593Smuzhiyun 	_list	tx_pending;
674*4882a593Smuzhiyun 	_queue	sta_pending;
675*4882a593Smuzhiyun 	int qcnt;
676*4882a593Smuzhiyun };
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 
679*4882a593Smuzhiyun struct sta_xmit_priv {
680*4882a593Smuzhiyun 	_lock	lock;
681*4882a593Smuzhiyun 	sint	option;
682*4882a593Smuzhiyun 	sint	apsd_setting;	/* When bit mask is on, the associated edca queue supports APSD. */
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 
685*4882a593Smuzhiyun 	/* struct tx_servq blk_q[MAX_NUMBLKS]; */
686*4882a593Smuzhiyun 	struct tx_servq	be_q;			/* priority == 0,3 */
687*4882a593Smuzhiyun 	struct tx_servq	bk_q;			/* priority == 1,2 */
688*4882a593Smuzhiyun 	struct tx_servq	vi_q;			/* priority == 4,5 */
689*4882a593Smuzhiyun 	struct tx_servq	vo_q;			/* priority == 6,7 */
690*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
691*4882a593Smuzhiyun 	struct tx_servq	mgmt_q;
692*4882a593Smuzhiyun #endif
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	_list	legacy_dz;
695*4882a593Smuzhiyun 	_list  apsd;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	u16 txseq_tid[16];
698*4882a593Smuzhiyun 
699*4882a593Smuzhiyun 	/* uint	sta_tx_bytes; */
700*4882a593Smuzhiyun 	/* u64	sta_tx_pkts; */
701*4882a593Smuzhiyun 	/* uint	sta_tx_fail; */
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 
704*4882a593Smuzhiyun };
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 
707*4882a593Smuzhiyun struct	hw_txqueue	{
708*4882a593Smuzhiyun 	volatile sint	head;
709*4882a593Smuzhiyun 	volatile sint	tail;
710*4882a593Smuzhiyun 	volatile sint 	free_sz;	/* in units of 64 bytes */
711*4882a593Smuzhiyun 	volatile sint      free_cmdsz;
712*4882a593Smuzhiyun 	volatile sint	 txsz[8];
713*4882a593Smuzhiyun 	uint	ff_hwaddr;
714*4882a593Smuzhiyun 	uint	cmd_hwaddr;
715*4882a593Smuzhiyun 	sint	ac_tag;
716*4882a593Smuzhiyun };
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun struct agg_pkt_info {
719*4882a593Smuzhiyun 	u16 offset;
720*4882a593Smuzhiyun 	u16 pkt_len;
721*4882a593Smuzhiyun };
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun enum cmdbuf_type {
724*4882a593Smuzhiyun 	CMDBUF_BEACON = 0x00,
725*4882a593Smuzhiyun 	CMDBUF_RSVD,
726*4882a593Smuzhiyun 	CMDBUF_MAX
727*4882a593Smuzhiyun };
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun u8 rtw_get_hwseq_no(_adapter *padapter);
730*4882a593Smuzhiyun 
731*4882a593Smuzhiyun struct	xmit_priv	{
732*4882a593Smuzhiyun 
733*4882a593Smuzhiyun 	_lock	lock;
734*4882a593Smuzhiyun 
735*4882a593Smuzhiyun 	_sema	xmit_sema;
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun 	/* _queue	blk_strms[MAX_NUMBLKS]; */
738*4882a593Smuzhiyun 	_queue	be_pending;
739*4882a593Smuzhiyun 	_queue	bk_pending;
740*4882a593Smuzhiyun 	_queue	vi_pending;
741*4882a593Smuzhiyun 	_queue	vo_pending;
742*4882a593Smuzhiyun 	_queue	mgmt_pending;
743*4882a593Smuzhiyun 
744*4882a593Smuzhiyun 	/* _queue	legacy_dz_queue; */
745*4882a593Smuzhiyun 	/* _queue	apsd_queue; */
746*4882a593Smuzhiyun 
747*4882a593Smuzhiyun 	u8 *pallocated_frame_buf;
748*4882a593Smuzhiyun 	u8 *pxmit_frame_buf;
749*4882a593Smuzhiyun 	uint free_xmitframe_cnt;
750*4882a593Smuzhiyun 	_queue	free_xmit_queue;
751*4882a593Smuzhiyun 
752*4882a593Smuzhiyun 	/* uint mapping_addr; */
753*4882a593Smuzhiyun 	/* uint pkt_sz; */
754*4882a593Smuzhiyun 
755*4882a593Smuzhiyun 	u8 *xframe_ext_alloc_addr;
756*4882a593Smuzhiyun 	u8 *xframe_ext;
757*4882a593Smuzhiyun 	uint free_xframe_ext_cnt;
758*4882a593Smuzhiyun 	_queue free_xframe_ext_queue;
759*4882a593Smuzhiyun 
760*4882a593Smuzhiyun 	/* struct	hw_txqueue	be_txqueue; */
761*4882a593Smuzhiyun 	/* struct	hw_txqueue	bk_txqueue; */
762*4882a593Smuzhiyun 	/* struct	hw_txqueue	vi_txqueue; */
763*4882a593Smuzhiyun 	/* struct	hw_txqueue	vo_txqueue; */
764*4882a593Smuzhiyun 	/* struct	hw_txqueue	bmc_txqueue; */
765*4882a593Smuzhiyun 
766*4882a593Smuzhiyun 	uint	frag_len;
767*4882a593Smuzhiyun 
768*4882a593Smuzhiyun 	_adapter	*adapter;
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	u8   vcs_setting;
771*4882a593Smuzhiyun 	u8	vcs;
772*4882a593Smuzhiyun 	u8	vcs_type;
773*4882a593Smuzhiyun 	/* u16  rts_thresh; */
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun 	u64	tx_bytes;
776*4882a593Smuzhiyun 	u64	tx_pkts;
777*4882a593Smuzhiyun 	u64	tx_drop;
778*4882a593Smuzhiyun 	u64	last_tx_pkts;
779*4882a593Smuzhiyun 
780*4882a593Smuzhiyun 	struct hw_xmit *hwxmits;
781*4882a593Smuzhiyun 	u8	hwxmit_entry;
782*4882a593Smuzhiyun 
783*4882a593Smuzhiyun 	u8	wmm_para_seq[4];/* sequence for wmm ac parameter strength from large to small. it's value is 0->vo, 1->vi, 2->be, 3->bk. */
784*4882a593Smuzhiyun 
785*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
786*4882a593Smuzhiyun 	_sema	tx_retevt;/* all tx return event; */
787*4882a593Smuzhiyun 	u8		txirp_cnt;
788*4882a593Smuzhiyun 
789*4882a593Smuzhiyun 	_tasklet xmit_tasklet;
790*4882a593Smuzhiyun 
791*4882a593Smuzhiyun 	/* per AC pending irp */
792*4882a593Smuzhiyun 	int beq_cnt;
793*4882a593Smuzhiyun 	int bkq_cnt;
794*4882a593Smuzhiyun 	int viq_cnt;
795*4882a593Smuzhiyun 	int voq_cnt;
796*4882a593Smuzhiyun 
797*4882a593Smuzhiyun #endif
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
800*4882a593Smuzhiyun 	/* Tx */
801*4882a593Smuzhiyun 	struct rtw_tx_ring	tx_ring[PCI_MAX_TX_QUEUE_COUNT];
802*4882a593Smuzhiyun 	int	txringcount[PCI_MAX_TX_QUEUE_COUNT];
803*4882a593Smuzhiyun 	u8 	beaconDMAing;		/* flag of indicating beacon is transmiting to HW by DMA */
804*4882a593Smuzhiyun 	_tasklet xmit_tasklet;
805*4882a593Smuzhiyun #endif
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
808*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_TASKLET
809*4882a593Smuzhiyun 	_tasklet xmit_tasklet;
810*4882a593Smuzhiyun #else
811*4882a593Smuzhiyun 	_thread_hdl_	SdioXmitThread;
812*4882a593Smuzhiyun 	_sema		SdioXmitSema;
813*4882a593Smuzhiyun 	#ifdef SDIO_FREE_XMIT_BUF_SEMA
814*4882a593Smuzhiyun 	_sema		sdio_free_xmitbuf_sema;
815*4882a593Smuzhiyun 	#endif
816*4882a593Smuzhiyun #endif /* CONFIG_SDIO_TX_TASKLET */
817*4882a593Smuzhiyun #endif /* CONFIG_SDIO_HCI */
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	_queue free_xmitbuf_queue;
820*4882a593Smuzhiyun 	_queue pending_xmitbuf_queue;
821*4882a593Smuzhiyun 	u8 *pallocated_xmitbuf;
822*4882a593Smuzhiyun 	u8 *pxmitbuf;
823*4882a593Smuzhiyun 	uint free_xmitbuf_cnt;
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 	_queue free_xmit_extbuf_queue;
826*4882a593Smuzhiyun 	u8 *pallocated_xmit_extbuf;
827*4882a593Smuzhiyun 	u8 *pxmit_extbuf;
828*4882a593Smuzhiyun 	uint free_xmit_extbuf_cnt;
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	struct xmit_buf	pcmd_xmitbuf[CMDBUF_MAX];
831*4882a593Smuzhiyun 	u8   hw_ssn_seq_no;/* mapping to REG_HW_SEQ 0,1,2,3 */
832*4882a593Smuzhiyun 	u16	nqos_ssn;
833*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE
834*4882a593Smuzhiyun 
835*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
836*4882a593Smuzhiyun #define MAX_AGG_PKT_NUM 20
837*4882a593Smuzhiyun #else
838*4882a593Smuzhiyun #define MAX_AGG_PKT_NUM 256 /* Max tx ampdu coounts		 */
839*4882a593Smuzhiyun #endif
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	struct agg_pkt_info agg_pkt[MAX_AGG_PKT_NUM];
842*4882a593Smuzhiyun #endif
843*4882a593Smuzhiyun 
844*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK
845*4882a593Smuzhiyun 	int	ack_tx;
846*4882a593Smuzhiyun 	_mutex ack_tx_mutex;
847*4882a593Smuzhiyun 	struct submit_ctx ack_tx_ops;
848*4882a593Smuzhiyun 	u8 seq_no;
849*4882a593Smuzhiyun #ifdef CONFIG_REMOVE_DUP_TX_STATE
850*4882a593Smuzhiyun 	u8 retry_count;
851*4882a593Smuzhiyun #endif
852*4882a593Smuzhiyun #endif
853*4882a593Smuzhiyun 
854*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU
855*4882a593Smuzhiyun 	_timer amsdu_vo_timer;
856*4882a593Smuzhiyun 	u8 amsdu_vo_timeout;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	_timer amsdu_vi_timer;
859*4882a593Smuzhiyun 	u8 amsdu_vi_timeout;
860*4882a593Smuzhiyun 
861*4882a593Smuzhiyun 	_timer amsdu_be_timer;
862*4882a593Smuzhiyun 	u8 amsdu_be_timeout;
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	_timer amsdu_bk_timer;
865*4882a593Smuzhiyun 	u8 amsdu_bk_timeout;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 	u32 amsdu_debug_set_timer;
868*4882a593Smuzhiyun 	u32 amsdu_debug_timeout;
869*4882a593Smuzhiyun 	u32 amsdu_debug_coalesce_one;
870*4882a593Smuzhiyun 	u32 amsdu_debug_coalesce_two;
871*4882a593Smuzhiyun 
872*4882a593Smuzhiyun #endif
873*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP
874*4882a593Smuzhiyun 	BOOLEAN	 dump_txbd_desc;
875*4882a593Smuzhiyun #endif
876*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING
877*4882a593Smuzhiyun 	_timer tx_poll_timer;
878*4882a593Smuzhiyun #endif
879*4882a593Smuzhiyun #ifdef CONFIG_LAYER2_ROAMING
880*4882a593Smuzhiyun 	_queue	rpkt_queue;
881*4882a593Smuzhiyun #endif
882*4882a593Smuzhiyun 	_lock lock_sctx;
883*4882a593Smuzhiyun 
884*4882a593Smuzhiyun };
885*4882a593Smuzhiyun 
886*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe(struct xmit_priv *pxmitpriv,
887*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
888*4882a593Smuzhiyun #define rtw_alloc_cmdxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_RSVD)
889*4882a593Smuzhiyun #if defined(CONFIG_RTL8192E) && defined(CONFIG_PCI_HCI)
890*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192ee(struct xmit_priv *pxmitpriv,
891*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
892*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192ee(p, CMDBUF_BEACON)
893*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822B) && defined(CONFIG_PCI_HCI)
894*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822be(struct xmit_priv *pxmitpriv,
895*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
896*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822be(p, CMDBUF_BEACON)
897*4882a593Smuzhiyun #elif defined(CONFIG_RTL8822C) && defined(CONFIG_PCI_HCI)
898*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8822ce(struct xmit_priv *pxmitpriv,
899*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
900*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8822ce(p, CMDBUF_BEACON)
901*4882a593Smuzhiyun #elif defined(CONFIG_RTL8821C) && defined(CONFIG_PCI_HCI)
902*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8821ce(struct xmit_priv *pxmitpriv,
903*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
904*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8821ce(p, CMDBUF_BEACON)
905*4882a593Smuzhiyun #elif defined(CONFIG_RTL8192F) && defined(CONFIG_PCI_HCI)
906*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8192fe(struct xmit_priv *pxmitpriv,
907*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
908*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8192fe(p, CMDBUF_BEACON)
909*4882a593Smuzhiyun #elif defined(CONFIG_RTL8812A) && defined(CONFIG_PCI_HCI)
910*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8812ae(struct xmit_priv *pxmitpriv,
911*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
912*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8812ae(p, CMDBUF_BEACON)
913*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723D) && defined(CONFIG_PCI_HCI)
914*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723de(struct xmit_priv *pxmitpriv,
915*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
916*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723de(p, CMDBUF_BEACON)
917*4882a593Smuzhiyun #elif defined(CONFIG_RTL8723B) && defined(CONFIG_PCI_HCI)
918*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8723be(struct xmit_priv *pxmitpriv,
919*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
920*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8723be(p, CMDBUF_BEACON)
921*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814A) && defined(CONFIG_PCI_HCI)
922*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814ae(struct xmit_priv *pxmitpriv,
923*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
924*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814ae(p, CMDBUF_BEACON)
925*4882a593Smuzhiyun #elif defined(CONFIG_RTL8814B) && defined(CONFIG_PCI_HCI)
926*4882a593Smuzhiyun extern struct xmit_frame *__rtw_alloc_cmdxmitframe_8814be(struct xmit_priv *pxmitpriv,
927*4882a593Smuzhiyun 		enum cmdbuf_type buf_type);
928*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe_8814be(p, CMDBUF_BEACON)
929*4882a593Smuzhiyun #else
930*4882a593Smuzhiyun #define rtw_alloc_bcnxmitframe(p) __rtw_alloc_cmdxmitframe(p, CMDBUF_BEACON)
931*4882a593Smuzhiyun #endif
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv);
934*4882a593Smuzhiyun extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv);
937*4882a593Smuzhiyun extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
938*4882a593Smuzhiyun 
939*4882a593Smuzhiyun void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz);
940*4882a593Smuzhiyun extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len);
941*4882a593Smuzhiyun 
942*4882a593Smuzhiyun extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib);
943*4882a593Smuzhiyun extern s32 rtw_put_snap(u8 *data, u16 h_proto);
944*4882a593Smuzhiyun 
945*4882a593Smuzhiyun extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv, u16 os_qid);
946*4882a593Smuzhiyun struct xmit_frame *rtw_alloc_xmitframe_ext(struct xmit_priv *pxmitpriv);
947*4882a593Smuzhiyun struct xmit_frame *rtw_alloc_xmitframe_once(struct xmit_priv *pxmitpriv);
948*4882a593Smuzhiyun extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe);
949*4882a593Smuzhiyun extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue);
950*4882a593Smuzhiyun struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac);
951*4882a593Smuzhiyun extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
954*4882a593Smuzhiyun void rtw_free_mgmt_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *mgmt_queue);
955*4882a593Smuzhiyun u8 rtw_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
956*4882a593Smuzhiyun struct xmit_frame *rtw_dequeue_mgmt_xframe(struct xmit_priv *pxmitpriv);
957*4882a593Smuzhiyun #endif /* CONFIG_RTW_MGMT_QUEUE */
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun extern struct xmit_frame *rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry);
960*4882a593Smuzhiyun 
961*4882a593Smuzhiyun extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe);
962*4882a593Smuzhiyun extern u32 rtw_calculate_wlan_pkt_size_by_attribue(struct pkt_attrib *pattrib);
963*4882a593Smuzhiyun #define rtw_wlan_pkt_size(f) rtw_calculate_wlan_pkt_size_by_attribue(&f->attrib)
964*4882a593Smuzhiyun extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
965*4882a593Smuzhiyun #if defined(CONFIG_IEEE80211W) || defined(CONFIG_RTW_MESH)
966*4882a593Smuzhiyun extern s32 rtw_mgmt_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe);
967*4882a593Smuzhiyun #endif
968*4882a593Smuzhiyun #ifdef CONFIG_TDLS
969*4882a593Smuzhiyun extern struct tdls_txmgmt *ptxmgmt;
970*4882a593Smuzhiyun s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, struct tdls_txmgmt *ptxmgmt);
971*4882a593Smuzhiyun s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib);
972*4882a593Smuzhiyun #endif
973*4882a593Smuzhiyun s32 _rtw_init_hw_txqueue(struct hw_txqueue *phw_txqueue, u8 ac_tag);
974*4882a593Smuzhiyun void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv);
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 
977*4882a593Smuzhiyun s32 rtw_txframes_pending(_adapter *padapter);
978*4882a593Smuzhiyun s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib);
979*4882a593Smuzhiyun void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry);
980*4882a593Smuzhiyun 
981*4882a593Smuzhiyun 
982*4882a593Smuzhiyun s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter);
983*4882a593Smuzhiyun void _rtw_free_xmit_priv(struct xmit_priv *pxmitpriv);
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun void rtw_alloc_hwxmits(_adapter *padapter);
987*4882a593Smuzhiyun void rtw_free_hwxmits(_adapter *padapter);
988*4882a593Smuzhiyun #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 24))
989*4882a593Smuzhiyun s32 rtw_monitor_xmit_entry(struct sk_buff *skb, struct net_device *ndev);
990*4882a593Smuzhiyun #endif
991*4882a593Smuzhiyun void rtw_xmit_dequeue_callback(_workitem *work);
992*4882a593Smuzhiyun void rtw_xmit_queue_set(struct sta_info *sta);
993*4882a593Smuzhiyun void rtw_xmit_queue_clear(struct sta_info *sta);
994*4882a593Smuzhiyun s32 rtw_xmit_posthandle(_adapter *padapter, struct xmit_frame *pxmitframe, _pkt *pkt);
995*4882a593Smuzhiyun s32 rtw_xmit(_adapter *padapter, _pkt **pkt, u16 os_qid);
996*4882a593Smuzhiyun bool xmitframe_hiq_filter(struct xmit_frame *xmitframe);
997*4882a593Smuzhiyun #if defined(CONFIG_AP_MODE) || defined(CONFIG_TDLS)
998*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
999*4882a593Smuzhiyun u8 mgmt_xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
1000*4882a593Smuzhiyun #endif
1001*4882a593Smuzhiyun sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe);
1002*4882a593Smuzhiyun void stop_sta_xmit(_adapter *padapter, struct sta_info *psta);
1003*4882a593Smuzhiyun void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta, u8 dequeue_type);
1004*4882a593Smuzhiyun void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta);
1005*4882a593Smuzhiyun #endif
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun u8 rtw_get_tx_bw_mode(_adapter *adapter, struct sta_info *sta);
1008*4882a593Smuzhiyun 
1009*4882a593Smuzhiyun void rtw_update_tx_rate_bmp(struct dvobj_priv *dvobj);
1010*4882a593Smuzhiyun u8 rtw_get_tx_bw_bmp_of_ht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
1011*4882a593Smuzhiyun u8 rtw_get_tx_bw_bmp_of_vht_rate(struct dvobj_priv *dvobj, u8 rate, u8 max_bw);
1012*4882a593Smuzhiyun s16 rtw_adapter_get_oper_txpwr_max_mbm(_adapter *adapter, bool eirp);
1013*4882a593Smuzhiyun s16 rtw_rfctl_get_oper_txpwr_max_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, u8 ifbmp_mod, u8 if_op, bool eirp);
1014*4882a593Smuzhiyun s16 rtw_get_oper_txpwr_max_mbm(struct dvobj_priv *dvobj, bool erip);
1015*4882a593Smuzhiyun s16 rtw_rfctl_get_reg_max_txpwr_mbm(struct rf_ctl_t *rfctl, u8 ch, u8 bw, u8 offset, bool eirp);
1016*4882a593Smuzhiyun 
1017*4882a593Smuzhiyun u8 query_ra_short_GI(struct sta_info *psta, u8 bw);
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun u8	qos_acm(u8 acm_mask, u8 priority);
1020*4882a593Smuzhiyun 
1021*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE
1022*4882a593Smuzhiyun void	enqueue_pending_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
1023*4882a593Smuzhiyun void enqueue_pending_xmitbuf_to_head(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
1024*4882a593Smuzhiyun struct xmit_buf	*dequeue_pending_xmitbuf(struct xmit_priv *pxmitpriv);
1025*4882a593Smuzhiyun struct xmit_buf	*select_and_dequeue_pending_xmitbuf(_adapter *padapter);
1026*4882a593Smuzhiyun sint	check_pending_xmitbuf(struct xmit_priv *pxmitpriv);
1027*4882a593Smuzhiyun thread_return	rtw_xmit_thread(thread_context context);
1028*4882a593Smuzhiyun #endif
1029*4882a593Smuzhiyun 
1030*4882a593Smuzhiyun #ifdef CONFIG_TX_AMSDU
1031*4882a593Smuzhiyun extern void rtw_amsdu_vo_timeout_handler(void *FunctionContext);
1032*4882a593Smuzhiyun extern void rtw_amsdu_vi_timeout_handler(void *FunctionContext);
1033*4882a593Smuzhiyun extern void rtw_amsdu_be_timeout_handler(void *FunctionContext);
1034*4882a593Smuzhiyun extern void rtw_amsdu_bk_timeout_handler(void *FunctionContext);
1035*4882a593Smuzhiyun 
1036*4882a593Smuzhiyun extern u8 rtw_amsdu_get_timer_status(_adapter *padapter, u8 priority);
1037*4882a593Smuzhiyun extern void rtw_amsdu_set_timer_status(_adapter *padapter, u8 priority, u8 status);
1038*4882a593Smuzhiyun extern void rtw_amsdu_set_timer(_adapter *padapter, u8 priority);
1039*4882a593Smuzhiyun extern void rtw_amsdu_cancel_timer(_adapter *padapter, u8 priority);
1040*4882a593Smuzhiyun 
1041*4882a593Smuzhiyun extern s32 rtw_xmitframe_coalesce_amsdu(_adapter *padapter, struct xmit_frame *pxmitframe, struct xmit_frame *pxmitframe_queue);
1042*4882a593Smuzhiyun extern s32 check_amsdu(struct xmit_frame *pxmitframe);
1043*4882a593Smuzhiyun extern s32 check_amsdu_tx_support(_adapter *padapter);
1044*4882a593Smuzhiyun extern struct xmit_frame *rtw_get_xframe(struct xmit_priv *pxmitpriv, int *num_frame);
1045*4882a593Smuzhiyun #endif
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun #ifdef DBG_TXBD_DESC_DUMP
1048*4882a593Smuzhiyun void rtw_tx_desc_backup(_adapter *padapter, struct xmit_frame *pxmitframe, u8 desc_size, u8 hwq);
1049*4882a593Smuzhiyun void rtw_tx_desc_backup_reset(void);
1050*4882a593Smuzhiyun u8 rtw_get_tx_desc_backup(_adapter *padapter, u8 hwq, struct rtw_tx_desc_backup **pbak);
1051*4882a593Smuzhiyun #endif
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING
1054*4882a593Smuzhiyun void rtw_tx_poll_init(_adapter *padapter);
1055*4882a593Smuzhiyun void rtw_tx_poll_timeout_handler(void *FunctionContext);
1056*4882a593Smuzhiyun void rtw_tx_poll_timer_set(_adapter *padapter, u32 delay);
1057*4882a593Smuzhiyun void rtw_tx_poll_timer_cancel(_adapter *padapter);
1058*4882a593Smuzhiyun #endif
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun u32	rtw_get_ff_hwaddr(struct xmit_frame	*pxmitframe);
1061*4882a593Smuzhiyun 
1062*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK
1063*4882a593Smuzhiyun int rtw_ack_tx_wait(struct xmit_priv *pxmitpriv, u32 timeout_ms);
1064*4882a593Smuzhiyun void rtw_ack_tx_done(struct xmit_priv *pxmitpriv, int status);
1065*4882a593Smuzhiyun #endif /* CONFIG_XMIT_ACK */
1066*4882a593Smuzhiyun 
1067*4882a593Smuzhiyun enum XMIT_BLOCK_REASON {
1068*4882a593Smuzhiyun 	XMIT_BLOCK_NONE = 0,
1069*4882a593Smuzhiyun 	XMIT_BLOCK_REDLMEM = BIT0, /*LPS-PG*/
1070*4882a593Smuzhiyun 	XMIT_BLOCK_SUSPEND = BIT1, /*WOW*/
1071*4882a593Smuzhiyun 	XMIT_BLOCK_MAX = 0xFF,
1072*4882a593Smuzhiyun };
1073*4882a593Smuzhiyun void rtw_init_xmit_block(_adapter *padapter);
1074*4882a593Smuzhiyun void rtw_deinit_xmit_block(_adapter *padapter);
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun #ifdef DBG_XMIT_BLOCK
1077*4882a593Smuzhiyun void dump_xmit_block(void *sel, _adapter *padapter);
1078*4882a593Smuzhiyun #endif
1079*4882a593Smuzhiyun void rtw_set_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
1080*4882a593Smuzhiyun void rtw_clr_xmit_block(_adapter *padapter, enum XMIT_BLOCK_REASON reason);
1081*4882a593Smuzhiyun bool rtw_is_xmit_blocked(_adapter *padapter);
1082*4882a593Smuzhiyun void rtw_hci_flush(_adapter *padapter);
1083*4882a593Smuzhiyun 
1084*4882a593Smuzhiyun /* include after declaring struct xmit_buf, in order to avoid warning */
1085*4882a593Smuzhiyun #include <xmit_osdep.h>
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun #endif /* _RTL871X_XMIT_H_ */
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