1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __RTW_PWRCTRL_H_
16*4882a593Smuzhiyun #define __RTW_PWRCTRL_H_
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define FW_PWR0 0
20*4882a593Smuzhiyun #define FW_PWR1 1
21*4882a593Smuzhiyun #define FW_PWR2 2
22*4882a593Smuzhiyun #define FW_PWR3 3
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define HW_PWR0 7
26*4882a593Smuzhiyun #define HW_PWR1 6
27*4882a593Smuzhiyun #define HW_PWR2 2
28*4882a593Smuzhiyun #define HW_PWR3 0
29*4882a593Smuzhiyun #define HW_PWR4 8
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define FW_PWRMSK 0x7
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define XMIT_ALIVE BIT(0)
35*4882a593Smuzhiyun #define RECV_ALIVE BIT(1)
36*4882a593Smuzhiyun #define CMD_ALIVE BIT(2)
37*4882a593Smuzhiyun #define EVT_ALIVE BIT(3)
38*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
39*4882a593Smuzhiyun #define BTCOEX_ALIVE BIT(4)
40*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
41*4882a593Smuzhiyun #define LPS_ALIVE BIT(5)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
44*4882a593Smuzhiyun #ifdef CONFIG_PLATFORM_ANDROID_INTEL_X86
45*4882a593Smuzhiyun /* TCP/ICMP/UDP multicast with specific IP addr */
46*4882a593Smuzhiyun #define DEFAULT_PATTERN_NUM 4
47*4882a593Smuzhiyun #else
48*4882a593Smuzhiyun /* TCP/ICMP */
49*4882a593Smuzhiyun #define DEFAULT_PATTERN_NUM 3
50*4882a593Smuzhiyun #endif
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_HW_CAM /* Frame Mask Cam number for pattern match */
53*4882a593Smuzhiyun #define MAX_WKFM_CAM_NUM 12
54*4882a593Smuzhiyun #else
55*4882a593Smuzhiyun #define MAX_WKFM_CAM_NUM 16
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define MAX_WKFM_SIZE 16 /* (16 bytes for WKFM bit mask, 16*8 = 128 bits) */
59*4882a593Smuzhiyun #define MAX_WKFM_PATTERN_SIZE 128
60*4882a593Smuzhiyun #define MAX_IN_PATTERN_SIZE 512
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /*
63*4882a593Smuzhiyun * MAX_WKFM_PATTERN_STR_LEN : the max. length of wow pattern string
64*4882a593Smuzhiyun * e.g. echo 00:01:02:...:7f > /proc/net/rtl88x2bu/wlan0/wow_pattern_info
65*4882a593Smuzhiyun * - each byte of pattern is represented as 2-bytes ascii : MAX_WKFM_PATTERN_SIZE * 2
66*4882a593Smuzhiyun * - the number of common ':' in pattern string : MAX_WKFM_PATTERN_SIZE - 1
67*4882a593Smuzhiyun * - 1 byte '\n'(0x0a) is generated at the end when we use echo command
68*4882a593Smuzhiyun * so total max. length is (MAX_WKFM_PATTERN_SIZE * 3)
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun #define MAX_WKFM_PATTERN_STR_LEN (MAX_WKFM_PATTERN_SIZE * 3)
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define WKFMCAM_ADDR_NUM 6
73*4882a593Smuzhiyun #define WKFMCAM_SIZE 24 /* each entry need 6*4 bytes */
74*4882a593Smuzhiyun enum pattern_type {
75*4882a593Smuzhiyun PATTERN_BROADCAST = 0,
76*4882a593Smuzhiyun PATTERN_MULTICAST,
77*4882a593Smuzhiyun PATTERN_UNICAST,
78*4882a593Smuzhiyun PATTERN_VALID,
79*4882a593Smuzhiyun PATTERN_INVALID,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun typedef struct rtl_priv_pattern {
83*4882a593Smuzhiyun int len;
84*4882a593Smuzhiyun char content[MAX_WKFM_PATTERN_SIZE];
85*4882a593Smuzhiyun char mask[MAX_WKFM_SIZE];
86*4882a593Smuzhiyun } rtl_priv_pattern_t;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun enum Power_Mgnt {
91*4882a593Smuzhiyun PS_MODE_ACTIVE = 0 ,
92*4882a593Smuzhiyun PS_MODE_MIN ,
93*4882a593Smuzhiyun PS_MODE_MAX ,
94*4882a593Smuzhiyun PS_MODE_DTIM , /* PS_MODE_SELF_DEFINED */
95*4882a593Smuzhiyun PS_MODE_VOIP ,
96*4882a593Smuzhiyun PS_MODE_UAPSD_WMM ,
97*4882a593Smuzhiyun PS_MODE_UAPSD ,
98*4882a593Smuzhiyun PS_MODE_IBSS ,
99*4882a593Smuzhiyun PS_MODE_WWLAN ,
100*4882a593Smuzhiyun PM_Radio_Off ,
101*4882a593Smuzhiyun PM_Card_Disable ,
102*4882a593Smuzhiyun PS_MODE_NUM,
103*4882a593Smuzhiyun };
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun enum lps_level {
106*4882a593Smuzhiyun LPS_NORMAL = 0,
107*4882a593Smuzhiyun LPS_LCLK,
108*4882a593Smuzhiyun LPS_PG,
109*4882a593Smuzhiyun LPS_LEVEL_MAX,
110*4882a593Smuzhiyun };
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun #ifdef CONFIG_PNO_SUPPORT
113*4882a593Smuzhiyun #define MAX_PNO_LIST_COUNT 16
114*4882a593Smuzhiyun #define MAX_SCAN_LIST_COUNT 14 /* 2.4G only */
115*4882a593Smuzhiyun #define MAX_HIDDEN_AP 8 /* 8 hidden AP */
116*4882a593Smuzhiyun #endif
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun BIT[2:0] = HW state
120*4882a593Smuzhiyun BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state
121*4882a593Smuzhiyun BIT[4] = sub-state
122*4882a593Smuzhiyun */
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define PS_DPS BIT(0)
125*4882a593Smuzhiyun #define PS_LCLK (PS_DPS)
126*4882a593Smuzhiyun #define PS_RF_OFF BIT(1)
127*4882a593Smuzhiyun #define PS_ALL_ON BIT(2)
128*4882a593Smuzhiyun #define PS_ST_ACTIVE BIT(3)
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun #define PS_ISR_ENABLE BIT(4)
131*4882a593Smuzhiyun #define PS_IMR_ENABLE BIT(5)
132*4882a593Smuzhiyun #define PS_ACK BIT(6)
133*4882a593Smuzhiyun #define PS_TOGGLE BIT(7)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define PS_STATE_MASK (0x0F)
136*4882a593Smuzhiyun #define PS_STATE_HW_MASK (0x07)
137*4882a593Smuzhiyun #define PS_SEQ_MASK (0xc0)
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #define PS_STATE(x) (PS_STATE_MASK & (x))
140*4882a593Smuzhiyun #define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x))
141*4882a593Smuzhiyun #define PS_SEQ(x) (PS_SEQ_MASK & (x))
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define PS_STATE_S0 (PS_DPS)
144*4882a593Smuzhiyun #define PS_STATE_S1 (PS_LCLK)
145*4882a593Smuzhiyun #define PS_STATE_S2 (PS_RF_OFF)
146*4882a593Smuzhiyun #define PS_STATE_S3 (PS_ALL_ON)
147*4882a593Smuzhiyun #define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON))
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON))
151*4882a593Smuzhiyun #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
152*4882a593Smuzhiyun #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun struct reportpwrstate_parm {
156*4882a593Smuzhiyun unsigned char mode;
157*4882a593Smuzhiyun unsigned char state; /* the CPWM value */
158*4882a593Smuzhiyun unsigned short rsvd;
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun typedef _sema _pwrlock;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun
_init_pwrlock(_pwrlock * plock)165*4882a593Smuzhiyun __inline static void _init_pwrlock(_pwrlock *plock)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun _rtw_init_sema(plock, 1);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
_free_pwrlock(_pwrlock * plock)170*4882a593Smuzhiyun __inline static void _free_pwrlock(_pwrlock *plock)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun _rtw_free_sema(plock);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun
_enter_pwrlock(_pwrlock * plock)176*4882a593Smuzhiyun __inline static void _enter_pwrlock(_pwrlock *plock)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun _rtw_down_sema(plock);
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun
_exit_pwrlock(_pwrlock * plock)182*4882a593Smuzhiyun __inline static void _exit_pwrlock(_pwrlock *plock)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun _rtw_up_sema(plock);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #define LPS_DELAY_MS 1000 /* 1 sec */
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun #define EXE_PWR_NONE 0x01
190*4882a593Smuzhiyun #define EXE_PWR_IPS 0x02
191*4882a593Smuzhiyun #define EXE_PWR_LPS 0x04
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* RF state. */
194*4882a593Smuzhiyun typedef enum _rt_rf_power_state {
195*4882a593Smuzhiyun rf_on, /* RF is on after RFSleep or RFOff */
196*4882a593Smuzhiyun rf_sleep, /* 802.11 Power Save mode */
197*4882a593Smuzhiyun rf_off, /* HW/SW Radio OFF or Inactive Power Save */
198*4882a593Smuzhiyun /* =====Add the new RF state above this line===== */
199*4882a593Smuzhiyun rf_max
200*4882a593Smuzhiyun } rt_rf_power_state;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun /* ASPM OSC Control bit, added by Roger, 2013.03.29. */
203*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_IGNORE 0 /* PCI ASPM ignore OSC control in default */
204*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_ENABLE BIT0 /* PCI ASPM controlled by OS according to ACPI Spec 5.0 */
205*4882a593Smuzhiyun #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun enum _PS_BBRegBackup_ {
209*4882a593Smuzhiyun PSBBREG_RF0 = 0,
210*4882a593Smuzhiyun PSBBREG_RF1,
211*4882a593Smuzhiyun PSBBREG_RF2,
212*4882a593Smuzhiyun PSBBREG_AFE0,
213*4882a593Smuzhiyun PSBBREG_TOTALCNT
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun enum { /* for ips_mode */
217*4882a593Smuzhiyun IPS_NONE = 0,
218*4882a593Smuzhiyun IPS_NORMAL,
219*4882a593Smuzhiyun IPS_LEVEL_2,
220*4882a593Smuzhiyun IPS_NUM
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun /* Design for pwrctrl_priv.ips_deny, 32 bits for 32 reasons at most */
224*4882a593Smuzhiyun typedef enum _PS_DENY_REASON {
225*4882a593Smuzhiyun PS_DENY_DRV_INITIAL = 0,
226*4882a593Smuzhiyun PS_DENY_SCAN,
227*4882a593Smuzhiyun PS_DENY_JOIN,
228*4882a593Smuzhiyun PS_DENY_DISCONNECT,
229*4882a593Smuzhiyun PS_DENY_SUSPEND,
230*4882a593Smuzhiyun PS_DENY_IOCTL,
231*4882a593Smuzhiyun PS_DENY_MGNT_TX,
232*4882a593Smuzhiyun PS_DENY_MONITOR_MODE,
233*4882a593Smuzhiyun PS_DENY_BEAMFORMING, /* Beamforming */
234*4882a593Smuzhiyun PS_DENY_DRV_REMOVE = 30,
235*4882a593Smuzhiyun PS_DENY_OTHERS = 31
236*4882a593Smuzhiyun } PS_DENY_REASON;
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun #ifdef CONFIG_WAR_OFFLOAD
239*4882a593Smuzhiyun /* only support mDNS V4/V6 rsp now */
240*4882a593Smuzhiyun enum {
241*4882a593Smuzhiyun WAR_ARP_RSP_EN = 0x0000001,
242*4882a593Smuzhiyun WAR_ICMPV6_NS_RSP_EN = 0x00000002,
243*4882a593Smuzhiyun WAR_ICMPV4_ECHO_RSP_EN = 0x00000004,
244*4882a593Smuzhiyun WAR_ICMPV6_ECHO_RSP_EN = 0x00000008,
245*4882a593Smuzhiyun WAR_NETBIOS_RSP_EN = 0x00000010,
246*4882a593Smuzhiyun WAR_LLMNR_V4_RSP_EN = 0x00000020,
247*4882a593Smuzhiyun WAR_LLMNR_V6_RSP_EN = 0x00000040,
248*4882a593Smuzhiyun WAR_SNMP_V4_RSP_EN = 0x00000080,
249*4882a593Smuzhiyun WAR_SNMP_V6_RSP_EN = 0x00000100,
250*4882a593Smuzhiyun WAR_SNMP_V4_WAKEUP_EN = 0x00000200,
251*4882a593Smuzhiyun WAR_SNMP_V6_WAKEUP_EN = 0x00000400,
252*4882a593Smuzhiyun WAR_SSDP_V4_WAKEUP_EN = 0x00000800,
253*4882a593Smuzhiyun WAR_SSDP_V6_WAKEUP_EN = 0x00001000,
254*4882a593Smuzhiyun WAR_WSD_V4_WAKEUP_EN = 0x00002000,
255*4882a593Smuzhiyun WAR_WSD_V6_WAKEUP_EN = 0x00004000,
256*4882a593Smuzhiyun WAR_SLP_V4_WAKEUP_EN = 0x00008000,
257*4882a593Smuzhiyun WAR_SLP_V6_WAKEUP_EN = 0x00010000,
258*4882a593Smuzhiyun WAR_MDNS_V4_RSP_EN = 0x00020000,
259*4882a593Smuzhiyun WAR_MDNS_V6_RSP_EN = 0x00040000,
260*4882a593Smuzhiyun WAR_DESIGNATED_MAC_EN = 0x00080000,
261*4882a593Smuzhiyun WAR_LLTD_WAKEUP_EN = 0x00100000,
262*4882a593Smuzhiyun WAR_ARP_WAKEUP_EN = 0x00200000,
263*4882a593Smuzhiyun WAR_MAGIC_WAKEUP_EN = 0x00400000,
264*4882a593Smuzhiyun WAR_MDNS_V4_WAKEUP_EN = 0x000800000,
265*4882a593Smuzhiyun WAR_MDNS_V6_WAKEUP_EN = 0x001000000
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun #endif /* CONFIG_WAR_OFFLOAD */
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun #ifdef CONFIG_PNO_SUPPORT
271*4882a593Smuzhiyun typedef struct pno_nlo_info {
272*4882a593Smuzhiyun u32 fast_scan_period; /* Fast scan period */
273*4882a593Smuzhiyun u8 ssid_num; /* number of entry */
274*4882a593Smuzhiyun u8 hidden_ssid_num;
275*4882a593Smuzhiyun u32 slow_scan_period; /* slow scan period */
276*4882a593Smuzhiyun u32 fast_scan_iterations; /* Fast scan iterations */
277*4882a593Smuzhiyun u8 ssid_length[MAX_PNO_LIST_COUNT]; /* SSID Length Array */
278*4882a593Smuzhiyun u8 ssid_cipher_info[MAX_PNO_LIST_COUNT]; /* Cipher information for security */
279*4882a593Smuzhiyun u8 ssid_channel_info[MAX_PNO_LIST_COUNT]; /* channel information */
280*4882a593Smuzhiyun u8 loc_probe_req[MAX_HIDDEN_AP]; /* loc_probeReq */
281*4882a593Smuzhiyun } pno_nlo_info_t;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun typedef struct pno_ssid {
284*4882a593Smuzhiyun u32 SSID_len;
285*4882a593Smuzhiyun u8 SSID[WLAN_SSID_MAXLEN];
286*4882a593Smuzhiyun } pno_ssid_t;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun typedef struct pno_ssid_list {
289*4882a593Smuzhiyun pno_ssid_t node[MAX_PNO_LIST_COUNT];
290*4882a593Smuzhiyun } pno_ssid_list_t;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun typedef struct pno_scan_channel_info {
293*4882a593Smuzhiyun u8 channel;
294*4882a593Smuzhiyun u8 tx_power;
295*4882a593Smuzhiyun u8 timeout;
296*4882a593Smuzhiyun u8 active; /* set 1 means active scan, or pasivite scan. */
297*4882a593Smuzhiyun } pno_scan_channel_info_t;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun #ifndef RTW_HALMAC
300*4882a593Smuzhiyun typedef struct pno_scan_info {
301*4882a593Smuzhiyun u8 enableRFE; /* Enable RFE */
302*4882a593Smuzhiyun u8 period_scan_time; /* exclusive with fast_scan_period and slow_scan_period */
303*4882a593Smuzhiyun u8 periodScan; /* exclusive with fast_scan_period and slow_scan_period */
304*4882a593Smuzhiyun u8 orig_80_offset; /* original channel 80 offset */
305*4882a593Smuzhiyun u8 orig_40_offset; /* original channel 40 offset */
306*4882a593Smuzhiyun u8 orig_bw; /* original bandwidth */
307*4882a593Smuzhiyun u8 orig_ch; /* original channel */
308*4882a593Smuzhiyun u8 channel_num; /* number of channel */
309*4882a593Smuzhiyun u64 rfe_type; /* rfe_type && 0x00000000000000ff */
310*4882a593Smuzhiyun pno_scan_channel_info_t ssid_channel_info[MAX_SCAN_LIST_COUNT];
311*4882a593Smuzhiyun } pno_scan_info_t;
312*4882a593Smuzhiyun #endif
313*4882a593Smuzhiyun #endif /* CONFIG_PNO_SUPPORT */
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun #ifdef CONFIG_LPS_POFF
316*4882a593Smuzhiyun /* Driver context for LPS 32K Close IO Power */
317*4882a593Smuzhiyun typedef struct lps_poff_info {
318*4882a593Smuzhiyun bool bEn;
319*4882a593Smuzhiyun u8 *pStaticFile;
320*4882a593Smuzhiyun u8 *pDynamicFile;
321*4882a593Smuzhiyun u32 ConfFileOffset;
322*4882a593Smuzhiyun u32 tx_bndy_static;
323*4882a593Smuzhiyun u32 tx_bndy_dynamic;
324*4882a593Smuzhiyun u16 ConfLenForPTK;
325*4882a593Smuzhiyun u16 ConfLenForGTK;
326*4882a593Smuzhiyun ATOMIC_T bEnterPOFF;
327*4882a593Smuzhiyun ATOMIC_T bTxBoundInProgress;
328*4882a593Smuzhiyun ATOMIC_T bSetPOFFParm;
329*4882a593Smuzhiyun } lps_poff_info_t;
330*4882a593Smuzhiyun #endif /*CONFIG_LPS_POFF*/
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun struct aoac_report {
333*4882a593Smuzhiyun u8 iv[8];
334*4882a593Smuzhiyun u8 replay_counter_eapol_key[8];
335*4882a593Smuzhiyun u8 group_key[32];
336*4882a593Smuzhiyun u8 key_index;
337*4882a593Smuzhiyun u8 security_type;
338*4882a593Smuzhiyun u8 wow_pattern_idx;
339*4882a593Smuzhiyun u8 version_info;
340*4882a593Smuzhiyun u8 rekey_ok:1;
341*4882a593Smuzhiyun u8 dummy:7;
342*4882a593Smuzhiyun u8 reserved[3];
343*4882a593Smuzhiyun u8 rxptk_iv[8];
344*4882a593Smuzhiyun u8 rxgtk_iv[4][8];
345*4882a593Smuzhiyun };
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun #ifdef CONFIG_WAR_OFFLOAD
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun struct war_ipv4_fmt {
350*4882a593Smuzhiyun u32 ip_addr[4];
351*4882a593Smuzhiyun u32 ip_subnet[4];
352*4882a593Smuzhiyun u32 ip_gateway[4];
353*4882a593Smuzhiyun };
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun struct war_ipv6_fmt {
356*4882a593Smuzhiyun u8 ipv6_addr[8][16];
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun #if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
360*4882a593Smuzhiyun /* limitation of mDNS parameter : length and number */
361*4882a593Smuzhiyun #define MAX_MDNS_SERVICE_NAME_LEN 15
362*4882a593Smuzhiyun #define MAX_MDNS_TRANS_LEN 4 /* _tcp or _udp */
363*4882a593Smuzhiyun #define MAX_MDNS_DOMAIN_LEN 5 /* local only for mdns */
364*4882a593Smuzhiyun #define MAX_MDNS_MACHINE_NAME_LEN (63+1) /* +1 for the length byte used by the DNS format */
365*4882a593Smuzhiyun #define MAX_MDNS_TARGET_LEN 63
366*4882a593Smuzhiyun #define MAX_MDNS_DOMAIN_NAME_LEN 63
367*4882a593Smuzhiyun #define MAX_MDNS_TXT_LEN 1536
368*4882a593Smuzhiyun #define MAX_MDNS_TXT_SINGLE_LEN 255
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun #define MAX_MDNS_SERVICE_NUM 10
372*4882a593Smuzhiyun #define MAX_MDNS_TXT_NUM 8
373*4882a593Smuzhiyun #define MAX_MDNS_MACHINE_NAME_NUM 3
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun /* for monitor rsvd page using */
376*4882a593Smuzhiyun #define MAX_MDNS_PARA_SIZE 1700 // 14*128 = 1792
377*4882a593Smuzhiyun #define MAX_MDNS_TXT_TOTAL_SIZE 10*MAX_MDNS_TXT_LEN
378*4882a593Smuzhiyun #define MAX_MDNS_RSP_PKT_SIZE 760 // 6*128 = 768
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun #define RTW_MDNS_SRV_INFO(sname, sname_len, tname, tname_len, dname, dname_len, port0, port1, ttlv, tar, tar_len, idx) \
381*4882a593Smuzhiyun { .service=sname, .service_len=sname_len, .transport=tname, .transport_len=tname_len, \
382*4882a593Smuzhiyun .domain=dname , .domain_len=dname_len , .port[0]=port0, .port[1]=port1, .ttl=ttlv, \
383*4882a593Smuzhiyun .target=tar, .target_len=tar_len, .txt_rsp_idx=idx }
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun struct war_mdns_service_info {
387*4882a593Smuzhiyun u8 service[MAX_MDNS_SERVICE_NAME_LEN+1];
388*4882a593Smuzhiyun u8 service_len;
389*4882a593Smuzhiyun u8 transport[MAX_MDNS_TRANS_LEN+1];
390*4882a593Smuzhiyun u8 transport_len;
391*4882a593Smuzhiyun u8 domain[MAX_MDNS_DOMAIN_LEN+1];
392*4882a593Smuzhiyun u8 domain_len;
393*4882a593Smuzhiyun u8 port[2];
394*4882a593Smuzhiyun u32 ttl;
395*4882a593Smuzhiyun u8 target[MAX_MDNS_TARGET_LEN+1];
396*4882a593Smuzhiyun u8 target_len;
397*4882a593Smuzhiyun s8 txt_rsp_idx;
398*4882a593Smuzhiyun };
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun struct war_mdns_machine_name {
401*4882a593Smuzhiyun u8 name[MAX_MDNS_MACHINE_NAME_LEN];
402*4882a593Smuzhiyun u8 name_len;
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun struct war_mdns_txt_rsp {
406*4882a593Smuzhiyun u8 txt[MAX_MDNS_TXT_LEN];
407*4882a593Smuzhiyun u16 txt_len;
408*4882a593Smuzhiyun };
409*4882a593Smuzhiyun #endif
410*4882a593Smuzhiyun #endif /* CONFIG_WAR_OFFLOAD */
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun struct rsvd_page_cache_t;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun struct pwrctrl_priv {
416*4882a593Smuzhiyun _pwrlock lock;
417*4882a593Smuzhiyun _pwrlock check_32k_lock;
418*4882a593Smuzhiyun volatile u8 rpwm; /* requested power state for fw */
419*4882a593Smuzhiyun volatile u8 cpwm; /* fw current power state. updated when 1. read from HCPWM 2. driver lowers power level */
420*4882a593Smuzhiyun volatile u8 tog; /* toggling */
421*4882a593Smuzhiyun volatile u8 cpwm_tog; /* toggling */
422*4882a593Smuzhiyun u8 rpwm_retry;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun u8 pwr_mode;
425*4882a593Smuzhiyun u8 smart_ps;
426*4882a593Smuzhiyun u8 bcn_ant_mode;
427*4882a593Smuzhiyun u8 dtim;
428*4882a593Smuzhiyun #ifdef CONFIG_LPS_CHK_BY_TP
429*4882a593Smuzhiyun u8 lps_chk_by_tp;
430*4882a593Smuzhiyun u16 lps_tx_tp_th;/*Mbps*/
431*4882a593Smuzhiyun u16 lps_rx_tp_th;/*Mbps*/
432*4882a593Smuzhiyun u16 lps_bi_tp_th;/*Mbps*//*TRX TP*/
433*4882a593Smuzhiyun int lps_chk_cnt_th;
434*4882a593Smuzhiyun int lps_chk_cnt;
435*4882a593Smuzhiyun u32 lps_tx_pkts;
436*4882a593Smuzhiyun u32 lps_rx_pkts;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun #endif
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA
441*4882a593Smuzhiyun u8 wmm_smart_ps;
442*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun u32 alives;
445*4882a593Smuzhiyun _workitem cpwm_event;
446*4882a593Smuzhiyun _workitem dma_event; /*for handle un-synchronized tx dma*/
447*4882a593Smuzhiyun #ifdef CONFIG_LPS_RPWM_TIMER
448*4882a593Smuzhiyun u8 brpwmtimeout;
449*4882a593Smuzhiyun _workitem rpwmtimeoutwi;
450*4882a593Smuzhiyun _timer pwr_rpwm_timer;
451*4882a593Smuzhiyun #endif /* CONFIG_LPS_RPWM_TIMER */
452*4882a593Smuzhiyun u8 bpower_saving; /* for LPS/IPS */
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun u8 b_hw_radio_off;
455*4882a593Smuzhiyun u8 reg_rfoff;
456*4882a593Smuzhiyun u8 reg_pdnmode; /* powerdown mode */
457*4882a593Smuzhiyun u32 rfoff_reason;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun uint ips_enter_cnts;
460*4882a593Smuzhiyun uint ips_leave_cnts;
461*4882a593Smuzhiyun uint lps_enter_cnts;
462*4882a593Smuzhiyun uint lps_leave_cnts;
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun u8 ips_mode;
465*4882a593Smuzhiyun u8 ips_org_mode;
466*4882a593Smuzhiyun u8 ips_mode_req; /* used to accept the mode setting request, will update to ipsmode later */
467*4882a593Smuzhiyun uint bips_processing;
468*4882a593Smuzhiyun systime ips_deny_time; /* will deny IPS when system time is smaller than this */
469*4882a593Smuzhiyun u8 pre_ips_type;/* 0: default flow, 1: carddisbale flow */
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun /* ps_deny: if 0, power save is free to go; otherwise deny all kinds of power save. */
472*4882a593Smuzhiyun /* Use PS_DENY_REASON to decide reason. */
473*4882a593Smuzhiyun /* Don't access this variable directly without control function, */
474*4882a593Smuzhiyun /* and this variable should be protected by lock. */
475*4882a593Smuzhiyun u32 ps_deny;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun u8 fw_psmode_iface_id;
480*4882a593Smuzhiyun u8 bLeisurePs;
481*4882a593Smuzhiyun u8 LpsIdleCount;
482*4882a593Smuzhiyun u8 power_mgnt;
483*4882a593Smuzhiyun u8 org_power_mgnt;
484*4882a593Smuzhiyun u8 bFwCurrentInPSMode;
485*4882a593Smuzhiyun systime lps_deny_time; /* will deny LPS when system time is smaller than this */
486*4882a593Smuzhiyun s32 pnp_current_pwr_state;
487*4882a593Smuzhiyun u8 pnp_bstop_trx;
488*4882a593Smuzhiyun u8 bInSuspend;
489*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
490*4882a593Smuzhiyun u8 bAutoResume;
491*4882a593Smuzhiyun u8 autopm_cnt;
492*4882a593Smuzhiyun #endif
493*4882a593Smuzhiyun u8 bSupportRemoteWakeup;
494*4882a593Smuzhiyun u8 wowlan_wake_reason;
495*4882a593Smuzhiyun u8 wowlan_last_wake_reason;
496*4882a593Smuzhiyun u8 wowlan_ap_mode;
497*4882a593Smuzhiyun u8 wowlan_mode;
498*4882a593Smuzhiyun u8 wowlan_p2p_mode;
499*4882a593Smuzhiyun u8 wowlan_pno_enable;
500*4882a593Smuzhiyun u8 wowlan_in_resume;
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
503*4882a593Smuzhiyun u8 is_high_active;
504*4882a593Smuzhiyun u8 wowlan_gpio_index;
505*4882a593Smuzhiyun u8 wowlan_gpio_output_state;
506*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */
507*4882a593Smuzhiyun u8 hst2dev_high_active;
508*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
509*4882a593Smuzhiyun bool default_patterns_en;
510*4882a593Smuzhiyun #ifdef CONFIG_IPV6
511*4882a593Smuzhiyun u8 wowlan_ns_offload_en;
512*4882a593Smuzhiyun #endif /*CONFIG_IPV6*/
513*4882a593Smuzhiyun u8 wowlan_txpause_status;
514*4882a593Smuzhiyun u8 wowlan_pattern_idx;
515*4882a593Smuzhiyun u64 wowlan_fw_iv;
516*4882a593Smuzhiyun struct rtl_priv_pattern patterns[MAX_WKFM_CAM_NUM];
517*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_IN_TXFIFO
518*4882a593Smuzhiyun u8 pattern_rsvd_page_loc;
519*4882a593Smuzhiyun #endif
520*4882a593Smuzhiyun #ifdef CONFIG_PNO_SUPPORT
521*4882a593Smuzhiyun u8 pno_inited;
522*4882a593Smuzhiyun pno_nlo_info_t *pnlo_info;
523*4882a593Smuzhiyun #ifndef RTW_HALMAC
524*4882a593Smuzhiyun pno_scan_info_t *pscan_info;
525*4882a593Smuzhiyun #endif
526*4882a593Smuzhiyun pno_ssid_list_t *pno_ssid_list;
527*4882a593Smuzhiyun #endif /* CONFIG_PNO_SUPPORT */
528*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_HW_CAM
529*4882a593Smuzhiyun _mutex wowlan_pattern_cam_mutex;
530*4882a593Smuzhiyun #endif
531*4882a593Smuzhiyun u8 wowlan_aoac_rpt_loc;
532*4882a593Smuzhiyun struct aoac_report wowlan_aoac_rpt;
533*4882a593Smuzhiyun u8 wowlan_power_mgmt;
534*4882a593Smuzhiyun u8 wowlan_lps_level;
535*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
536*4882a593Smuzhiyun u8 wowlan_lps_1t1r;
537*4882a593Smuzhiyun #endif
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN
540*4882a593Smuzhiyun /*data 0,rsv page location*/
541*4882a593Smuzhiyun u8 wowlan_keep_alive_mode;
542*4882a593Smuzhiyun u8 keep_alive_pattern_loc;
543*4882a593Smuzhiyun /*data 1 ,cam id, rx udp packet*/
544*4882a593Smuzhiyun u8 wowlan_keep_alive_ack_index;
545*4882a593Smuzhiyun /*data 2 ,cam id, pattern match packet*/
546*4882a593Smuzhiyun u8 wowlan_wake_pattern_index;
547*4882a593Smuzhiyun /*data3,unit: TBTT*/
548*4882a593Smuzhiyun u16 wowlan_keep_alive_period;
549*4882a593Smuzhiyun /*data4,unit: TBTT*/
550*4882a593Smuzhiyun u8 wowlan_keep_alive_retry_interval;
551*4882a593Smuzhiyun /*data5*/
552*4882a593Smuzhiyun u8 wowlan_keep_alive_retry_counter;
553*4882a593Smuzhiyun /*from echo*/
554*4882a593Smuzhiyun u8 keep_alive_pattern[WLAN_MAX_KEEP_ALIVE_IE_LEN];
555*4882a593Smuzhiyun u32 keep_alive_pattern_len;
556*4882a593Smuzhiyun #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun #ifdef CONFIG_WAR_OFFLOAD
559*4882a593Smuzhiyun u8 wowlan_war_offload_mode;
560*4882a593Smuzhiyun u32 wowlan_war_offload_ctrl;
561*4882a593Smuzhiyun struct war_ipv4_fmt wowlan_war_offload_ipv4;
562*4882a593Smuzhiyun struct war_ipv6_fmt wowlan_war_offload_ipv6;
563*4882a593Smuzhiyun u8 wowlan_war_offload_mac[6];
564*4882a593Smuzhiyun #if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
565*4882a593Smuzhiyun struct war_mdns_machine_name wowlan_war_offload_mdns_mnane[MAX_MDNS_MACHINE_NAME_NUM];
566*4882a593Smuzhiyun struct war_mdns_service_info wowlan_war_offload_mdns_service[MAX_MDNS_SERVICE_NUM];
567*4882a593Smuzhiyun struct war_mdns_txt_rsp wowlan_war_offload_mdns_txt_rsp[MAX_MDNS_TXT_NUM];
568*4882a593Smuzhiyun u8 wowlan_war_offload_mdns_mnane_num;
569*4882a593Smuzhiyun u8 wowlan_war_offload_mdns_service_info_num;
570*4882a593Smuzhiyun u8 wowlan_war_offload_mdns_txt_rsp_num;
571*4882a593Smuzhiyun u8 wowlan_war_offload_mdns_domain_name[MAX_MDNS_DOMAIN_NAME_LEN+1];
572*4882a593Smuzhiyun u8 wowlan_war_offload_mdns_domain_name_len;
573*4882a593Smuzhiyun u32 wowlan_war_offload_mdns_para_cur_size;
574*4882a593Smuzhiyun u32 wowlan_war_offload_mdns_rsp_cur_size;
575*4882a593Smuzhiyun #endif /* CONFIG_OFFLOAD_MDNS_V4 || CONFIG_OFFLOAD_MDNS_V6 */
576*4882a593Smuzhiyun #endif /* CONFIG_WAR_OFFLOAD */
577*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
578*4882a593Smuzhiyun _timer pwr_state_check_timer;
579*4882a593Smuzhiyun int pwr_state_check_interval;
580*4882a593Smuzhiyun u8 pwr_state_check_cnts;
581*4882a593Smuzhiyun
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun rt_rf_power_state rf_pwrstate;/* cur power state, only for IPS */
584*4882a593Smuzhiyun /* rt_rf_power_state current_rfpwrstate; */
585*4882a593Smuzhiyun rt_rf_power_state change_rfpwrstate;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun u8 bHWPowerdown; /* power down mode selection. 0:radio off, 1:power down */
588*4882a593Smuzhiyun u8 bHWPwrPindetect; /* come from registrypriv.hwpwrp_detect. enable power down function. 0:disable, 1:enable */
589*4882a593Smuzhiyun u8 bkeepfwalive;
590*4882a593Smuzhiyun u8 brfoffbyhw;
591*4882a593Smuzhiyun unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun #ifdef CONFIG_RESUME_IN_WORKQUEUE
594*4882a593Smuzhiyun struct workqueue_struct *rtw_workqueue;
595*4882a593Smuzhiyun _workitem resume_work;
596*4882a593Smuzhiyun #endif
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun #ifdef CONFIG_HAS_EARLYSUSPEND
599*4882a593Smuzhiyun struct early_suspend early_suspend;
600*4882a593Smuzhiyun u8 do_late_resume;
601*4882a593Smuzhiyun #endif /* CONFIG_HAS_EARLYSUSPEND */
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun #ifdef CONFIG_ANDROID_POWER
604*4882a593Smuzhiyun android_early_suspend_t early_suspend;
605*4882a593Smuzhiyun u8 do_late_resume;
606*4882a593Smuzhiyun #endif
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun #ifdef CONFIG_LPS_POFF
609*4882a593Smuzhiyun lps_poff_info_t *plps_poff_info;
610*4882a593Smuzhiyun #endif
611*4882a593Smuzhiyun u8 lps_level_bk;
612*4882a593Smuzhiyun u8 lps_level; /*LPS_NORMAL,LPA_CG,LPS_PG*/
613*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
614*4882a593Smuzhiyun u8 lps_1t1r_bk;
615*4882a593Smuzhiyun u8 lps_1t1r;
616*4882a593Smuzhiyun #endif
617*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG
618*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_info;
619*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C
620*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_dpk_info;
621*4882a593Smuzhiyun struct rsvd_page_cache_t lpspg_iqk_info;
622*4882a593Smuzhiyun #endif
623*4882a593Smuzhiyun #endif
624*4882a593Smuzhiyun u8 current_lps_hw_port_id;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun #ifdef CONFIG_RTW_CFGVENDOR_LLSTATS
627*4882a593Smuzhiyun systime radio_on_start_time;
628*4882a593Smuzhiyun systime pwr_saving_start_time;
629*4882a593Smuzhiyun u32 pwr_saving_time;
630*4882a593Smuzhiyun u32 on_time;
631*4882a593Smuzhiyun u32 tx_time;
632*4882a593Smuzhiyun u32 rx_time;
633*4882a593Smuzhiyun #endif /* CONFIG_RTW_CFGVENDOR_LLSTATS */
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun #ifdef CONFIG_LPS_ACK
636*4882a593Smuzhiyun struct submit_ctx lps_ack_sctx;
637*4882a593Smuzhiyun s8 lps_ack_status;
638*4882a593Smuzhiyun _mutex lps_ack_mutex;
639*4882a593Smuzhiyun #endif /* CONFIG_LPS_ACK */
640*4882a593Smuzhiyun };
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun #define rtw_get_ips_mode_req(pwrctl) \
643*4882a593Smuzhiyun (pwrctl)->ips_mode_req
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun #define rtw_ips_mode_req(pwrctl, ips_mode) \
646*4882a593Smuzhiyun (pwrctl)->ips_mode_req = (ips_mode)
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun #define RTW_PWR_STATE_CHK_INTERVAL 2000
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun #define _rtw_set_pwr_state_check_timer(pwrctl, ms) \
651*4882a593Smuzhiyun do { \
652*4882a593Smuzhiyun /*RTW_INFO("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctl), (ms));*/ \
653*4882a593Smuzhiyun _set_timer(&(pwrctl)->pwr_state_check_timer, (ms)); \
654*4882a593Smuzhiyun } while (0)
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun #define rtw_set_pwr_state_check_timer(pwrctl) \
657*4882a593Smuzhiyun _rtw_set_pwr_state_check_timer((pwrctl), (pwrctl)->pwr_state_check_interval)
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun extern void rtw_init_pwrctrl_priv(_adapter *adapter);
660*4882a593Smuzhiyun extern void rtw_free_pwrctrl_priv(_adapter *adapter);
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun #ifdef CONFIG_LPS_LCLK
663*4882a593Smuzhiyun s32 rtw_register_task_alive(PADAPTER, u32 task);
664*4882a593Smuzhiyun void rtw_unregister_task_alive(PADAPTER, u32 task);
665*4882a593Smuzhiyun extern s32 rtw_register_tx_alive(PADAPTER padapter);
666*4882a593Smuzhiyun extern void rtw_unregister_tx_alive(PADAPTER padapter);
667*4882a593Smuzhiyun extern s32 rtw_register_rx_alive(PADAPTER padapter);
668*4882a593Smuzhiyun extern void rtw_unregister_rx_alive(PADAPTER padapter);
669*4882a593Smuzhiyun extern s32 rtw_register_cmd_alive(PADAPTER padapter);
670*4882a593Smuzhiyun extern void rtw_unregister_cmd_alive(PADAPTER padapter);
671*4882a593Smuzhiyun extern s32 rtw_register_evt_alive(PADAPTER padapter);
672*4882a593Smuzhiyun extern void rtw_unregister_evt_alive(PADAPTER padapter);
673*4882a593Smuzhiyun extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
674*4882a593Smuzhiyun extern void LPS_Leave_check(PADAPTER padapter);
675*4882a593Smuzhiyun void rtw_set_lps_lclk(_adapter *padapter, u8 enable);
676*4882a593Smuzhiyun #endif
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
679*4882a593Smuzhiyun extern void LeaveAllPowerSaveModeDirect(PADAPTER Adapter);
680*4882a593Smuzhiyun #ifdef CONFIG_IPS
681*4882a593Smuzhiyun void _ips_enter(_adapter *padapter);
682*4882a593Smuzhiyun void ips_enter(_adapter *padapter);
683*4882a593Smuzhiyun int _ips_leave(_adapter *padapter);
684*4882a593Smuzhiyun int ips_leave(_adapter *padapter);
685*4882a593Smuzhiyun #endif
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun void rtw_ps_processor(_adapter *padapter);
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun #ifdef SUPPORT_HW_RFOFF_DETECTED
690*4882a593Smuzhiyun rt_rf_power_state RfOnOffDetect(PADAPTER pAdapter);
691*4882a593Smuzhiyun #endif
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun
694*4882a593Smuzhiyun #ifdef DBG_CHECK_FW_PS_STATE
695*4882a593Smuzhiyun int rtw_fw_ps_state(PADAPTER padapter);
696*4882a593Smuzhiyun #endif
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun #ifdef CONFIG_LPS
699*4882a593Smuzhiyun extern const char * const LPS_CTRL_PHYDM;
700*4882a593Smuzhiyun void LPS_Enter(PADAPTER padapter, const char *msg);
701*4882a593Smuzhiyun void LPS_Leave(PADAPTER padapter, const char *msg);
702*4882a593Smuzhiyun void rtw_exec_lps(_adapter *padapter, u8 ps_mode);
703*4882a593Smuzhiyun void rtw_lps_rfon_ctrl(_adapter *padapter, u8 rfon_ctrl);
704*4882a593Smuzhiyun #ifdef CONFIG_CHECK_LEAVE_LPS
705*4882a593Smuzhiyun #ifdef CONFIG_LPS_CHK_BY_TP
706*4882a593Smuzhiyun void traffic_check_for_leave_lps_by_tp(PADAPTER padapter, u8 tx, struct sta_info *sta);
707*4882a593Smuzhiyun #endif
708*4882a593Smuzhiyun void traffic_check_for_leave_lps(PADAPTER padapter, u8 tx, u32 tx_packets);
709*4882a593Smuzhiyun #endif /*CONFIG_CHECK_LEAVE_LPS*/
710*4882a593Smuzhiyun void rtw_set_ps_mode(PADAPTER padapter, u8 ps_mode, u8 smart_ps, u8 bcn_ant_mode, const char *msg);
711*4882a593Smuzhiyun void rtw_set_fw_in_ips_mode(PADAPTER padapter, u8 enable);
712*4882a593Smuzhiyun u8 rtw_set_rpwm(_adapter *padapter, u8 val8);
713*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
714*4882a593Smuzhiyun void rtw_wow_lps_level_decide(_adapter *adapter, u8 wow_en);
715*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
716*4882a593Smuzhiyun #endif /* CONFIG_LPS */
717*4882a593Smuzhiyun
718*4882a593Smuzhiyun #ifdef CONFIG_RESUME_IN_WORKQUEUE
719*4882a593Smuzhiyun void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
720*4882a593Smuzhiyun #endif /* CONFIG_RESUME_IN_WORKQUEUE */
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
723*4882a593Smuzhiyun bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
724*4882a593Smuzhiyun bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
725*4882a593Smuzhiyun void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
726*4882a593Smuzhiyun void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
727*4882a593Smuzhiyun void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
728*4882a593Smuzhiyun #else
729*4882a593Smuzhiyun #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
730*4882a593Smuzhiyun #define rtw_is_do_late_resume(pwrpriv) _FALSE
731*4882a593Smuzhiyun #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
732*4882a593Smuzhiyun #define rtw_register_early_suspend(pwrpriv) do {} while (0)
733*4882a593Smuzhiyun #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
734*4882a593Smuzhiyun #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun u8 rtw_interface_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val);
737*4882a593Smuzhiyun void rtw_set_ips_deny(_adapter *padapter, u32 ms);
738*4882a593Smuzhiyun int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
739*4882a593Smuzhiyun #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
740*4882a593Smuzhiyun #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
741*4882a593Smuzhiyun int rtw_pm_set_ips(_adapter *padapter, u8 mode);
742*4882a593Smuzhiyun int rtw_pm_set_lps(_adapter *padapter, u8 mode);
743*4882a593Smuzhiyun int rtw_pm_set_lps_level(_adapter *padapter, u8 level);
744*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
745*4882a593Smuzhiyun int rtw_pm_set_lps_1t1r(_adapter *padapter, u8 en);
746*4882a593Smuzhiyun #endif
747*4882a593Smuzhiyun void rtw_set_lps_deny(_adapter *adapter, u32 ms);
748*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
749*4882a593Smuzhiyun int rtw_pm_set_wow_lps(_adapter *padapter, u8 mode);
750*4882a593Smuzhiyun int rtw_pm_set_wow_lps_level(_adapter *padapter, u8 level);
751*4882a593Smuzhiyun #ifdef CONFIG_LPS_1T1R
752*4882a593Smuzhiyun int rtw_pm_set_wow_lps_1t1r(_adapter *padapter, u8 en);
753*4882a593Smuzhiyun #endif
754*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun void rtw_ps_deny(PADAPTER padapter, PS_DENY_REASON reason);
757*4882a593Smuzhiyun void rtw_ps_deny_cancel(PADAPTER padapter, PS_DENY_REASON reason);
758*4882a593Smuzhiyun u32 rtw_ps_deny_get(PADAPTER padapter);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN)
761*4882a593Smuzhiyun void rtw_get_current_ip_address(PADAPTER padapter, u8 *pcurrentip);
762*4882a593Smuzhiyun void rtw_get_sec_iv(PADAPTER padapter, u8 *pcur_dot11txpn, u8 *StaAddr);
763*4882a593Smuzhiyun bool rtw_wowlan_parser_pattern_cmd(u8 *input, char *pattern,
764*4882a593Smuzhiyun int *pattern_len, char *bit_mask);
765*4882a593Smuzhiyun void rtw_wow_pattern_sw_reset(_adapter *adapter);
766*4882a593Smuzhiyun u8 rtw_set_default_pattern(_adapter *adapter);
767*4882a593Smuzhiyun void rtw_wow_pattern_sw_dump(_adapter *adapter);
768*4882a593Smuzhiyun #ifdef CONFIG_WAR_OFFLOAD
769*4882a593Smuzhiyun #if defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6)
770*4882a593Smuzhiyun void rtw_wow_war_mdns_dump_buf(struct seq_file *m, u8 *title, u8 *buf, u32 len);
771*4882a593Smuzhiyun void rtw_wow_war_mdns_dump_txt(struct seq_file *m, u8 *title, u8 *buf, u32 len);
772*4882a593Smuzhiyun bool rtw_wow_war_mdns_parser_pattern(u8 *input, char *target, u32 *target_len, u32 max_len);
773*4882a593Smuzhiyun void rtw_wow_war_mdns_parms_reset(_adapter *adapter, u8 is_set_default);
774*4882a593Smuzhiyun #endif /* defined(CONFIG_OFFLOAD_MDNS_V4) || defined(CONFIG_OFFLOAD_MDNS_V6) */
775*4882a593Smuzhiyun #endif /* CONFIG_WAR_OFFLOAD */
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
778*4882a593Smuzhiyun void rtw_ssmps_enter(_adapter *adapter, struct sta_info *sta);
779*4882a593Smuzhiyun void rtw_ssmps_leave(_adapter *adapter, struct sta_info *sta);
780*4882a593Smuzhiyun #endif /* __RTL871X_PWRCTRL_H_ */
781