1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _RTW_MP_H_ 16*4882a593Smuzhiyun #define _RTW_MP_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define RTWPRIV_VER_INFO 1 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define MAX_MP_XMITBUF_SZ 2048 21*4882a593Smuzhiyun #define NR_MP_XMITFRAME 8 22*4882a593Smuzhiyun #define MP_READ_REG_MAX_OFFSET 0x4FFF 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct mp_xmit_frame { 25*4882a593Smuzhiyun _list list; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct pkt_attrib attrib; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun _pkt *pkt; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun int frame_tag; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun _adapter *padapter; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* insert urb, irp, and irpcnt info below... */ 38*4882a593Smuzhiyun /* max frag_cnt = 8 */ 39*4882a593Smuzhiyun u8 *mem_addr; 40*4882a593Smuzhiyun u32 sz[8]; 41*4882a593Smuzhiyun u8 bpending[8]; 42*4882a593Smuzhiyun sint ac_tag[8]; 43*4882a593Smuzhiyun sint last[8]; 44*4882a593Smuzhiyun uint irpcnt; 45*4882a593Smuzhiyun uint fragcnt; 46*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct mp_wiparam { 52*4882a593Smuzhiyun u32 bcompleted; 53*4882a593Smuzhiyun u32 act_type; 54*4882a593Smuzhiyun u32 io_offset; 55*4882a593Smuzhiyun u32 io_value; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun typedef void(*wi_act_func)(void *padapter); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct mp_tx { 61*4882a593Smuzhiyun u8 stop; 62*4882a593Smuzhiyun u32 count, sended; 63*4882a593Smuzhiyun u8 payload; 64*4882a593Smuzhiyun struct pkt_attrib attrib; 65*4882a593Smuzhiyun /* struct tx_desc desc; */ 66*4882a593Smuzhiyun /* u8 resvdtx[7]; */ 67*4882a593Smuzhiyun u8 desc[TXDESC_SIZE]; 68*4882a593Smuzhiyun u8 *pallocated_buf; 69*4882a593Smuzhiyun u8 *buf; 70*4882a593Smuzhiyun u32 buf_size, write_size; 71*4882a593Smuzhiyun _thread_hdl_ PktTxThread; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define MP_MAX_LINES 1000 75*4882a593Smuzhiyun #define MP_MAX_LINES_BYTES 256 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun typedef struct _RT_PMAC_PKT_INFO { 79*4882a593Smuzhiyun u8 MCS; 80*4882a593Smuzhiyun u8 Nss; 81*4882a593Smuzhiyun u8 Nsts; 82*4882a593Smuzhiyun u32 N_sym; 83*4882a593Smuzhiyun u8 SIGA2B3; 84*4882a593Smuzhiyun } RT_PMAC_PKT_INFO, *PRT_PMAC_PKT_INFO; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun typedef struct _RT_PMAC_TX_INFO { 87*4882a593Smuzhiyun u8 bEnPMacTx:1; /* 0: Disable PMac 1: Enable PMac */ 88*4882a593Smuzhiyun u8 Mode:3; /* 0: Packet TX 3:Continuous TX */ 89*4882a593Smuzhiyun u8 Ntx:4; /* 0-7 */ 90*4882a593Smuzhiyun u8 TX_RATE; /* MPT_RATE_E */ 91*4882a593Smuzhiyun u8 TX_RATE_HEX; 92*4882a593Smuzhiyun u8 TX_SC; 93*4882a593Smuzhiyun u8 bSGI:1; 94*4882a593Smuzhiyun u8 bSPreamble:1; 95*4882a593Smuzhiyun u8 bSTBC:1; 96*4882a593Smuzhiyun u8 bLDPC:1; 97*4882a593Smuzhiyun u8 NDP_sound:1; 98*4882a593Smuzhiyun u8 BandWidth:3; /* 0: 20 1:40 2:80Mhz */ 99*4882a593Smuzhiyun u8 m_STBC; /* bSTBC + 1 */ 100*4882a593Smuzhiyun u16 PacketPeriod; 101*4882a593Smuzhiyun u32 PacketCount; 102*4882a593Smuzhiyun u32 PacketLength; 103*4882a593Smuzhiyun u8 PacketPattern; 104*4882a593Smuzhiyun u16 SFD; 105*4882a593Smuzhiyun u8 SignalField; 106*4882a593Smuzhiyun u8 ServiceField; 107*4882a593Smuzhiyun u16 LENGTH; 108*4882a593Smuzhiyun u8 CRC16[2]; 109*4882a593Smuzhiyun u8 LSIG[3]; 110*4882a593Smuzhiyun u8 HT_SIG[6]; 111*4882a593Smuzhiyun u8 VHT_SIG_A[6]; 112*4882a593Smuzhiyun u8 VHT_SIG_B[4]; 113*4882a593Smuzhiyun u8 VHT_SIG_B_CRC; 114*4882a593Smuzhiyun u8 VHT_Delimiter[4]; 115*4882a593Smuzhiyun u8 MacAddress[6]; 116*4882a593Smuzhiyun } RT_PMAC_TX_INFO, *PRT_PMAC_TX_INFO; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun typedef void (*MPT_WORK_ITEM_HANDLER)(void *Adapter); 120*4882a593Smuzhiyun typedef struct _MPT_CONTEXT { 121*4882a593Smuzhiyun /* Indicate if we have started Mass Production Test. */ 122*4882a593Smuzhiyun BOOLEAN bMassProdTest; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Indicate if the driver is unloading or unloaded. */ 125*4882a593Smuzhiyun BOOLEAN bMptDrvUnload; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun _sema MPh2c_Sema; 128*4882a593Smuzhiyun _timer MPh2c_timeout_timer; 129*4882a593Smuzhiyun /* Event used to sync H2c for BT control */ 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun BOOLEAN MptH2cRspEvent; 132*4882a593Smuzhiyun BOOLEAN MptBtC2hEvent; 133*4882a593Smuzhiyun BOOLEAN bMPh2c_timeout; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* 8190 PCI does not support NDIS_WORK_ITEM. */ 136*4882a593Smuzhiyun /* Work Item for Mass Production Test. */ 137*4882a593Smuzhiyun /* NDIS_WORK_ITEM MptWorkItem; 138*4882a593Smuzhiyun * RT_WORK_ITEM MptWorkItem; */ 139*4882a593Smuzhiyun /* Event used to sync the case unloading driver and MptWorkItem is still in progress. 140*4882a593Smuzhiyun * NDIS_EVENT MptWorkItemEvent; */ 141*4882a593Smuzhiyun /* To protect the following variables. 142*4882a593Smuzhiyun * NDIS_SPIN_LOCK MptWorkItemSpinLock; */ 143*4882a593Smuzhiyun /* Indicate a MptWorkItem is scheduled and not yet finished. */ 144*4882a593Smuzhiyun BOOLEAN bMptWorkItemInProgress; 145*4882a593Smuzhiyun /* An instance which implements function and context of MptWorkItem. */ 146*4882a593Smuzhiyun MPT_WORK_ITEM_HANDLER CurrMptAct; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* 1=Start, 0=Stop from UI. */ 149*4882a593Smuzhiyun u32 MptTestStart; 150*4882a593Smuzhiyun /* _TEST_MODE, defined in MPT_Req2.h */ 151*4882a593Smuzhiyun u32 MptTestItem; 152*4882a593Smuzhiyun /* Variable needed in each implementation of CurrMptAct. */ 153*4882a593Smuzhiyun u32 MptActType; /* Type of action performed in CurrMptAct. */ 154*4882a593Smuzhiyun /* The Offset of IO operation is depend of MptActType. */ 155*4882a593Smuzhiyun u32 MptIoOffset; 156*4882a593Smuzhiyun /* The Value of IO operation is depend of MptActType. */ 157*4882a593Smuzhiyun u32 MptIoValue; 158*4882a593Smuzhiyun /* The RfPath of IO operation is depend of MptActType. */ 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun u32 mpt_rf_path; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun WIRELESS_MODE MptWirelessModeToSw; /* Wireless mode to switch. */ 164*4882a593Smuzhiyun u8 MptChannelToSw; /* Channel to switch. */ 165*4882a593Smuzhiyun u8 MptInitGainToSet; /* Initial gain to set. */ 166*4882a593Smuzhiyun /* u32 bMptAntennaA; */ /* TRUE if we want to use antenna A. */ 167*4882a593Smuzhiyun u32 MptBandWidth; /* bandwidth to switch. */ 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun u32 mpt_rate_index;/* rate index. */ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun /* Register value kept for Single Carrier Tx test. */ 172*4882a593Smuzhiyun u8 btMpCckTxPower; 173*4882a593Smuzhiyun /* Register value kept for Single Carrier Tx test. */ 174*4882a593Smuzhiyun u8 btMpOfdmTxPower; 175*4882a593Smuzhiyun /* For MP Tx Power index */ 176*4882a593Smuzhiyun u8 TxPwrLevel[4]; /* rf-A, rf-B*/ 177*4882a593Smuzhiyun u32 RegTxPwrLimit; 178*4882a593Smuzhiyun /* Content of RCR Regsiter for Mass Production Test. */ 179*4882a593Smuzhiyun u32 MptRCR; 180*4882a593Smuzhiyun /* TRUE if we only receive packets with specific pattern. */ 181*4882a593Smuzhiyun BOOLEAN bMptFilterPattern; 182*4882a593Smuzhiyun /* Rx OK count, statistics used in Mass Production Test. */ 183*4882a593Smuzhiyun u32 MptRxOkCnt; 184*4882a593Smuzhiyun /* Rx CRC32 error count, statistics used in Mass Production Test. */ 185*4882a593Smuzhiyun u32 MptRxCrcErrCnt; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun BOOLEAN bCckContTx; /* TRUE if we are in CCK Continuous Tx test. */ 188*4882a593Smuzhiyun BOOLEAN bOfdmContTx; /* TRUE if we are in OFDM Continuous Tx test. */ 189*4882a593Smuzhiyun /* TRUE if we have start Continuous Tx test. */ 190*4882a593Smuzhiyun BOOLEAN is_start_cont_tx; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun /* TRUE if we are in Single Carrier Tx test. */ 193*4882a593Smuzhiyun BOOLEAN bSingleCarrier; 194*4882a593Smuzhiyun /* TRUE if we are in Carrier Suppression Tx Test. */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun BOOLEAN is_carrier_suppression; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* TRUE if we are in Single Tone Tx test. */ 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun BOOLEAN is_single_tone; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* ACK counter asked by K.Y.. */ 204*4882a593Smuzhiyun BOOLEAN bMptEnableAckCounter; 205*4882a593Smuzhiyun u32 MptAckCounter; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun /* SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! */ 208*4882a593Smuzhiyun /* s8 BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; */ 209*4882a593Smuzhiyun /* s8 BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; */ 210*4882a593Smuzhiyun /* s32 RfReadLine[2]; */ 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun u8 APK_bound[2]; /* for APK path A/path B */ 213*4882a593Smuzhiyun BOOLEAN bMptIndexEven; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun u8 backup0xc50; 216*4882a593Smuzhiyun u8 backup0xc58; 217*4882a593Smuzhiyun u8 backup0xc30; 218*4882a593Smuzhiyun u8 backup0x52_RF_A; 219*4882a593Smuzhiyun u8 backup0x52_RF_B; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun u32 backup0x58_RF_A; 222*4882a593Smuzhiyun u32 backup0x58_RF_B; 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun u8 h2cReqNum; 225*4882a593Smuzhiyun u8 c2hBuf[32]; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun u8 btInBuf[100]; 228*4882a593Smuzhiyun u32 mptOutLen; 229*4882a593Smuzhiyun u8 mptOutBuf[100]; 230*4882a593Smuzhiyun RT_PMAC_TX_INFO PMacTxInfo; 231*4882a593Smuzhiyun RT_PMAC_PKT_INFO PMacPktInfo; 232*4882a593Smuzhiyun u8 HWTxmode; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun BOOLEAN bldpc; 235*4882a593Smuzhiyun BOOLEAN bstbc; 236*4882a593Smuzhiyun } MPT_CONTEXT, *PMPT_CONTEXT; 237*4882a593Smuzhiyun /* #endif */ 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* #define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) */ 241*4882a593Smuzhiyun enum { 242*4882a593Smuzhiyun WRITE_REG = 1, 243*4882a593Smuzhiyun READ_REG, 244*4882a593Smuzhiyun WRITE_RF, 245*4882a593Smuzhiyun READ_RF, 246*4882a593Smuzhiyun MP_START, 247*4882a593Smuzhiyun MP_STOP, 248*4882a593Smuzhiyun MP_RATE, 249*4882a593Smuzhiyun MP_CHANNEL, 250*4882a593Smuzhiyun MP_CHL_OFFSET, 251*4882a593Smuzhiyun MP_BANDWIDTH, 252*4882a593Smuzhiyun MP_TXPOWER, 253*4882a593Smuzhiyun MP_ANT_TX, 254*4882a593Smuzhiyun MP_ANT_RX, 255*4882a593Smuzhiyun MP_CTX, 256*4882a593Smuzhiyun MP_QUERY, 257*4882a593Smuzhiyun MP_ARX, 258*4882a593Smuzhiyun MP_PSD, 259*4882a593Smuzhiyun MP_PWRTRK, 260*4882a593Smuzhiyun MP_THER, 261*4882a593Smuzhiyun MP_IOCTL, 262*4882a593Smuzhiyun EFUSE_GET, 263*4882a593Smuzhiyun EFUSE_SET, 264*4882a593Smuzhiyun MP_RESET_STATS, 265*4882a593Smuzhiyun MP_DUMP, 266*4882a593Smuzhiyun MP_PHYPARA, 267*4882a593Smuzhiyun MP_SetRFPathSwh, 268*4882a593Smuzhiyun MP_QueryDrvStats, 269*4882a593Smuzhiyun CTA_TEST, 270*4882a593Smuzhiyun MP_DISABLE_BT_COEXIST, 271*4882a593Smuzhiyun MP_PwrCtlDM, 272*4882a593Smuzhiyun MP_GETVER, 273*4882a593Smuzhiyun MP_MON, 274*4882a593Smuzhiyun EFUSE_BT_MASK, 275*4882a593Smuzhiyun EFUSE_MASK, 276*4882a593Smuzhiyun EFUSE_FILE, 277*4882a593Smuzhiyun EFUSE_FILE_STORE, 278*4882a593Smuzhiyun MP_TX, 279*4882a593Smuzhiyun MP_RX, 280*4882a593Smuzhiyun MP_IQK, 281*4882a593Smuzhiyun MP_LCK, 282*4882a593Smuzhiyun MP_HW_TX_MODE, 283*4882a593Smuzhiyun MP_GET_TXPOWER_INX, 284*4882a593Smuzhiyun MP_CUSTOMER_STR, 285*4882a593Smuzhiyun MP_PWRLMT, 286*4882a593Smuzhiyun MP_PWRBYRATE, 287*4882a593Smuzhiyun BT_EFUSE_FILE, 288*4882a593Smuzhiyun MP_SetBT, 289*4882a593Smuzhiyun MP_SWRFPath, 290*4882a593Smuzhiyun MP_LINK, 291*4882a593Smuzhiyun MP_DPK_TRK, 292*4882a593Smuzhiyun MP_DPK, 293*4882a593Smuzhiyun MP_GET_TSSIDE, 294*4882a593Smuzhiyun MP_SET_TSSIDE, 295*4882a593Smuzhiyun MP_NULL, 296*4882a593Smuzhiyun #ifdef CONFIG_APPEND_VENDOR_IE_ENABLE 297*4882a593Smuzhiyun VENDOR_IE_SET , 298*4882a593Smuzhiyun VENDOR_IE_GET , 299*4882a593Smuzhiyun #endif 300*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 301*4882a593Smuzhiyun MP_WOW_ENABLE, 302*4882a593Smuzhiyun MP_WOW_SET_PATTERN, 303*4882a593Smuzhiyun #ifdef CONFIG_WOW_KEEP_ALIVE_PATTERN 304*4882a593Smuzhiyun MP_WOW_SET_KEEP_ALIVE_PATTERN, 305*4882a593Smuzhiyun #endif /*CONFIG_WOW_KEEP_ALIVE_PATTERN*/ 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun #endif 308*4882a593Smuzhiyun #ifdef CONFIG_AP_WOWLAN 309*4882a593Smuzhiyun MP_AP_WOW_ENABLE, 310*4882a593Smuzhiyun #endif 311*4882a593Smuzhiyun MP_SD_IREAD, 312*4882a593Smuzhiyun MP_SD_IWRITE, 313*4882a593Smuzhiyun GET_IC_TYPE, 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun struct mp_priv { 317*4882a593Smuzhiyun _adapter *papdater; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun /* Testing Flag */ 320*4882a593Smuzhiyun u32 mode;/* 0 for normal type packet, 1 for loopback packet (16bytes TXCMD) */ 321*4882a593Smuzhiyun 322*4882a593Smuzhiyun u32 prev_fw_state; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* OID cmd handler */ 325*4882a593Smuzhiyun struct mp_wiparam workparam; 326*4882a593Smuzhiyun /* u8 act_in_progress; */ 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun /* Tx Section */ 329*4882a593Smuzhiyun u8 TID; 330*4882a593Smuzhiyun u32 tx_pktcount; 331*4882a593Smuzhiyun u32 pktInterval; 332*4882a593Smuzhiyun u32 pktLength; 333*4882a593Smuzhiyun struct mp_tx tx; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun /* Rx Section */ 336*4882a593Smuzhiyun u32 rx_bssidpktcount; 337*4882a593Smuzhiyun u32 rx_pktcount; 338*4882a593Smuzhiyun u32 rx_pktcount_filter_out; 339*4882a593Smuzhiyun u32 rx_crcerrpktcount; 340*4882a593Smuzhiyun u32 rx_pktloss; 341*4882a593Smuzhiyun BOOLEAN rx_bindicatePkt; 342*4882a593Smuzhiyun struct recv_stat rxstat; 343*4882a593Smuzhiyun BOOLEAN brx_filter_beacon; 344*4882a593Smuzhiyun 345*4882a593Smuzhiyun /* RF/BB relative */ 346*4882a593Smuzhiyun u8 channel; 347*4882a593Smuzhiyun u8 bandwidth; 348*4882a593Smuzhiyun u8 prime_channel_offset; 349*4882a593Smuzhiyun u8 txpoweridx; 350*4882a593Smuzhiyun s8 txpower_dbm_offset; 351*4882a593Smuzhiyun u8 rateidx; 352*4882a593Smuzhiyun u32 preamble; 353*4882a593Smuzhiyun /* u8 modem; */ 354*4882a593Smuzhiyun u32 CrystalCap; 355*4882a593Smuzhiyun /* u32 curr_crystalcap; */ 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun u16 antenna_tx; 358*4882a593Smuzhiyun u16 antenna_rx; 359*4882a593Smuzhiyun /* u8 curr_rfpath; */ 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun u8 check_mp_pkt; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun u8 bSetTxPower; 364*4882a593Smuzhiyun /* uint ForcedDataRate; */ 365*4882a593Smuzhiyun u8 mp_dm; 366*4882a593Smuzhiyun u8 mac_filter[ETH_ALEN]; 367*4882a593Smuzhiyun u8 bmac_filter; 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun /* RF PATH Setting for WLG WLA BTG BT */ 370*4882a593Smuzhiyun u8 rf_path_cfg; 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun struct wlan_network mp_network; 373*4882a593Smuzhiyun NDIS_802_11_MAC_ADDRESS network_macaddr; 374*4882a593Smuzhiyun 375*4882a593Smuzhiyun u8 *pallocated_mp_xmitframe_buf; 376*4882a593Smuzhiyun u8 *pmp_xmtframe_buf; 377*4882a593Smuzhiyun _queue free_mp_xmitqueue; 378*4882a593Smuzhiyun u32 free_mp_xmitframe_cnt; 379*4882a593Smuzhiyun BOOLEAN bSetRxBssid; 380*4882a593Smuzhiyun BOOLEAN bTxBufCkFail; 381*4882a593Smuzhiyun BOOLEAN bRTWSmbCfg; 382*4882a593Smuzhiyun BOOLEAN bloopback; 383*4882a593Smuzhiyun BOOLEAN bloadefusemap; 384*4882a593Smuzhiyun BOOLEAN bloadBTefusemap; 385*4882a593Smuzhiyun BOOLEAN bprocess_mp_mode; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun MPT_CONTEXT mpt_ctx; 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun u8 *TXradomBuffer; 390*4882a593Smuzhiyun u8 CureFuseBTCoex; 391*4882a593Smuzhiyun u8 mplink_buf[2048]; 392*4882a593Smuzhiyun u32 mplink_rx_len; 393*4882a593Smuzhiyun BOOLEAN mplink_brx; 394*4882a593Smuzhiyun BOOLEAN mplink_btx; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun bool tssitrk_on; 397*4882a593Smuzhiyun bool efuse_update_on; 398*4882a593Smuzhiyun bool efuse_update_file; 399*4882a593Smuzhiyun char efuse_file_path[128]; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun typedef struct _IOCMD_STRUCT_ { 403*4882a593Smuzhiyun u8 cmdclass; 404*4882a593Smuzhiyun u16 value; 405*4882a593Smuzhiyun u8 index; 406*4882a593Smuzhiyun } IOCMD_STRUCT; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun struct rf_reg_param { 409*4882a593Smuzhiyun u32 path; 410*4882a593Smuzhiyun u32 offset; 411*4882a593Smuzhiyun u32 value; 412*4882a593Smuzhiyun }; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun struct bb_reg_param { 415*4882a593Smuzhiyun u32 offset; 416*4882a593Smuzhiyun u32 value; 417*4882a593Smuzhiyun }; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun typedef struct _MP_FIRMWARE { 420*4882a593Smuzhiyun FIRMWARE_SOURCE eFWSource; 421*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG 422*4882a593Smuzhiyun u8 *szFwBuffer; 423*4882a593Smuzhiyun #else 424*4882a593Smuzhiyun u8 szFwBuffer[0x8000]; 425*4882a593Smuzhiyun #endif 426*4882a593Smuzhiyun u32 ulFwLength; 427*4882a593Smuzhiyun } RT_MP_FIRMWARE, *PRT_MP_FIRMWARE; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun 430*4882a593Smuzhiyun #define GET_MPPRIV(__padapter) (struct mp_priv*)(&(((struct _ADAPTER*)__padapter)->mppriv)) 431*4882a593Smuzhiyun #define GET_EFUSE_UPDATE_ON(_padapter) (GET_MPPRIV(_padapter)->efuse_update_on) 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun /* *********************************************************************** */ 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun #define LOWER _TRUE 436*4882a593Smuzhiyun #define RAISE _FALSE 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun /* Hardware Registers */ 439*4882a593Smuzhiyun #if 0 440*4882a593Smuzhiyun #if 0 441*4882a593Smuzhiyun #define IOCMD_CTRL_REG 0x102502C0 442*4882a593Smuzhiyun #define IOCMD_DATA_REG 0x102502C4 443*4882a593Smuzhiyun #else 444*4882a593Smuzhiyun #define IOCMD_CTRL_REG 0x10250370 445*4882a593Smuzhiyun #define IOCMD_DATA_REG 0x10250374 446*4882a593Smuzhiyun #endif 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun #define IOCMD_GET_THERMAL_METER 0xFD000028 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #define IOCMD_CLASS_BB_RF 0xF0 451*4882a593Smuzhiyun #define IOCMD_BB_READ_IDX 0x00 452*4882a593Smuzhiyun #define IOCMD_BB_WRITE_IDX 0x01 453*4882a593Smuzhiyun #define IOCMD_RF_READ_IDX 0x02 454*4882a593Smuzhiyun #define IOCMD_RF_WRIT_IDX 0x03 455*4882a593Smuzhiyun #endif 456*4882a593Smuzhiyun #define BB_REG_BASE_ADDR 0x800 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun /* MP variables */ 459*4882a593Smuzhiyun #if 0 460*4882a593Smuzhiyun #define _2MAC_MODE_ 0 461*4882a593Smuzhiyun #define _LOOPBOOK_MODE_ 1 462*4882a593Smuzhiyun #endif 463*4882a593Smuzhiyun typedef enum _MP_MODE_ { 464*4882a593Smuzhiyun MP_OFF, 465*4882a593Smuzhiyun MP_ON, 466*4882a593Smuzhiyun MP_ERR, 467*4882a593Smuzhiyun MP_CONTINUOUS_TX, 468*4882a593Smuzhiyun MP_SINGLE_CARRIER_TX, 469*4882a593Smuzhiyun MP_CARRIER_SUPPRISSION_TX, 470*4882a593Smuzhiyun MP_SINGLE_TONE_TX, 471*4882a593Smuzhiyun MP_PACKET_TX, 472*4882a593Smuzhiyun MP_PACKET_RX 473*4882a593Smuzhiyun } MP_MODE; 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun typedef enum _TEST_MODE { 476*4882a593Smuzhiyun TEST_NONE , 477*4882a593Smuzhiyun PACKETS_TX , 478*4882a593Smuzhiyun PACKETS_RX , 479*4882a593Smuzhiyun CONTINUOUS_TX , 480*4882a593Smuzhiyun OFDM_Single_Tone_TX , 481*4882a593Smuzhiyun CCK_Carrier_Suppression_TX 482*4882a593Smuzhiyun } TEST_MODE; 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun typedef enum _MPT_BANDWIDTH { 486*4882a593Smuzhiyun MPT_BW_20MHZ = 0, 487*4882a593Smuzhiyun MPT_BW_40MHZ_DUPLICATE = 1, 488*4882a593Smuzhiyun MPT_BW_40MHZ_ABOVE = 2, 489*4882a593Smuzhiyun MPT_BW_40MHZ_BELOW = 3, 490*4882a593Smuzhiyun MPT_BW_40MHZ = 4, 491*4882a593Smuzhiyun MPT_BW_80MHZ = 5, 492*4882a593Smuzhiyun MPT_BW_80MHZ_20_ABOVE = 6, 493*4882a593Smuzhiyun MPT_BW_80MHZ_20_BELOW = 7, 494*4882a593Smuzhiyun MPT_BW_80MHZ_20_BOTTOM = 8, 495*4882a593Smuzhiyun MPT_BW_80MHZ_20_TOP = 9, 496*4882a593Smuzhiyun MPT_BW_80MHZ_40_ABOVE = 10, 497*4882a593Smuzhiyun MPT_BW_80MHZ_40_BELOW = 11, 498*4882a593Smuzhiyun } MPT_BANDWIDTHE, *PMPT_BANDWIDTH; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun #define MAX_RF_PATH_NUMS RF_PATH_MAX 501*4882a593Smuzhiyun 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun extern u8 mpdatarate[NumRates]; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun /* MP set force data rate base on the definition. */ 506*4882a593Smuzhiyun typedef enum _MPT_RATE_INDEX { 507*4882a593Smuzhiyun /* CCK rate. */ 508*4882a593Smuzhiyun MPT_RATE_1M = 1 , /* 0 */ 509*4882a593Smuzhiyun MPT_RATE_2M, 510*4882a593Smuzhiyun MPT_RATE_55M, 511*4882a593Smuzhiyun MPT_RATE_11M, /* 3 */ 512*4882a593Smuzhiyun 513*4882a593Smuzhiyun /* OFDM rate. */ 514*4882a593Smuzhiyun MPT_RATE_6M, /* 4 */ 515*4882a593Smuzhiyun MPT_RATE_9M, 516*4882a593Smuzhiyun MPT_RATE_12M, 517*4882a593Smuzhiyun MPT_RATE_18M, 518*4882a593Smuzhiyun MPT_RATE_24M, 519*4882a593Smuzhiyun MPT_RATE_36M, 520*4882a593Smuzhiyun MPT_RATE_48M, 521*4882a593Smuzhiyun MPT_RATE_54M, /* 11 */ 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun /* HT rate. */ 524*4882a593Smuzhiyun MPT_RATE_MCS0, /* 12 */ 525*4882a593Smuzhiyun MPT_RATE_MCS1, 526*4882a593Smuzhiyun MPT_RATE_MCS2, 527*4882a593Smuzhiyun MPT_RATE_MCS3, 528*4882a593Smuzhiyun MPT_RATE_MCS4, 529*4882a593Smuzhiyun MPT_RATE_MCS5, 530*4882a593Smuzhiyun MPT_RATE_MCS6, 531*4882a593Smuzhiyun MPT_RATE_MCS7, /* 19 */ 532*4882a593Smuzhiyun MPT_RATE_MCS8, 533*4882a593Smuzhiyun MPT_RATE_MCS9, 534*4882a593Smuzhiyun MPT_RATE_MCS10, 535*4882a593Smuzhiyun MPT_RATE_MCS11, 536*4882a593Smuzhiyun MPT_RATE_MCS12, 537*4882a593Smuzhiyun MPT_RATE_MCS13, 538*4882a593Smuzhiyun MPT_RATE_MCS14, 539*4882a593Smuzhiyun MPT_RATE_MCS15, /* 27 */ 540*4882a593Smuzhiyun MPT_RATE_MCS16, 541*4882a593Smuzhiyun MPT_RATE_MCS17, /* #29 */ 542*4882a593Smuzhiyun MPT_RATE_MCS18, 543*4882a593Smuzhiyun MPT_RATE_MCS19, 544*4882a593Smuzhiyun MPT_RATE_MCS20, 545*4882a593Smuzhiyun MPT_RATE_MCS21, 546*4882a593Smuzhiyun MPT_RATE_MCS22, /* #34 */ 547*4882a593Smuzhiyun MPT_RATE_MCS23, 548*4882a593Smuzhiyun MPT_RATE_MCS24, 549*4882a593Smuzhiyun MPT_RATE_MCS25, 550*4882a593Smuzhiyun MPT_RATE_MCS26, 551*4882a593Smuzhiyun MPT_RATE_MCS27, /* #39 */ 552*4882a593Smuzhiyun MPT_RATE_MCS28, /* #40 */ 553*4882a593Smuzhiyun MPT_RATE_MCS29, /* #41 */ 554*4882a593Smuzhiyun MPT_RATE_MCS30, /* #42 */ 555*4882a593Smuzhiyun MPT_RATE_MCS31, /* #43 */ 556*4882a593Smuzhiyun /* VHT rate. Total: 20*/ 557*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS0 = 100,/* #44*/ 558*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS1, /* # */ 559*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS2, 560*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS3, 561*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS4, 562*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS5, 563*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS6, /* # */ 564*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS7, 565*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS8, 566*4882a593Smuzhiyun MPT_RATE_VHT1SS_MCS9, /* #53 */ 567*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS0, /* #54 */ 568*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS1, 569*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS2, 570*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS3, 571*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS4, 572*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS5, 573*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS6, 574*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS7, 575*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS8, 576*4882a593Smuzhiyun MPT_RATE_VHT2SS_MCS9, /* #63 */ 577*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS0, 578*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS1, 579*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS2, 580*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS3, 581*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS4, 582*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS5, 583*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS6, /* #126 */ 584*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS7, 585*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS8, 586*4882a593Smuzhiyun MPT_RATE_VHT3SS_MCS9, 587*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS0, 588*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS1, /* #131 */ 589*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS2, 590*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS3, 591*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS4, 592*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS5, 593*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS6, /* #136 */ 594*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS7, 595*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS8, 596*4882a593Smuzhiyun MPT_RATE_VHT4SS_MCS9, 597*4882a593Smuzhiyun MPT_RATE_LAST 598*4882a593Smuzhiyun } MPT_RATE_E, *PMPT_RATE_E; 599*4882a593Smuzhiyun 600*4882a593Smuzhiyun #define MAX_TX_PWR_INDEX_N_MODE 64 /* 0x3F */ 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun #define MPT_IS_CCK_RATE(_value) (MPT_RATE_1M <= _value && _value <= MPT_RATE_11M) 603*4882a593Smuzhiyun #define MPT_IS_OFDM_RATE(_value) (MPT_RATE_6M <= _value && _value <= MPT_RATE_54M) 604*4882a593Smuzhiyun #define MPT_IS_HT_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS31) 605*4882a593Smuzhiyun #define MPT_IS_HT_1S_RATE(_value) (MPT_RATE_MCS0 <= _value && _value <= MPT_RATE_MCS7) 606*4882a593Smuzhiyun #define MPT_IS_HT_2S_RATE(_value) (MPT_RATE_MCS8 <= _value && _value <= MPT_RATE_MCS15) 607*4882a593Smuzhiyun #define MPT_IS_HT_3S_RATE(_value) (MPT_RATE_MCS16 <= _value && _value <= MPT_RATE_MCS23) 608*4882a593Smuzhiyun #define MPT_IS_HT_4S_RATE(_value) (MPT_RATE_MCS24 <= _value && _value <= MPT_RATE_MCS31) 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun #define MPT_IS_VHT_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) 611*4882a593Smuzhiyun #define MPT_IS_VHT_1S_RATE(_value) (MPT_RATE_VHT1SS_MCS0 <= _value && _value <= MPT_RATE_VHT1SS_MCS9) 612*4882a593Smuzhiyun #define MPT_IS_VHT_2S_RATE(_value) (MPT_RATE_VHT2SS_MCS0 <= _value && _value <= MPT_RATE_VHT2SS_MCS9) 613*4882a593Smuzhiyun #define MPT_IS_VHT_3S_RATE(_value) (MPT_RATE_VHT3SS_MCS0 <= _value && _value <= MPT_RATE_VHT3SS_MCS9) 614*4882a593Smuzhiyun #define MPT_IS_VHT_4S_RATE(_value) (MPT_RATE_VHT4SS_MCS0 <= _value && _value <= MPT_RATE_VHT4SS_MCS9) 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun #define MPT_IS_2SS_RATE(_rate) ((MPT_RATE_MCS8 <= _rate && _rate <= MPT_RATE_MCS15) || \ 617*4882a593Smuzhiyun (MPT_RATE_VHT2SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT2SS_MCS9)) 618*4882a593Smuzhiyun #define MPT_IS_3SS_RATE(_rate) ((MPT_RATE_MCS16 <= _rate && _rate <= MPT_RATE_MCS23) || \ 619*4882a593Smuzhiyun (MPT_RATE_VHT3SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT3SS_MCS9)) 620*4882a593Smuzhiyun #define MPT_IS_4SS_RATE(_rate) ((MPT_RATE_MCS24 <= _rate && _rate <= MPT_RATE_MCS31) || \ 621*4882a593Smuzhiyun (MPT_RATE_VHT4SS_MCS0 <= _rate && _rate <= MPT_RATE_VHT4SS_MCS9)) 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun typedef enum _POWER_MODE_ { 624*4882a593Smuzhiyun POWER_LOW = 0, 625*4882a593Smuzhiyun POWER_NORMAL 626*4882a593Smuzhiyun } POWER_MODE; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /* The following enumeration is used to define the value of Reg0xD00[30:28] or JaguarReg0x914[18:16]. */ 629*4882a593Smuzhiyun typedef enum _OFDM_TX_MODE { 630*4882a593Smuzhiyun OFDM_ALL_OFF = 0, 631*4882a593Smuzhiyun OFDM_ContinuousTx = 1, 632*4882a593Smuzhiyun OFDM_SingleCarrier = 2, 633*4882a593Smuzhiyun OFDM_SingleTone = 4, 634*4882a593Smuzhiyun } OFDM_TX_MODE; 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun #define RX_PKT_BROADCAST 1 638*4882a593Smuzhiyun #define RX_PKT_DEST_ADDR 2 639*4882a593Smuzhiyun #define RX_PKT_PHY_MATCH 3 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun typedef enum _ENCRY_CTRL_STATE_ { 642*4882a593Smuzhiyun HW_CONTROL, /* hw encryption& decryption */ 643*4882a593Smuzhiyun SW_CONTROL, /* sw encryption& decryption */ 644*4882a593Smuzhiyun HW_ENCRY_SW_DECRY, /* hw encryption & sw decryption */ 645*4882a593Smuzhiyun SW_ENCRY_HW_DECRY /* sw encryption & hw decryption */ 646*4882a593Smuzhiyun } ENCRY_CTRL_STATE; 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun typedef enum _MPT_TXPWR_DEF { 649*4882a593Smuzhiyun MPT_CCK, 650*4882a593Smuzhiyun MPT_OFDM, /* L and HT OFDM */ 651*4882a593Smuzhiyun MPT_OFDM_AND_HT, 652*4882a593Smuzhiyun MPT_HT, 653*4882a593Smuzhiyun MPT_VHT 654*4882a593Smuzhiyun } MPT_TXPWR_DEF; 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun 657*4882a593Smuzhiyun #define IS_MPT_HT_RATE(_rate) (_rate >= MPT_RATE_MCS0 && _rate <= MPT_RATE_MCS31) 658*4882a593Smuzhiyun #define IS_MPT_VHT_RATE(_rate) (_rate >= MPT_RATE_VHT1SS_MCS0 && _rate <= MPT_RATE_VHT4SS_MCS9) 659*4882a593Smuzhiyun #define IS_MPT_CCK_RATE(_rate) (_rate >= MPT_RATE_1M && _rate <= MPT_RATE_11M) 660*4882a593Smuzhiyun #define IS_MPT_OFDM_RATE(_rate) (_rate >= MPT_RATE_6M && _rate <= MPT_RATE_54M) 661*4882a593Smuzhiyun 662*4882a593Smuzhiyun typedef enum _mp_tx_pkt_payload{ 663*4882a593Smuzhiyun MP_TX_Payload_00 = 0, 664*4882a593Smuzhiyun MP_TX_Payload_a5, 665*4882a593Smuzhiyun MP_TX_Payload_5a, 666*4882a593Smuzhiyun MP_TX_Payload_ff, 667*4882a593Smuzhiyun MP_TX_Payload_prbs9, 668*4882a593Smuzhiyun MP_TX_Payload_default_random 669*4882a593Smuzhiyun } mp_tx_pkt_payload; 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun /*************************************************************************/ 672*4882a593Smuzhiyun #if 0 673*4882a593Smuzhiyun extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); 674*4882a593Smuzhiyun extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); 675*4882a593Smuzhiyun #endif 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun extern s32 init_mp_priv(PADAPTER padapter); 678*4882a593Smuzhiyun extern void free_mp_priv(struct mp_priv *pmp_priv); 679*4882a593Smuzhiyun extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); 680*4882a593Smuzhiyun extern void MPT_DeInitAdapter(PADAPTER padapter); 681*4882a593Smuzhiyun extern s32 mp_start_test(PADAPTER padapter); 682*4882a593Smuzhiyun extern void mp_stop_test(PADAPTER padapter); 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); 685*4882a593Smuzhiyun extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); 686*4882a593Smuzhiyun 687*4882a593Smuzhiyun extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); 688*4882a593Smuzhiyun extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); 689*4882a593Smuzhiyun extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); 690*4882a593Smuzhiyun extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); 691*4882a593Smuzhiyun extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); 692*4882a593Smuzhiyun extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); 693*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY 694*4882a593Smuzhiyun u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain); 695*4882a593Smuzhiyun #endif 696*4882a593Smuzhiyun void SetChannel(PADAPTER pAdapter); 697*4882a593Smuzhiyun void SetBandwidth(PADAPTER pAdapter); 698*4882a593Smuzhiyun int SetTxPower(PADAPTER pAdapter); 699*4882a593Smuzhiyun void SetAntenna(PADAPTER pAdapter); 700*4882a593Smuzhiyun void SetDataRate(PADAPTER pAdapter); 701*4882a593Smuzhiyun void SetAntenna(PADAPTER pAdapter); 702*4882a593Smuzhiyun s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); 703*4882a593Smuzhiyun void GetThermalMeter(PADAPTER pAdapter, u8 rfpath ,u8 *value); 704*4882a593Smuzhiyun void SetContinuousTx(PADAPTER pAdapter, u8 bStart); 705*4882a593Smuzhiyun void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); 706*4882a593Smuzhiyun void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); 707*4882a593Smuzhiyun void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); 708*4882a593Smuzhiyun void PhySetTxPowerLevel(PADAPTER pAdapter); 709*4882a593Smuzhiyun void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc); 710*4882a593Smuzhiyun void SetPacketTx(PADAPTER padapter); 711*4882a593Smuzhiyun void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB); 712*4882a593Smuzhiyun void ResetPhyRxPktCount(PADAPTER pAdapter); 713*4882a593Smuzhiyun u32 GetPhyRxPktReceived(PADAPTER pAdapter); 714*4882a593Smuzhiyun u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); 715*4882a593Smuzhiyun s32 SetPowerTracking(PADAPTER padapter, u8 enable); 716*4882a593Smuzhiyun void GetPowerTracking(PADAPTER padapter, u8 *enable); 717*4882a593Smuzhiyun u32 mp_query_psd(PADAPTER pAdapter, u8 *data); 718*4882a593Smuzhiyun void rtw_mp_trigger_iqk(PADAPTER padapter); 719*4882a593Smuzhiyun void rtw_mp_trigger_lck(PADAPTER padapter); 720*4882a593Smuzhiyun void rtw_mp_trigger_dpk(PADAPTER padapter); 721*4882a593Smuzhiyun u8 rtw_mp_mode_check(PADAPTER padapter); 722*4882a593Smuzhiyun bool rtw_is_mp_tssitrk_on(_adapter *adapter); 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun void hal_mpt_SwitchRfSetting(PADAPTER pAdapter); 725*4882a593Smuzhiyun s32 hal_mpt_SetPowerTracking(PADAPTER padapter, u8 enable); 726*4882a593Smuzhiyun void hal_mpt_GetPowerTracking(PADAPTER padapter, u8 *enable); 727*4882a593Smuzhiyun void hal_mpt_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); 728*4882a593Smuzhiyun void hal_mpt_SetChannel(PADAPTER pAdapter); 729*4882a593Smuzhiyun void hal_mpt_SetBandwidth(PADAPTER pAdapter); 730*4882a593Smuzhiyun void hal_mpt_SetTxPower(PADAPTER pAdapter); 731*4882a593Smuzhiyun void hal_mpt_SetDataRate(PADAPTER pAdapter); 732*4882a593Smuzhiyun void hal_mpt_SetAntenna(PADAPTER pAdapter); 733*4882a593Smuzhiyun s32 hal_mpt_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); 734*4882a593Smuzhiyun void hal_mpt_TriggerRFThermalMeter(PADAPTER pAdapter); 735*4882a593Smuzhiyun u8 hal_mpt_ReadRFThermalMeter(PADAPTER pAdapter, u8 rf_path); 736*4882a593Smuzhiyun void hal_mpt_GetThermalMeter(PADAPTER pAdapter, u8 rfpath, u8 *value); 737*4882a593Smuzhiyun void hal_mpt_SetContinuousTx(PADAPTER pAdapter, u8 bStart); 738*4882a593Smuzhiyun void hal_mpt_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); 739*4882a593Smuzhiyun void hal_mpt_SetSingleToneTx(PADAPTER pAdapter, u8 bStart); 740*4882a593Smuzhiyun void hal_mpt_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); 741*4882a593Smuzhiyun u8 mpt_ProSetPMacTx(PADAPTER Adapter); 742*4882a593Smuzhiyun void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain); 743*4882a593Smuzhiyun void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate); 744*4882a593Smuzhiyun u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter); 745*4882a593Smuzhiyun u32 mpt_ProQueryCalTxPower(PADAPTER pAdapter, u8 RfPath); 746*4882a593Smuzhiyun void MPT_PwrCtlDM(PADAPTER padapter, u32 trk_type); 747*4882a593Smuzhiyun u8 mpt_to_mgnt_rate(u32 MptRateIdx); 748*4882a593Smuzhiyun u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr); 749*4882a593Smuzhiyun u32 mp_join(PADAPTER padapter, u8 mode); 750*4882a593Smuzhiyun u32 hal_mpt_query_phytxok(PADAPTER pAdapter); 751*4882a593Smuzhiyun u32 mpt_get_tx_power_finalabs_val(PADAPTER padapter, u8 rf_path); 752*4882a593Smuzhiyun void mpt_trigger_tssi_tracking(PADAPTER pAdapter, u8 rf_path); 753*4882a593Smuzhiyun u32 hal_mpt_tssi_turn_target_power(PADAPTER padapter, s16 power_offset, u8 path); 754*4882a593Smuzhiyun s16 hal_mpt_get_tx_power_mdbm(_adapter *padapter, u8 rf_path); 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun 757*4882a593Smuzhiyun void 758*4882a593Smuzhiyun PMAC_Get_Pkt_Param( 759*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 760*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo 761*4882a593Smuzhiyun ); 762*4882a593Smuzhiyun void 763*4882a593Smuzhiyun CCK_generator( 764*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 765*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo 766*4882a593Smuzhiyun ); 767*4882a593Smuzhiyun void 768*4882a593Smuzhiyun PMAC_Nsym_generator( 769*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 770*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo 771*4882a593Smuzhiyun ); 772*4882a593Smuzhiyun void 773*4882a593Smuzhiyun L_SIG_generator( 774*4882a593Smuzhiyun u32 N_SYM, /* Max: 750*/ 775*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 776*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo 777*4882a593Smuzhiyun ); 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun void HT_SIG_generator( 780*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 781*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo); 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun void VHT_SIG_A_generator( 784*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo, 785*4882a593Smuzhiyun PRT_PMAC_PKT_INFO pPMacPktInfo); 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun void VHT_SIG_B_generator( 788*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo); 789*4882a593Smuzhiyun 790*4882a593Smuzhiyun void VHT_Delimiter_generator( 791*4882a593Smuzhiyun PRT_PMAC_TX_INFO pPMacTxInfo); 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun int rtw_mp_write_reg(struct net_device *dev, 795*4882a593Smuzhiyun struct iw_request_info *info, 796*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 797*4882a593Smuzhiyun int rtw_mp_read_reg(struct net_device *dev, 798*4882a593Smuzhiyun struct iw_request_info *info, 799*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 800*4882a593Smuzhiyun int rtw_mp_write_rf(struct net_device *dev, 801*4882a593Smuzhiyun struct iw_request_info *info, 802*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 803*4882a593Smuzhiyun int rtw_mp_read_rf(struct net_device *dev, 804*4882a593Smuzhiyun struct iw_request_info *info, 805*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 806*4882a593Smuzhiyun int rtw_mp_start(struct net_device *dev, 807*4882a593Smuzhiyun struct iw_request_info *info, 808*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 809*4882a593Smuzhiyun int rtw_mp_stop(struct net_device *dev, 810*4882a593Smuzhiyun struct iw_request_info *info, 811*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 812*4882a593Smuzhiyun int rtw_mp_rate(struct net_device *dev, 813*4882a593Smuzhiyun struct iw_request_info *info, 814*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 815*4882a593Smuzhiyun int rtw_mp_channel(struct net_device *dev, 816*4882a593Smuzhiyun struct iw_request_info *info, 817*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 818*4882a593Smuzhiyun int rtw_mp_ch_offset(struct net_device *dev, 819*4882a593Smuzhiyun struct iw_request_info *info, 820*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 821*4882a593Smuzhiyun int rtw_mp_bandwidth(struct net_device *dev, 822*4882a593Smuzhiyun struct iw_request_info *info, 823*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 824*4882a593Smuzhiyun int rtw_mp_txpower_index(struct net_device *dev, 825*4882a593Smuzhiyun struct iw_request_info *info, 826*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 827*4882a593Smuzhiyun int rtw_mp_txpower(struct net_device *dev, 828*4882a593Smuzhiyun struct iw_request_info *info, 829*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 830*4882a593Smuzhiyun int rtw_mp_txpower(struct net_device *dev, 831*4882a593Smuzhiyun struct iw_request_info *info, 832*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 833*4882a593Smuzhiyun int rtw_mp_ant_tx(struct net_device *dev, 834*4882a593Smuzhiyun struct iw_request_info *info, 835*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 836*4882a593Smuzhiyun int rtw_mp_ant_rx(struct net_device *dev, 837*4882a593Smuzhiyun struct iw_request_info *info, 838*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 839*4882a593Smuzhiyun int rtw_set_ctx_destAddr(struct net_device *dev, 840*4882a593Smuzhiyun struct iw_request_info *info, 841*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 842*4882a593Smuzhiyun int rtw_mp_ctx(struct net_device *dev, 843*4882a593Smuzhiyun struct iw_request_info *info, 844*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 845*4882a593Smuzhiyun int rtw_mp_disable_bt_coexist(struct net_device *dev, 846*4882a593Smuzhiyun struct iw_request_info *info, 847*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 848*4882a593Smuzhiyun int rtw_mp_disable_bt_coexist(struct net_device *dev, 849*4882a593Smuzhiyun struct iw_request_info *info, 850*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 851*4882a593Smuzhiyun int rtw_mp_arx(struct net_device *dev, 852*4882a593Smuzhiyun struct iw_request_info *info, 853*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 854*4882a593Smuzhiyun int rtw_mp_trx_query(struct net_device *dev, 855*4882a593Smuzhiyun struct iw_request_info *info, 856*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 857*4882a593Smuzhiyun int rtw_mp_pwrtrk(struct net_device *dev, 858*4882a593Smuzhiyun struct iw_request_info *info, 859*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 860*4882a593Smuzhiyun int rtw_mp_psd(struct net_device *dev, 861*4882a593Smuzhiyun struct iw_request_info *info, 862*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 863*4882a593Smuzhiyun int rtw_mp_thermal(struct net_device *dev, 864*4882a593Smuzhiyun struct iw_request_info *info, 865*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 866*4882a593Smuzhiyun int rtw_mp_reset_stats(struct net_device *dev, 867*4882a593Smuzhiyun struct iw_request_info *info, 868*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 869*4882a593Smuzhiyun int rtw_mp_dump(struct net_device *dev, 870*4882a593Smuzhiyun struct iw_request_info *info, 871*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 872*4882a593Smuzhiyun int rtw_mp_phypara(struct net_device *dev, 873*4882a593Smuzhiyun struct iw_request_info *info, 874*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 875*4882a593Smuzhiyun int rtw_mp_SetRFPath(struct net_device *dev, 876*4882a593Smuzhiyun struct iw_request_info *info, 877*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 878*4882a593Smuzhiyun int rtw_mp_switch_rf_path(struct net_device *dev, 879*4882a593Smuzhiyun struct iw_request_info *info, 880*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 881*4882a593Smuzhiyun int rtw_mp_link(struct net_device *dev, 882*4882a593Smuzhiyun struct iw_request_info *info, 883*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 884*4882a593Smuzhiyun int rtw_mp_QueryDrv(struct net_device *dev, 885*4882a593Smuzhiyun struct iw_request_info *info, 886*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 887*4882a593Smuzhiyun int rtw_mp_PwrCtlDM(struct net_device *dev, 888*4882a593Smuzhiyun struct iw_request_info *info, 889*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 890*4882a593Smuzhiyun int rtw_mp_getver(struct net_device *dev, 891*4882a593Smuzhiyun struct iw_request_info *info, 892*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 893*4882a593Smuzhiyun int rtw_mp_mon(struct net_device *dev, 894*4882a593Smuzhiyun struct iw_request_info *info, 895*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 896*4882a593Smuzhiyun int rtw_mp_pwrlmt(struct net_device *dev, 897*4882a593Smuzhiyun struct iw_request_info *info, 898*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 899*4882a593Smuzhiyun int rtw_mp_pwrbyrate(struct net_device *dev, 900*4882a593Smuzhiyun struct iw_request_info *info, 901*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 902*4882a593Smuzhiyun int rtw_mp_dpk_track(struct net_device *dev, 903*4882a593Smuzhiyun struct iw_request_info *info, 904*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 905*4882a593Smuzhiyun int rtw_mp_dpk(struct net_device *dev, 906*4882a593Smuzhiyun struct iw_request_info *info, 907*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 908*4882a593Smuzhiyun int rtw_efuse_mask_file(struct net_device *dev, 909*4882a593Smuzhiyun struct iw_request_info *info, 910*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 911*4882a593Smuzhiyun int rtw_bt_efuse_mask_file(struct net_device *dev, 912*4882a593Smuzhiyun struct iw_request_info *info, 913*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 914*4882a593Smuzhiyun int rtw_efuse_file_map(struct net_device *dev, 915*4882a593Smuzhiyun struct iw_request_info *info, 916*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 917*4882a593Smuzhiyun #if !defined(CONFIG_RTW_ANDROID_GKI) 918*4882a593Smuzhiyun int rtw_efuse_file_map_store(struct net_device *dev, 919*4882a593Smuzhiyun struct iw_request_info *info, 920*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 921*4882a593Smuzhiyun #endif /* !defined(CONFIG_RTW_ANDROID_GKI) */ 922*4882a593Smuzhiyun int rtw_bt_efuse_file_map(struct net_device *dev, 923*4882a593Smuzhiyun struct iw_request_info *info, 924*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 925*4882a593Smuzhiyun int rtw_mp_SetBT(struct net_device *dev, 926*4882a593Smuzhiyun struct iw_request_info *info, 927*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 928*4882a593Smuzhiyun int rtw_mp_pretx_proc(PADAPTER padapter, u8 bStartTest, char *extra); 929*4882a593Smuzhiyun int rtw_mp_tx(struct net_device *dev, 930*4882a593Smuzhiyun struct iw_request_info *info, 931*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 932*4882a593Smuzhiyun int rtw_mp_rx(struct net_device *dev, 933*4882a593Smuzhiyun struct iw_request_info *info, 934*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 935*4882a593Smuzhiyun int rtw_mp_hwtx(struct net_device *dev, 936*4882a593Smuzhiyun struct iw_request_info *info, 937*4882a593Smuzhiyun union iwreq_data *wrqu, char *extra); 938*4882a593Smuzhiyun u8 HwRateToMPTRate(u8 rate); 939*4882a593Smuzhiyun int rtw_mp_iqk(struct net_device *dev, 940*4882a593Smuzhiyun struct iw_request_info *info, 941*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 942*4882a593Smuzhiyun int rtw_mp_lck(struct net_device *dev, 943*4882a593Smuzhiyun struct iw_request_info *info, 944*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 945*4882a593Smuzhiyun int rtw_mp_get_tsside(struct net_device *dev, 946*4882a593Smuzhiyun struct iw_request_info *info, 947*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 948*4882a593Smuzhiyun int rtw_mp_set_tsside(struct net_device *dev, 949*4882a593Smuzhiyun struct iw_request_info *info, 950*4882a593Smuzhiyun struct iw_point *wrqu, char *extra); 951*4882a593Smuzhiyun #endif /* _RTW_MP_H_ */ 952