1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2013 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8821A_SPEC_H__ 16*4882a593Smuzhiyun #define __RTL8821A_SPEC_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <drv_conf.h> 19*4882a593Smuzhiyun /* This file should based on "hal_com_reg.h" */ 20*4882a593Smuzhiyun #include <hal_com_reg.h> 21*4882a593Smuzhiyun /* Because 8812a and 8821a is the same serial, 22*4882a593Smuzhiyun * most of 8821a register definitions are the same as 8812a. */ 23*4882a593Smuzhiyun #include <rtl8812a_spec.h> 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* ************************************************************ 27*4882a593Smuzhiyun * 8821A Regsiter offset definition 28*4882a593Smuzhiyun * ************************************************************ */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun /* ************************************************************ 31*4882a593Smuzhiyun * MAC register 32*4882a593Smuzhiyun * ************************************************************ */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* ----------------------------------------------------- 35*4882a593Smuzhiyun * 0x0000h ~ 0x00FFh System Configuration 36*4882a593Smuzhiyun * ----------------------------------------------------- */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* ----------------------------------------------------- 39*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 40*4882a593Smuzhiyun * ----------------------------------------------------- */ 41*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* ----------------------------------------------------- 44*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 45*4882a593Smuzhiyun * ----------------------------------------------------- */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* ----------------------------------------------------- 48*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 49*4882a593Smuzhiyun * ----------------------------------------------------- */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* ----------------------------------------------------- 52*4882a593Smuzhiyun * 0x0300h ~ 0x03FFh PCIe 53*4882a593Smuzhiyun * ----------------------------------------------------- */ 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* ----------------------------------------------------- 56*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 57*4882a593Smuzhiyun * ----------------------------------------------------- */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* ----------------------------------------------------- 60*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 61*4882a593Smuzhiyun * ----------------------------------------------------- */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* ----------------------------------------------------- 64*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 65*4882a593Smuzhiyun * ----------------------------------------------------- */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* ************************************************************ 69*4882a593Smuzhiyun * SDIO Bus Specification 70*4882a593Smuzhiyun * ************************************************************ */ 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* ----------------------------------------------------- 73*4882a593Smuzhiyun * SDIO CMD Address Mapping 74*4882a593Smuzhiyun * ----------------------------------------------------- */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* ----------------------------------------------------- 77*4882a593Smuzhiyun * I/O bus domain (Host) 78*4882a593Smuzhiyun * ----------------------------------------------------- */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* ----------------------------------------------------- 81*4882a593Smuzhiyun * SDIO register 82*4882a593Smuzhiyun * ----------------------------------------------------- */ 83*4882a593Smuzhiyun #define SDIO_REG_FREE_TXPG2 0x024 84*4882a593Smuzhiyun #define SDIO_REG_HCPWM1_8821A 0x025 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* ************************************************************ 87*4882a593Smuzhiyun * Regsiter Bit and Content definition 88*4882a593Smuzhiyun * ************************************************************ */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif /* __RTL8821A_SPEC_H__ */ 91