1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2019 - 2021 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef _RTL8723F_HAL_H_ 16*4882a593Smuzhiyun #define _RTL8723F_HAL_H_ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <osdep_service.h> /* BIT(x) */ 19*4882a593Smuzhiyun #include <drv_types.h> /* PADAPTER */ 20*4882a593Smuzhiyun #include "../hal/halmac-rs/halmac_api.h" /* MAC REG definition */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define MAX_RECVBUF_SZ 16384 /* 16KB (RX_FIFO_SIZE_8723F), TX: 32KB */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * MAC Register definition 26*4882a593Smuzhiyun */ 27*4882a593Smuzhiyun #define REG_LEDCFG0 REG_LED_CFG_8723F /* rtw_mp.c */ 28*4882a593Smuzhiyun #define MSR (REG_CR_8723F + 2) /* rtw_mp.c & hal_com.c */ 29*4882a593Smuzhiyun #define MSR1 REG_CR_EXT_8723F /* rtw_mp.c & hal_com.c */ 30*4882a593Smuzhiyun #define REG_C2HEVT_MSG_NORMAL 0x1A0 /* hal_com.c */ 31*4882a593Smuzhiyun #define REG_C2HEVT_CLEAR 0x1AF /* hal_com.c */ 32*4882a593Smuzhiyun #define REG_BCN_CTRL_1 REG_BCN_CTRL_CLINT0_8723F /* hal_com.c */ 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON 0x01C7 /* hal_com.c */ 35*4882a593Smuzhiyun #define REG_GPIO_PIN_CTRL_2 REG_GPIO_EXT_CTRL_8723F /* hal_com.c */ 36*4882a593Smuzhiyun #define REG_FIFOPAGE REG_FIFOPAGE_INFO_8723F /* hal_com.c */ 37*4882a593Smuzhiyun #define REG_RXPKTBUF_CTRL REG_PKTBUF_DBG_CTRL_8723F /* hal_com.c */ 38*4882a593Smuzhiyun #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD_8723F /* hal_com.c */ 39*4882a593Smuzhiyun #define REG_RSV_CTRL REG_REG_ACCESS_CTRL_8723F /* hal_com.c */ 40*4882a593Smuzhiyun #define REG_CAMCMD REG_KEYCAMCMD_8723F /* hal_com.c */ 41*4882a593Smuzhiyun #define REG_CAMWRITE REG_KEYCAM_WD_8723F /* hal_com.c */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define BIT_AUTO_SYNC_BY_TBTT BIT_EN_TSFAUTO_SYNC_8723F /* hal_com.c */ 44*4882a593Smuzhiyun #define BIT_DIS_ATIM_ROOT_8723F 23 /* REG_HIQ_NO_LMT_EN_V2[23], disable ATIM ROOT */ 45*4882a593Smuzhiyun #define BIT_SECCAM_POLLING_8723F BIT_KEYCAM_POLLING_8723F /* rtl8723f_ops.c */ 46*4882a593Smuzhiyun #define BIT_GET_NETYPE2 BIT_GET_P2_NETSTATE_8723F /* hal_halmac.c */ 47*4882a593Smuzhiyun #define BIT_GET_NETYPE3 BIT_GET_P3_NETSTATE_8723F /* hal_halmac.c */ 48*4882a593Smuzhiyun #define BIT_GET_NETYPE4 BIT_GET_P4_NETSTATE_8723F /* hal_halmac.c */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #ifdef CONFIG_WOW_PATTERN_IN_TXFIFO 51*4882a593Smuzhiyun #define WKCAM_OFFSET_BIT_MASK 0xFFF 52*4882a593Smuzhiyun #define WKCAM_OFFSET_BIT_MASK_OFFSET 12 53*4882a593Smuzhiyun #define REG_TXBUF_WKCAM_OFFSET 0x1B4 //BIT_TXBUF_WKCAM_OFFSET [24:12] 54*4882a593Smuzhiyun #define REG_PKT_BUFF_ACCESS_CTRL 0x106 /* hal_com.c */ 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* RXERR_RPT, for rtw_mp.c */ 58*4882a593Smuzhiyun #define RXERR_TYPE_OFDM_PPDU 0 59*4882a593Smuzhiyun #define RXERR_TYPE_OFDM_FALSE_ALARM 2 60*4882a593Smuzhiyun #define RXERR_TYPE_OFDM_MPDU_OK 0 61*4882a593Smuzhiyun #define RXERR_TYPE_OFDM_MPDU_FAIL 1 62*4882a593Smuzhiyun #define RXERR_TYPE_CCK_PPDU 3 63*4882a593Smuzhiyun #define RXERR_TYPE_CCK_FALSE_ALARM 5 64*4882a593Smuzhiyun #define RXERR_TYPE_CCK_MPDU_OK 3 65*4882a593Smuzhiyun #define RXERR_TYPE_CCK_MPDU_FAIL 4 66*4882a593Smuzhiyun #define RXERR_TYPE_HT_PPDU 8 67*4882a593Smuzhiyun #define RXERR_TYPE_HT_FALSE_ALARM 9 68*4882a593Smuzhiyun #define RXERR_TYPE_HT_MPDU_TOTAL 6 69*4882a593Smuzhiyun #define RXERR_TYPE_HT_MPDU_OK 6 70*4882a593Smuzhiyun #define RXERR_TYPE_HT_MPDU_FAIL 7 71*4882a593Smuzhiyun #define RXERR_TYPE_RX_FULL_DROP 10 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define RXERR_COUNTER_MASK BIT_MASK_RPT_COUNTER_8723F 74*4882a593Smuzhiyun #define RXERR_RPT_RST BIT_RXERR_RPT_RST_8723F 75*4882a593Smuzhiyun #define _RXERR_RPT_SEL(type) (BIT_RXERR_RPT_SEL_V1_3_0_8723F(type) \ 76*4882a593Smuzhiyun | ((type & 0x10) ? BIT_RXERR_RPT_SEL_V1_4_8723F : 0)) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* 79*4882a593Smuzhiyun * BB Register definition 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun #define rPMAC_Reset 0x100 /* hal_mp.c */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define rFPGA0_RFMOD 0x800 84*4882a593Smuzhiyun #define rFPGA0_TxInfo 0x804 85*4882a593Smuzhiyun #define rOFDMCCKEN_Jaguar 0x808 /* hal_mp.c */ 86*4882a593Smuzhiyun #define rFPGA0_TxGainStage 0x80C /* phydm only */ 87*4882a593Smuzhiyun #define rFPGA0_XA_HSSIParameter1 0x820 /* hal_mp.c */ 88*4882a593Smuzhiyun #define rFPGA0_XA_HSSIParameter2 0x824 /* hal_mp.c */ 89*4882a593Smuzhiyun #define rFPGA0_XB_HSSIParameter1 0x828 /* hal_mp.c */ 90*4882a593Smuzhiyun #define rFPGA0_XB_HSSIParameter2 0x82C /* hal_mp.c */ 91*4882a593Smuzhiyun #define rTxAGC_B_Rate18_06 0x830 92*4882a593Smuzhiyun #define rTxAGC_B_Rate54_24 0x834 93*4882a593Smuzhiyun #define rTxAGC_B_CCK1_55_Mcs32 0x838 94*4882a593Smuzhiyun #define rCCAonSec_Jaguar 0x838 /* hal_mp.c */ 95*4882a593Smuzhiyun #define rTxAGC_B_Mcs03_Mcs00 0x83C 96*4882a593Smuzhiyun #define rTxAGC_B_Mcs07_Mcs04 0x848 97*4882a593Smuzhiyun #define rTxAGC_B_Mcs11_Mcs08 0x84C 98*4882a593Smuzhiyun #define rFPGA0_XA_RFInterfaceOE 0x860 99*4882a593Smuzhiyun #define rFPGA0_XB_RFInterfaceOE 0x864 100*4882a593Smuzhiyun #define rTxAGC_B_Mcs15_Mcs12 0x868 101*4882a593Smuzhiyun #define rTxAGC_B_CCK11_A_CCK2_11 0x86C 102*4882a593Smuzhiyun #define rFPGA0_XAB_RFInterfaceSW 0x870 103*4882a593Smuzhiyun #define rFPGA0_XAB_RFParameter 0x878 104*4882a593Smuzhiyun #define rFPGA0_AnalogParameter4 0x88C /* hal_mp.c & phydm */ 105*4882a593Smuzhiyun #define rFPGA0_XB_LSSIReadBack 0x8A4 /* phydm */ 106*4882a593Smuzhiyun #define rHSSIRead_Jaguar 0x8B0 /* RF read addr (rtl8723f_phy.c) */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun #define rC_TxScale_Jaguar2 0x181C /* Pah_C TX scaling factor (hal_mp.c) */ 109*4882a593Smuzhiyun #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C (hal_mp.c) */ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define rFPGA1_TxInfo 0x90C /* hal_mp.c */ 112*4882a593Smuzhiyun #define rSingleTone_ContTx_Jaguar 0x914 /* hal_mp.c */ 113*4882a593Smuzhiyun /* TX BeamForming */ 114*4882a593Smuzhiyun #define REG_BB_TX_PATH_SEL_1_8723F 0x93C /* rtl8723f_phy.c */ 115*4882a593Smuzhiyun #define REG_BB_TX_PATH_SEL_2_8723F 0x940 /* rtl8723f_phy.c */ 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* TX BeamForming */ 118*4882a593Smuzhiyun #define REG_BB_TXBF_ANT_SET_BF1_8723F 0x19AC /* rtl8723f_phy.c */ 119*4882a593Smuzhiyun #define REG_BB_TXBF_ANT_SET_BF0_8723F 0x19B4 /* rtl8723f_phy.c */ 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define rCCK0_System 0xA00 122*4882a593Smuzhiyun #define rCCK0_AFESetting 0xA04 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define rCCK0_DSPParameter2 0xA1C 125*4882a593Smuzhiyun #define rCCK0_TxFilter1 0xA20 126*4882a593Smuzhiyun #define rCCK0_TxFilter2 0xA24 127*4882a593Smuzhiyun #define rCCK0_DebugPort 0xA28 128*4882a593Smuzhiyun #define rCCK0_FalseAlarmReport 0xA2C 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun #define rD_TxScale_Jaguar2 0x1A1C /* Path_D TX scaling factor (hal_mp.c) */ 131*4882a593Smuzhiyun #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D (hal_mp.c) */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define rOFDM0_TRxPathEnable 0xC04 134*4882a593Smuzhiyun #define rOFDM0_TRMuxPar 0xC08 135*4882a593Smuzhiyun #define rA_TxScale_Jaguar 0xC1C /* Pah_A TX scaling factor (hal_mp.c) */ 136*4882a593Smuzhiyun #define rOFDM0_RxDetector1 0xC30 /* rtw_mp.c */ 137*4882a593Smuzhiyun #define rOFDM0_ECCAThreshold 0xC4C /* phydm only */ 138*4882a593Smuzhiyun #define rOFDM0_XAAGCCore1 0xC50 /* phydm only */ 139*4882a593Smuzhiyun #define rA_IGI_Jaguar 0xC50 /* Initial Gain for path-A (hal_mp.c) */ 140*4882a593Smuzhiyun #define rOFDM0_XBAGCCore1 0xC58 /* phydm only */ 141*4882a593Smuzhiyun #define rOFDM0_XATxIQImbalance 0xC80 /* phydm only */ 142*4882a593Smuzhiyun #define rA_LSSIWrite_Jaguar 0xC90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define rOFDM1_LSTF 0xD00 145*4882a593Smuzhiyun #define rOFDM1_TRxPathEnable 0xD04 /* hal_mp.c */ 146*4882a593Smuzhiyun #define rA_PIRead_Jaguar 0xD04 /* RF readback with PI (rtl8723f_phy.c) */ 147*4882a593Smuzhiyun #define rA_SIRead_Jaguar 0xD08 /* RF readback with SI (rtl8723f_phy.c) */ 148*4882a593Smuzhiyun #define rB_PIRead_Jaguar 0xD44 /* RF readback with PI (rtl8723f_phy.c) */ 149*4882a593Smuzhiyun #define rB_SIRead_Jaguar 0xD48 /* RF readback with SI (rtl8723f_phy.c) */ 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define rTxAGC_A_Rate18_06 0xE00 152*4882a593Smuzhiyun #define rTxAGC_A_Rate54_24 0xE04 153*4882a593Smuzhiyun #define rTxAGC_A_CCK1_Mcs32 0xE08 154*4882a593Smuzhiyun #define rTxAGC_A_Mcs03_Mcs00 0xE10 155*4882a593Smuzhiyun #define rTxAGC_A_Mcs07_Mcs04 0xE14 156*4882a593Smuzhiyun #define rTxAGC_A_Mcs11_Mcs08 0xE18 157*4882a593Smuzhiyun #define rTxAGC_A_Mcs15_Mcs12 0xE1C 158*4882a593Smuzhiyun #define rB_TxScale_Jaguar 0xE1C /* Path_B TX scaling factor (hal_mp.c) */ 159*4882a593Smuzhiyun #define rB_IGI_Jaguar 0xE50 /* Initial Gain for path-B (hal_mp.c) */ 160*4882a593Smuzhiyun #define rB_LSSIWrite_Jaguar 0xE90 /* RF write addr, LSSI Parameter (rtl8822b_phy.c) */ 161*4882a593Smuzhiyun /* RFE */ 162*4882a593Smuzhiyun #define rA_RFE_Pinmux_Jaguar 0xCB0 /* hal_mp.c */ 163*4882a593Smuzhiyun #define rB_RFE_Pinmux_Jaguar 0xEB0 /* Path_B RFE control pinmux */ 164*4882a593Smuzhiyun #define rA_RFE_Inv_Jaguar 0xCB4 /* Path_A RFE cotrol */ 165*4882a593Smuzhiyun #define rB_RFE_Inv_Jaguar 0xEB4 /* Path_B RFE control */ 166*4882a593Smuzhiyun #define rA_RFE_Jaguar 0xCB8 /* Path_A RFE cotrol */ 167*4882a593Smuzhiyun #define rB_RFE_Jaguar 0xEB8 /* Path_B RFE control */ 168*4882a593Smuzhiyun #define rA_RFE_Inverse_Jaguar 0xCBC /* Path_A RFE control inverse */ 169*4882a593Smuzhiyun #define rB_RFE_Inverse_Jaguar 0xEBC /* Path_B RFE control inverse */ 170*4882a593Smuzhiyun #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */ 171*4882a593Smuzhiyun #define bMask_RFEInv_Jaguar 0x3FF00000 172*4882a593Smuzhiyun #define bMask_AntselPathFollow_Jaguar 0x00030000 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux*/ 175*4882a593Smuzhiyun #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux*/ 176*4882a593Smuzhiyun #define rA_RFE_Sel_Jaguar2 0x1990 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* Page1(0x100) */ 179*4882a593Smuzhiyun #define bBBResetB 0x100 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun /* Page8(0x800) */ 182*4882a593Smuzhiyun #define bCCKEn 0x1000000 183*4882a593Smuzhiyun #define bOFDMEn 0x2000000 184*4882a593Smuzhiyun /* Reg 0x80C rFPGA0_TxGainStage */ 185*4882a593Smuzhiyun #define bXBTxAGC 0xF00 186*4882a593Smuzhiyun #define bXCTxAGC 0xF000 187*4882a593Smuzhiyun #define bXDTxAGC 0xF0000 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* PageA(0xA00) */ 190*4882a593Smuzhiyun #define bCCKBBMode 0x3 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define bCCKScramble 0x8 193*4882a593Smuzhiyun #define bCCKTxRate 0x3000 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* General */ 196*4882a593Smuzhiyun #define bMaskByte0 0xFF /* mp, rtw_odm.c & phydm */ 197*4882a593Smuzhiyun #define bMaskByte1 0xFF00 /* hal_mp.c & phydm */ 198*4882a593Smuzhiyun #define bMaskByte2 0xFF0000 /* hal_mp.c & phydm */ 199*4882a593Smuzhiyun #define bMaskByte3 0xFF000000 /* hal_mp.c & phydm */ 200*4882a593Smuzhiyun #define bMaskHWord 0xFFFF0000 /* hal_com.c, rtw_mp.c */ 201*4882a593Smuzhiyun #define bMaskLWord 0x0000FFFF /* mp, hal_com.c & phydm */ 202*4882a593Smuzhiyun #define bMaskDWord 0xFFFFFFFF /* mp, hal, rtw_odm.c & phydm */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define bEnable 0x1 /* hal_mp.c, rtw_mp.c */ 205*4882a593Smuzhiyun #define bDisable 0x0 /* rtw_mp.c */ 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun #define MAX_STALL_TIME 50 /* unit: us, hal_com_phycfg.c */ 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define Rx_Smooth_Factor 20 /* phydm only */ 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* 212*4882a593Smuzhiyun * RF Register definition 213*4882a593Smuzhiyun */ 214*4882a593Smuzhiyun #define RF_AC 0x00 215*4882a593Smuzhiyun #define RF_AC_Jaguar 0x00 /* hal_mp.c */ 216*4882a593Smuzhiyun #define RF_CHNLBW 0x18 /* rtl8723f_phy.c */ 217*4882a593Smuzhiyun #define RF_ModeTableAddr 0x30 /* rtl8723f_phy.c */ 218*4882a593Smuzhiyun #define RF_ModeTableData0 0x31 /* rtl8723f_phy.c */ 219*4882a593Smuzhiyun #define RF_ModeTableData1 0x32 /* rtl8723f_phy.c */ 220*4882a593Smuzhiyun #define RF_0x52 0x52 221*4882a593Smuzhiyun #define RF_WeLut_Jaguar 0xEF /* rtl8723f_phy.c */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* rtw_lps_state_chk() @hal_com.c */ 224*4882a593Smuzhiyun #define BIT_PWRBIT_OW_EN BIT_WMAC_TCR_PWRMGT_CTL_8723F 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun /* 227*4882a593Smuzhiyun * General Functions 228*4882a593Smuzhiyun */ 229*4882a593Smuzhiyun void rtl8723f_init_hal_spec(PADAPTER); /* hal/hal_com.c */ 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED 232*4882a593Smuzhiyun /* MP Functions */ 233*4882a593Smuzhiyun #include <rtw_mp.h> /* struct mp_priv */ 234*4882a593Smuzhiyun void rtl8723f_prepare_mp_txdesc(PADAPTER, struct mp_priv *); /* rtw_mp.c */ 235*4882a593Smuzhiyun void rtl8723f_mp_config_rfpath(PADAPTER); /* hal_mp.c */ 236*4882a593Smuzhiyun #endif 237*4882a593Smuzhiyun void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus); 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI 240*4882a593Smuzhiyun #include <rtl8723fu_hal.h> 241*4882a593Smuzhiyun #elif defined(CONFIG_SDIO_HCI) 242*4882a593Smuzhiyun #include <rtl8723fs_hal.h> 243*4882a593Smuzhiyun #endif 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #endif /* _RTL8723F_HAL_H_ */ 246