1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8723B_SPEC_H__ 16*4882a593Smuzhiyun #define __RTL8723B_SPEC_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <drv_conf.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* ----------------------------------------------------- 24*4882a593Smuzhiyun * 25*4882a593Smuzhiyun * 0x0000h ~ 0x00FFh System Configuration 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * ----------------------------------------------------- */ 28*4882a593Smuzhiyun #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */ 29*4882a593Smuzhiyun #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038 30*4882a593Smuzhiyun #define REG_HSISR_8723B 0x005c 31*4882a593Smuzhiyun #define REG_PAD_CTRL1_8723B 0x0064 32*4882a593Smuzhiyun #define REG_AFE_CTRL_4_8723B 0x0078 33*4882a593Smuzhiyun #define REG_HMEBOX_DBG_0_8723B 0x0088 34*4882a593Smuzhiyun #define REG_HMEBOX_DBG_1_8723B 0x008A 35*4882a593Smuzhiyun #define REG_HMEBOX_DBG_2_8723B 0x008C 36*4882a593Smuzhiyun #define REG_HMEBOX_DBG_3_8723B 0x008E 37*4882a593Smuzhiyun #define REG_HIMR0_8723B 0x00B0 38*4882a593Smuzhiyun #define REG_HISR0_8723B 0x00B4 39*4882a593Smuzhiyun #define REG_HIMR1_8723B 0x00B8 40*4882a593Smuzhiyun #define REG_HISR1_8723B 0x00BC 41*4882a593Smuzhiyun #define REG_PMC_DBG_CTRL2_8723B 0x00CC 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* ----------------------------------------------------- 44*4882a593Smuzhiyun * 45*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 46*4882a593Smuzhiyun * 47*4882a593Smuzhiyun * ----------------------------------------------------- */ 48*4882a593Smuzhiyun #define REG_C2HEVT_CMD_ID_8723B 0x01A0 49*4882a593Smuzhiyun #define REG_C2HEVT_CMD_LEN_8723B 0x01AE 50*4882a593Smuzhiyun #define REG_WOWLAN_WAKE_REASON 0x01C7 51*4882a593Smuzhiyun #define REG_WOWLAN_GTK_DBG1 0x630 52*4882a593Smuzhiyun #define REG_WOWLAN_GTK_DBG2 0x634 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun #define REG_HMEBOX_EXT0_8723B 0x01F0 55*4882a593Smuzhiyun #define REG_HMEBOX_EXT1_8723B 0x01F4 56*4882a593Smuzhiyun #define REG_HMEBOX_EXT2_8723B 0x01F8 57*4882a593Smuzhiyun #define REG_HMEBOX_EXT3_8723B 0x01FC 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* ----------------------------------------------------- 60*4882a593Smuzhiyun * 61*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 62*4882a593Smuzhiyun * 63*4882a593Smuzhiyun * ----------------------------------------------------- */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* ----------------------------------------------------- 66*4882a593Smuzhiyun * 67*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 68*4882a593Smuzhiyun * 69*4882a593Smuzhiyun * ----------------------------------------------------- */ 70*4882a593Smuzhiyun #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */ 71*4882a593Smuzhiyun #define REG_RXDMA_MODE_CTRL_8723B 0x0290 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* ----------------------------------------------------- 74*4882a593Smuzhiyun * 75*4882a593Smuzhiyun * 0x0300h ~ 0x03FFh PCIe 76*4882a593Smuzhiyun * 77*4882a593Smuzhiyun * ----------------------------------------------------- */ 78*4882a593Smuzhiyun #define REG_PCIE_CTRL_REG_8723B 0x0300 79*4882a593Smuzhiyun #define REG_INT_MIG_8723B 0x0304 /* Interrupt Migration */ 80*4882a593Smuzhiyun #define REG_BCNQ_DESA_8723B 0x0308 /* TX Beacon Descriptor Address */ 81*4882a593Smuzhiyun #define REG_HQ_DESA_8723B 0x0310 /* TX High Queue Descriptor Address */ 82*4882a593Smuzhiyun #define REG_MGQ_DESA_8723B 0x0318 /* TX Manage Queue Descriptor Address */ 83*4882a593Smuzhiyun #define REG_VOQ_DESA_8723B 0x0320 /* TX VO Queue Descriptor Address */ 84*4882a593Smuzhiyun #define REG_VIQ_DESA_8723B 0x0328 /* TX VI Queue Descriptor Address */ 85*4882a593Smuzhiyun #define REG_BEQ_DESA_8723B 0x0330 /* TX BE Queue Descriptor Address */ 86*4882a593Smuzhiyun #define REG_BKQ_DESA_8723B 0x0338 /* TX BK Queue Descriptor Address */ 87*4882a593Smuzhiyun #define REG_RX_DESA_8723B 0x0340 /* RX Queue Descriptor Address */ 88*4882a593Smuzhiyun #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */ 89*4882a593Smuzhiyun #define REG_DBI_RDATA_8723B 0x034C /* DBI Read Data */ 90*4882a593Smuzhiyun #define REG_DBI_ADDR_8723B 0x0350 /* DBI Address */ 91*4882a593Smuzhiyun #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */ 92*4882a593Smuzhiyun #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */ 93*4882a593Smuzhiyun #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */ 94*4882a593Smuzhiyun #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */ 95*4882a593Smuzhiyun #define REG_DBG_SEL_8723B 0x0360 /* Debug Selection Register */ 96*4882a593Smuzhiyun #define REG_PCIE_HRPWM_8723B 0x0361 /* PCIe RPWM */ 97*4882a593Smuzhiyun #define REG_PCIE_HCPWM_8723B 0x0363 /* PCIe CPWM */ 98*4882a593Smuzhiyun #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */ 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* ----------------------------------------------------- 101*4882a593Smuzhiyun * 102*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 103*4882a593Smuzhiyun * 104*4882a593Smuzhiyun * ----------------------------------------------------- */ 105*4882a593Smuzhiyun #define REG_TXPKTBUF_BCNQ_BDNY_8723B 0x0424 106*4882a593Smuzhiyun #define REG_TXPKTBUF_MGQ_BDNY_8723B 0x0425 107*4882a593Smuzhiyun #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B 0x045D 108*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 109*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_LOW 0x0484 110*4882a593Smuzhiyun #define REG_TXPKTBUF_IV_HIGH 0x0488 111*4882a593Smuzhiyun #endif 112*4882a593Smuzhiyun #define REG_AMPDU_BURST_MODE_8723B 0x04BC 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun /* ----------------------------------------------------- 115*4882a593Smuzhiyun * 116*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 117*4882a593Smuzhiyun * 118*4882a593Smuzhiyun * ----------------------------------------------------- */ 119*4882a593Smuzhiyun #define REG_SECONDARY_CCA_CTRL_8723B 0x0577 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* ----------------------------------------------------- 122*4882a593Smuzhiyun * 123*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 124*4882a593Smuzhiyun * 125*4882a593Smuzhiyun * ----------------------------------------------------- */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* ************************************************************ 129*4882a593Smuzhiyun * SDIO Bus Specification 130*4882a593Smuzhiyun * ************************************************************ */ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* ----------------------------------------------------- 133*4882a593Smuzhiyun * SDIO CMD Address Mapping 134*4882a593Smuzhiyun * ----------------------------------------------------- */ 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* ----------------------------------------------------- 137*4882a593Smuzhiyun * I/O bus domain (Host) 138*4882a593Smuzhiyun * ----------------------------------------------------- */ 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* ----------------------------------------------------- 141*4882a593Smuzhiyun * SDIO register 142*4882a593Smuzhiyun * ----------------------------------------------------- */ 143*4882a593Smuzhiyun #define SDIO_REG_HCPWM1_8723B 0x025 /* HCI Current Power Mode 1 */ 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* **************************************************************************** 147*4882a593Smuzhiyun * 8723 Regsiter Bit and Content definition 148*4882a593Smuzhiyun * **************************************************************************** */ 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 2 HSISR 151*4882a593Smuzhiyun * interrupt mask which needs to clear */ 152*4882a593Smuzhiyun #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\ 153*4882a593Smuzhiyun HSISR_SPS_OCP_INT |\ 154*4882a593Smuzhiyun HSISR_RON_INT |\ 155*4882a593Smuzhiyun HSISR_PDNINT |\ 156*4882a593Smuzhiyun HSISR_GPIO9_INT) 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* ----------------------------------------------------- 159*4882a593Smuzhiyun * 160*4882a593Smuzhiyun * 0x0100h ~ 0x01FFh MACTOP General Configuration 161*4882a593Smuzhiyun * 162*4882a593Smuzhiyun * ----------------------------------------------------- */ 163*4882a593Smuzhiyun #undef IS_E_CUT 164*4882a593Smuzhiyun #define IS_E_CUT(version) FALSE 165*4882a593Smuzhiyun #undef IS_F_CUT 166*4882a593Smuzhiyun #define IS_F_CUT(version) ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? TRUE : FALSE) 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun /* ----------------------------------------------------- 169*4882a593Smuzhiyun * 170*4882a593Smuzhiyun * 0x0200h ~ 0x027Fh TXDMA Configuration 171*4882a593Smuzhiyun * 172*4882a593Smuzhiyun * ----------------------------------------------------- */ 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun /* ----------------------------------------------------- 175*4882a593Smuzhiyun * 176*4882a593Smuzhiyun * 0x0280h ~ 0x02FFh RXDMA Configuration 177*4882a593Smuzhiyun * 178*4882a593Smuzhiyun * ----------------------------------------------------- */ 179*4882a593Smuzhiyun #define BIT_USB_RXDMA_AGG_EN BIT(31) 180*4882a593Smuzhiyun #define RXDMA_AGG_MODE_EN BIT(1) 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 183*4882a593Smuzhiyun #define RXPKT_RELEASE_POLL BIT(16) 184*4882a593Smuzhiyun #define RXDMA_IDLE BIT(17) 185*4882a593Smuzhiyun #define RW_RELEASE_EN BIT(18) 186*4882a593Smuzhiyun #endif 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun /* ----------------------------------------------------- 189*4882a593Smuzhiyun * 190*4882a593Smuzhiyun * 0x0400h ~ 0x047Fh Protocol Configuration 191*4882a593Smuzhiyun * 192*4882a593Smuzhiyun * ----------------------------------------------------- */ 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 195*4882a593Smuzhiyun * 8723B REG_CCK_CHECK (offset 0x454) 196*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 197*4882a593Smuzhiyun #define BIT_BCN_PORT_SEL BIT(5) 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* ----------------------------------------------------- 200*4882a593Smuzhiyun * 201*4882a593Smuzhiyun * 0x0500h ~ 0x05FFh EDCA Configuration 202*4882a593Smuzhiyun * 203*4882a593Smuzhiyun * ----------------------------------------------------- */ 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* ----------------------------------------------------- 206*4882a593Smuzhiyun * 207*4882a593Smuzhiyun * 0x0600h ~ 0x07FFh WMAC Configuration 208*4882a593Smuzhiyun * 209*4882a593Smuzhiyun * ----------------------------------------------------- */ 210*4882a593Smuzhiyun #ifdef CONFIG_RF_POWER_TRIM 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun #ifdef CONFIG_RTL8723B 213*4882a593Smuzhiyun #define EEPROM_RF_GAIN_OFFSET 0xC1 214*4882a593Smuzhiyun #endif 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define EEPROM_RF_GAIN_VAL 0x1F6 217*4882a593Smuzhiyun #endif /*CONFIG_RF_POWER_TRIM*/ 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /* ---------------------------------------------------------------------------- 221*4882a593Smuzhiyun * 8195 IMR/ISR bits (offset 0xB0, 8bits) 222*4882a593Smuzhiyun * ---------------------------------------------------------------------------- */ 223*4882a593Smuzhiyun #define IMR_DISABLED_8723B 0 224*4882a593Smuzhiyun /* IMR DW0(0x00B0-00B3) Bit 0-31 */ 225*4882a593Smuzhiyun #define IMR_TIMER2_8723B BIT(31) /* Timeout interrupt 2 */ 226*4882a593Smuzhiyun #define IMR_TIMER1_8723B BIT(30) /* Timeout interrupt 1 */ 227*4882a593Smuzhiyun #define IMR_PSTIMEOUT_8723B BIT(29) /* Power Save Time Out Interrupt */ 228*4882a593Smuzhiyun #define IMR_GTINT4_8723B BIT(28) /* When GTIMER4 expires, this bit is set to 1 */ 229*4882a593Smuzhiyun #define IMR_GTINT3_8723B BIT(27) /* When GTIMER3 expires, this bit is set to 1 */ 230*4882a593Smuzhiyun #define IMR_TXBCN0ERR_8723B BIT(26) /* Transmit Beacon0 Error */ 231*4882a593Smuzhiyun #define IMR_TXBCN0OK_8723B BIT(25) /* Transmit Beacon0 OK */ 232*4882a593Smuzhiyun #define IMR_TSF_BIT32_TOGGLE_8723B BIT(24) /* TSF Timer BIT(32) toggle indication interrupt */ 233*4882a593Smuzhiyun #define IMR_BCNDMAINT0_8723B BIT(20) /* Beacon DMA Interrupt 0 */ 234*4882a593Smuzhiyun #define IMR_BCNDERR0_8723B BIT(16) /* Beacon Queue DMA OK0 */ 235*4882a593Smuzhiyun #define IMR_HSISR_IND_ON_INT_8723B BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 236*4882a593Smuzhiyun #define IMR_BCNDMAINT_E_8723B BIT(14) /* Beacon DMA Interrupt Extension for Win7 */ 237*4882a593Smuzhiyun #define IMR_ATIMEND_8723B BIT(12) /* CTWidnow End or ATIM Window End */ 238*4882a593Smuzhiyun #define IMR_C2HCMD_8723B BIT(10) /* CPU to Host Command INT Status, Write 1 clear */ 239*4882a593Smuzhiyun #define IMR_CPWM2_8723B BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */ 240*4882a593Smuzhiyun #define IMR_CPWM_8723B BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */ 241*4882a593Smuzhiyun #define IMR_HIGHDOK_8723B BIT(7) /* High Queue DMA OK */ 242*4882a593Smuzhiyun #define IMR_MGNTDOK_8723B BIT(6) /* Management Queue DMA OK */ 243*4882a593Smuzhiyun #define IMR_BKDOK_8723B BIT(5) /* AC_BK DMA OK */ 244*4882a593Smuzhiyun #define IMR_BEDOK_8723B BIT(4) /* AC_BE DMA OK */ 245*4882a593Smuzhiyun #define IMR_VIDOK_8723B BIT(3) /* AC_VI DMA OK */ 246*4882a593Smuzhiyun #define IMR_VODOK_8723B BIT(2) /* AC_VO DMA OK */ 247*4882a593Smuzhiyun #define IMR_RDU_8723B BIT(1) /* Rx Descriptor Unavailable */ 248*4882a593Smuzhiyun #define IMR_ROK_8723B BIT(0) /* Receive DMA OK */ 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 251*4882a593Smuzhiyun #define IMR_BCNDMAINT7_8723B BIT(27) /* Beacon DMA Interrupt 7 */ 252*4882a593Smuzhiyun #define IMR_BCNDMAINT6_8723B BIT(26) /* Beacon DMA Interrupt 6 */ 253*4882a593Smuzhiyun #define IMR_BCNDMAINT5_8723B BIT(25) /* Beacon DMA Interrupt 5 */ 254*4882a593Smuzhiyun #define IMR_BCNDMAINT4_8723B BIT(24) /* Beacon DMA Interrupt 4 */ 255*4882a593Smuzhiyun #define IMR_BCNDMAINT3_8723B BIT(23) /* Beacon DMA Interrupt 3 */ 256*4882a593Smuzhiyun #define IMR_BCNDMAINT2_8723B BIT(22) /* Beacon DMA Interrupt 2 */ 257*4882a593Smuzhiyun #define IMR_BCNDMAINT1_8723B BIT(21) /* Beacon DMA Interrupt 1 */ 258*4882a593Smuzhiyun #define IMR_BCNDOK7_8723B BIT(20) /* Beacon Queue DMA OK Interrupt 7 */ 259*4882a593Smuzhiyun #define IMR_BCNDOK6_8723B BIT(19) /* Beacon Queue DMA OK Interrupt 6 */ 260*4882a593Smuzhiyun #define IMR_BCNDOK5_8723B BIT(18) /* Beacon Queue DMA OK Interrupt 5 */ 261*4882a593Smuzhiyun #define IMR_BCNDOK4_8723B BIT(17) /* Beacon Queue DMA OK Interrupt 4 */ 262*4882a593Smuzhiyun #define IMR_BCNDOK3_8723B BIT(16) /* Beacon Queue DMA OK Interrupt 3 */ 263*4882a593Smuzhiyun #define IMR_BCNDOK2_8723B BIT(15) /* Beacon Queue DMA OK Interrupt 2 */ 264*4882a593Smuzhiyun #define IMR_BCNDOK1_8723B BIT(14) /* Beacon Queue DMA OK Interrupt 1 */ 265*4882a593Smuzhiyun #define IMR_ATIMEND_E_8723B BIT(13) /* ATIM Window End Extension for Win7 */ 266*4882a593Smuzhiyun #define IMR_TXERR_8723B BIT(11) /* Tx Error Flag Interrupt Status, write 1 clear. */ 267*4882a593Smuzhiyun #define IMR_RXERR_8723B BIT(10) /* Rx Error Flag INT Status, Write 1 clear */ 268*4882a593Smuzhiyun #define IMR_TXFOVW_8723B BIT(9) /* Transmit FIFO Overflow */ 269*4882a593Smuzhiyun #define IMR_RXFOVW_8723B BIT(8) /* Receive FIFO Overflow */ 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 272*4882a593Smuzhiyun /* #define IMR_RX_MASK (IMR_ROK_8723B|IMR_RDU_8723B|IMR_RXFOVW_8723B) */ 273*4882a593Smuzhiyun #define IMR_TX_MASK (IMR_VODOK_8723B | IMR_VIDOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B | IMR_MGNTDOK_8723B | IMR_HIGHDOK_8723B) 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8723B | IMR_TXBCN0OK_8723B | IMR_TXBCN0ERR_8723B | IMR_BCNDERR0_8723B) 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun #define RT_AC_INT_MASKS (IMR_VIDOK_8723B | IMR_VODOK_8723B | IMR_BEDOK_8723B | IMR_BKDOK_8723B) 278*4882a593Smuzhiyun #endif 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun #endif /* __RTL8723B_SPEC_H__ */ 281