1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2012 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __RTL8192E_HAL_H__ 16*4882a593Smuzhiyun #define __RTL8192E_HAL_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun /* #include "hal_com.h" */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #include "hal_data.h" 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* include HAL Related header after HAL Related compiling flags */ 23*4882a593Smuzhiyun #include "rtl8192e_spec.h" 24*4882a593Smuzhiyun #include "rtl8192e_rf.h" 25*4882a593Smuzhiyun #include "rtl8192e_dm.h" 26*4882a593Smuzhiyun #include "rtl8192e_recv.h" 27*4882a593Smuzhiyun #include "rtl8192e_xmit.h" 28*4882a593Smuzhiyun #include "rtl8192e_cmd.h" 29*4882a593Smuzhiyun #include "rtl8192e_led.h" 30*4882a593Smuzhiyun #include "Hal8192EPwrSeq.h" 31*4882a593Smuzhiyun #include "Hal8192EPhyReg.h" 32*4882a593Smuzhiyun #include "Hal8192EPhyCfg.h" 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT 36*4882a593Smuzhiyun #include "rtl8192e_sreset.h" 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* --------------------------------------------------------------------- 40*4882a593Smuzhiyun * RTL8192E Power Configuration CMDs for PCIe interface 41*4882a593Smuzhiyun * --------------------------------------------------------------------- */ 42*4882a593Smuzhiyun #define Rtl8192E_NIC_PWR_ON_FLOW rtl8192E_power_on_flow 43*4882a593Smuzhiyun #define Rtl8192E_NIC_RF_OFF_FLOW rtl8192E_radio_off_flow 44*4882a593Smuzhiyun #define Rtl8192E_NIC_DISABLE_FLOW rtl8192E_card_disable_flow 45*4882a593Smuzhiyun #define Rtl8192E_NIC_ENABLE_FLOW rtl8192E_card_enable_flow 46*4882a593Smuzhiyun #define Rtl8192E_NIC_SUSPEND_FLOW rtl8192E_suspend_flow 47*4882a593Smuzhiyun #define Rtl8192E_NIC_RESUME_FLOW rtl8192E_resume_flow 48*4882a593Smuzhiyun #define Rtl8192E_NIC_PDN_FLOW rtl8192E_hwpdn_flow 49*4882a593Smuzhiyun #define Rtl8192E_NIC_LPS_ENTER_FLOW rtl8192E_enter_lps_flow 50*4882a593Smuzhiyun #define Rtl8192E_NIC_LPS_LEAVE_FLOW rtl8192E_leave_lps_flow 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #if 1 /* download firmware related data structure */ 54*4882a593Smuzhiyun #define FW_SIZE_8192E 0x8000 /* Compatible with RTL8192e Maximal RAM code size 32k */ 55*4882a593Smuzhiyun #define FW_START_ADDRESS 0x1000 56*4882a593Smuzhiyun #define FW_END_ADDRESS 0x5FFF 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define IS_FW_HEADER_EXIST_8192E(_pFwHdr) ((GET_FIRMWARE_HDR_SIGNATURE_8192E(_pFwHdr) & 0xFFF0) == 0x92E0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun typedef struct _RT_FIRMWARE_8192E { 64*4882a593Smuzhiyun FIRMWARE_SOURCE eFWSource; 65*4882a593Smuzhiyun #ifdef CONFIG_EMBEDDED_FWIMG 66*4882a593Smuzhiyun u8 *szFwBuffer; 67*4882a593Smuzhiyun #else 68*4882a593Smuzhiyun u8 szFwBuffer[FW_SIZE_8192E]; 69*4882a593Smuzhiyun #endif 70*4882a593Smuzhiyun u32 ulFwLength; 71*4882a593Smuzhiyun } RT_FIRMWARE_8192E, *PRT_FIRMWARE_8192E; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * This structure must be cared byte-ordering 75*4882a593Smuzhiyun * 76*4882a593Smuzhiyun * Added by tynli. 2009.12.04. */ 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* ***************************************************** 79*4882a593Smuzhiyun * Firmware Header(8-byte alinment required) 80*4882a593Smuzhiyun * ***************************************************** 81*4882a593Smuzhiyun * --- LONG WORD 0 ---- */ 82*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SIGNATURE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 0, 16) /* 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut */ 83*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_CATEGORY_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 16, 8) /* AP/NIC and USB/PCI */ 84*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_FUNCTION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr, 24, 8) /* Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions */ 85*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_VERSION_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 0, 16)/* FW Version */ 86*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SUB_VER_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 16, 8) /* FW Subversion, default 0x00 */ 87*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD1_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+4, 24, 8) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* --- LONG WORD 1 ---- */ 90*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MONTH_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 0, 8) /* Release time Month field */ 91*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_DATE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 8, 8) /* Release time Date field */ 92*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_HOUR_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 16, 8)/* Release time Hour field */ 93*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_MINUTE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+8, 24, 8)/* Release time Minute field */ 94*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_ROMCODE_SIZE_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 0, 16)/* The size of RAM code */ 95*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD2_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+12, 16, 16) 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* --- LONG WORD 2 ---- */ 98*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_SVN_IDX_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+16, 0, 32)/* The SVN entry index */ 99*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD3_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+20, 0, 32) 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* --- LONG WORD 3 ---- */ 102*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD4_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+24, 0, 32) 103*4882a593Smuzhiyun #define GET_FIRMWARE_HDR_RSVD5_8192E(__FwHdr) LE_BITS_TO_4BYTE(__FwHdr+28, 0, 32) 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #endif /* download firmware related data structure */ 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define DRIVER_EARLY_INT_TIME_8192E 0x05 108*4882a593Smuzhiyun #define BCN_DMA_ATIME_INT_TIME_8192E 0x02 109*4882a593Smuzhiyun #define RX_DMA_SIZE_8192E 0x4000 /* 16K*/ 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 112*4882a593Smuzhiyun #define RESV_FMWF (WKFMCAM_SIZE * MAX_WKFM_CAM_NUM) /* 16 entries, for each is 24 bytes*/ 113*4882a593Smuzhiyun #else 114*4882a593Smuzhiyun #define RESV_FMWF 0 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_DEBUG 118*4882a593Smuzhiyun #define RX_DMA_RESERVED_SIZE_8192E 0x100 /* 256B, reserved for c2h debug message*/ 119*4882a593Smuzhiyun #else 120*4882a593Smuzhiyun #define RX_DMA_RESERVED_SIZE_8192E 0x40 /* 64B, reserved for c2h event(16bytes) or ccx(8 Bytes)*/ 121*4882a593Smuzhiyun #endif 122*4882a593Smuzhiyun #define MAX_RX_DMA_BUFFER_SIZE_8192E (RX_DMA_SIZE_8192E-RX_DMA_RESERVED_SIZE_8192E) /*RX 16K*/ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define PAGE_SIZE_TX_92E PAGE_SIZE_256 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* For General Reserved Page Number(Beacon Queue is reserved page) 128*4882a593Smuzhiyun * if (CONFIG_2BCN_EN) Beacon:4, PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1 129*4882a593Smuzhiyun * Beacon: MAX_BEACON_LEN / PAGE_SIZE_TX_92E 130*4882a593Smuzhiyun * PS-Poll:1, Null Data:1,Prob Rsp:1,Qos Null Data:1,CTS-2-SELF / LTE QoS Null*/ 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun #define RSVD_PAGE_NUM_8192E (MAX_BEACON_LEN / PAGE_SIZE_TX_92E + 6) /*0x08*/ 133*4882a593Smuzhiyun /* For WoWLan , more reserved page 134*4882a593Smuzhiyun * ARP Rsp:1, RWC:1, GTK Info:1,GTK RSP:2,GTK EXT MEM:2, AOAC rpt: 1,PNO: 6 135*4882a593Smuzhiyun * NS offload: 2 NDP info: 1 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 138*4882a593Smuzhiyun #define WOWLAN_PAGE_NUM_8192E 0x0b 139*4882a593Smuzhiyun #else 140*4882a593Smuzhiyun #define WOWLAN_PAGE_NUM_8192E 0x00 141*4882a593Smuzhiyun #endif 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #ifdef CONFIG_PNO_SUPPORT 144*4882a593Smuzhiyun #undef WOWLAN_PAGE_NUM_8192E 145*4882a593Smuzhiyun #define WOWLAN_PAGE_NUM_8192E 0x0d 146*4882a593Smuzhiyun #endif 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* Note: 149*4882a593Smuzhiyun Tx FIFO Size : 64KB 150*4882a593Smuzhiyun Tx page Size : 256B 151*4882a593Smuzhiyun Total page numbers : 256(0x100) 152*4882a593Smuzhiyun */ 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define TOTAL_RSVD_PAGE_NUMBER_8192E (RSVD_PAGE_NUM_8192E + WOWLAN_PAGE_NUM_8192E) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define TOTAL_PAGE_NUMBER_8192E (0x100) 157*4882a593Smuzhiyun #define TX_TOTAL_PAGE_NUMBER_8192E (TOTAL_PAGE_NUMBER_8192E - TOTAL_RSVD_PAGE_NUMBER_8192E) 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_8192E (TX_TOTAL_PAGE_NUMBER_8192E) /* beacon header start address */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define RSVD_PKT_LEN_92E (TOTAL_RSVD_PAGE_NUMBER_8192E * PAGE_SIZE_TX_92E) 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define TX_PAGE_LOAD_FW_BOUNDARY_8192E 0x47 /* 0xA5 */ 165*4882a593Smuzhiyun #define TX_PAGE_BOUNDARY_WOWLAN_8192E 0xE0 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* For Normal Chip Setting 168*4882a593Smuzhiyun * (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER_92C */ 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_HPQ_8192E 0x10 171*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_LPQ_8192E 0x10 172*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_NPQ_8192E 0x10 173*4882a593Smuzhiyun #define NORMAL_PAGE_NUM_EPQ_8192E 0x00 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Note: For WMM Normal Chip Setting ,modify later */ 177*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_HPQ_8192E NORMAL_PAGE_NUM_HPQ_8192E 178*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_LPQ_8192E NORMAL_PAGE_NUM_LPQ_8192E 179*4882a593Smuzhiyun #define WMM_NORMAL_PAGE_NUM_NPQ_8192E NORMAL_PAGE_NUM_NPQ_8192E 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* ------------------------------------------------------------------------- 183*4882a593Smuzhiyun * Chip specific 184*4882a593Smuzhiyun * ------------------------------------------------------------------------- */ 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun /* pic buffer descriptor */ 187*4882a593Smuzhiyun #define RTL8192EE_SEG_NUM TX_BUFFER_SEG_NUM 188*4882a593Smuzhiyun #define TX_DESC_NUM_92E 128 189*4882a593Smuzhiyun #define RX_DESC_NUM_92E 128 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* ------------------------------------------------------------------------- 192*4882a593Smuzhiyun * Channel Plan 193*4882a593Smuzhiyun * ------------------------------------------------------------------------- */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define HWSET_MAX_SIZE_8192E 512 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define EFUSE_REAL_CONTENT_LEN_8192E 512 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define EFUSE_MAP_LEN_8192E 512 200*4882a593Smuzhiyun #define EFUSE_MAX_SECTION_8192E 64 201*4882a593Smuzhiyun #define EFUSE_MAX_WORD_UNIT_8192E 4 202*4882a593Smuzhiyun #define EFUSE_IC_ID_OFFSET_8192E 506 /* For some inferiority IC purpose. added by Roger, 2009.09.02. */ 203*4882a593Smuzhiyun #define AVAILABLE_EFUSE_ADDR_8192E(addr) (addr < EFUSE_REAL_CONTENT_LEN_8192E) 204*4882a593Smuzhiyun /* 205*4882a593Smuzhiyun * <Roger_Notes> To prevent out of boundary programming case, leave 1byte and program full section 206*4882a593Smuzhiyun * 9bytes + 1byt + 5bytes and pre 1byte. 207*4882a593Smuzhiyun * For worst case: 208*4882a593Smuzhiyun * | 1byte|----8bytes----|1byte|--5bytes--| 209*4882a593Smuzhiyun * | | Reserved(14bytes) | 210*4882a593Smuzhiyun * */ 211*4882a593Smuzhiyun #define EFUSE_OOB_PROTECT_BYTES_8192E 15 /* PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */ 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun /* ******************************************************** 216*4882a593Smuzhiyun * EFUSE for BT definition 217*4882a593Smuzhiyun * ******************************************************** */ 218*4882a593Smuzhiyun #define EFUSE_BT_REAL_BANK_CONTENT_LEN_8192E 512 219*4882a593Smuzhiyun #define EFUSE_BT_REAL_CONTENT_LEN_8192E 1024 /* 512*2 */ 220*4882a593Smuzhiyun #define EFUSE_BT_MAP_LEN_8192E 1024 /* 1k bytes */ 221*4882a593Smuzhiyun #define EFUSE_BT_MAX_SECTION_8192E 128 /* 1024/8 */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun #define EFUSE_PROTECT_BYTES_BANK_8192E 16 224*4882a593Smuzhiyun #define EFUSE_MAX_BANK_8192E 3 225*4882a593Smuzhiyun /* *********************************************************** */ 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) 228*4882a593Smuzhiyun #define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /* #define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) */ 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* #define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) */ 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun /* rtl8812_hal_init.c */ 235*4882a593Smuzhiyun void _8051Reset8192E(PADAPTER padapter); 236*4882a593Smuzhiyun s32 FirmwareDownload8192E(PADAPTER Adapter, BOOLEAN bUsedWoWLANFw); 237*4882a593Smuzhiyun void InitializeFirmwareVars8192E(PADAPTER padapter); 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun s32 InitLLTTable8192E(PADAPTER padapter, u8 txpktbuf_bndy); 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun /* EFuse */ 242*4882a593Smuzhiyun u8 GetEEPROMSize8192E(PADAPTER padapter); 243*4882a593Smuzhiyun void hal_InitPGData_8192E(PADAPTER padapter, u8 *PROMContent); 244*4882a593Smuzhiyun void Hal_EfuseParseIDCode8192E(PADAPTER padapter, u8 *hwinfo); 245*4882a593Smuzhiyun void Hal_ReadPROMVersion8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 246*4882a593Smuzhiyun void Hal_ReadPowerSavingMode8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 247*4882a593Smuzhiyun void Hal_ReadTxPowerInfo8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 248*4882a593Smuzhiyun void Hal_ReadBoardType8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 249*4882a593Smuzhiyun void Hal_ReadThermalMeter_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 250*4882a593Smuzhiyun void Hal_ReadChannelPlan8192E(PADAPTER padapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 251*4882a593Smuzhiyun void Hal_EfuseParseXtal_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 252*4882a593Smuzhiyun void Hal_ReadAntennaDiversity8192E(PADAPTER pAdapter, u8 *PROMContent, BOOLEAN AutoLoadFail); 253*4882a593Smuzhiyun void Hal_ReadPAType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 254*4882a593Smuzhiyun void Hal_ReadAmplifierType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 255*4882a593Smuzhiyun void Hal_ReadRFEType_8192E(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); 256*4882a593Smuzhiyun void Hal_EfuseParseBTCoexistInfo8192E(PADAPTER Adapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 257*4882a593Smuzhiyun void Hal_EfuseParseKFreeData_8192E(PADAPTER pAdapter, u8 *hwinfo, BOOLEAN AutoLoadFail); 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun u8 Hal_CrystalAFEAdjust(_adapter *Adapter); 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun BOOLEAN HalDetectPwrDownMode8192E(PADAPTER Adapter); 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 264*4882a593Smuzhiyun void Hal_DetectWoWMode(PADAPTER pAdapter); 265*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /***********************************************************/ 268*4882a593Smuzhiyun /* RTL8192E-MAC Setting */ 269*4882a593Smuzhiyun void _InitQueueReservedPage_8192E(PADAPTER Adapter); 270*4882a593Smuzhiyun void _InitQueuePriority_8192E(PADAPTER Adapter); 271*4882a593Smuzhiyun void _InitTxBufferBoundary_8192E(PADAPTER Adapter, u8 txpktbuf_bndy); 272*4882a593Smuzhiyun void _InitPageBoundary_8192E(PADAPTER Adapter); 273*4882a593Smuzhiyun /* void _InitTransferPageSize_8192E(PADAPTER Adapter); */ 274*4882a593Smuzhiyun void _InitDriverInfoSize_8192E(PADAPTER Adapter, u8 drvInfoSize); 275*4882a593Smuzhiyun void _InitRDGSetting_8192E(PADAPTER Adapter); 276*4882a593Smuzhiyun void _InitID_8192E(PADAPTER Adapter); 277*4882a593Smuzhiyun void _InitNetworkType_8192E(PADAPTER Adapter); 278*4882a593Smuzhiyun void _InitWMACSetting_8192E(PADAPTER Adapter); 279*4882a593Smuzhiyun void _InitAdaptiveCtrl_8192E(PADAPTER Adapter); 280*4882a593Smuzhiyun void _InitEDCA_8192E(PADAPTER Adapter); 281*4882a593Smuzhiyun void _InitRetryFunction_8192E(PADAPTER Adapter); 282*4882a593Smuzhiyun void _BBTurnOnBlock_8192E(PADAPTER Adapter); 283*4882a593Smuzhiyun void _InitBeaconParameters_8192E(PADAPTER Adapter); 284*4882a593Smuzhiyun void _InitBeaconMaxError_8192E( 285*4882a593Smuzhiyun PADAPTER Adapter, 286*4882a593Smuzhiyun BOOLEAN InfraMode 287*4882a593Smuzhiyun ); 288*4882a593Smuzhiyun void SetBeaconRelatedRegisters8192E(PADAPTER padapter); 289*4882a593Smuzhiyun void hal_ReadRFType_8192E(PADAPTER Adapter); 290*4882a593Smuzhiyun /* RTL8192E-MAC Setting 291*4882a593Smuzhiyun ***********************************************************/ 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun u8 SetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); 294*4882a593Smuzhiyun void GetHwReg8192E(PADAPTER Adapter, u8 variable, u8 *val); 295*4882a593Smuzhiyun u8 296*4882a593Smuzhiyun SetHalDefVar8192E( 297*4882a593Smuzhiyun PADAPTER Adapter, 298*4882a593Smuzhiyun HAL_DEF_VARIABLE eVariable, 299*4882a593Smuzhiyun void *pValue 300*4882a593Smuzhiyun ); 301*4882a593Smuzhiyun u8 302*4882a593Smuzhiyun GetHalDefVar8192E( 303*4882a593Smuzhiyun PADAPTER Adapter, 304*4882a593Smuzhiyun HAL_DEF_VARIABLE eVariable, 305*4882a593Smuzhiyun void *pValue 306*4882a593Smuzhiyun ); 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun void rtl8192e_set_hal_ops(struct hal_ops *pHalFunc); 309*4882a593Smuzhiyun void init_hal_spec_8192e(_adapter *adapter); 310*4882a593Smuzhiyun void rtl8192e_init_default_value(_adapter *padapter); 311*4882a593Smuzhiyun 312*4882a593Smuzhiyun void rtl8192e_start_thread(_adapter *padapter); 313*4882a593Smuzhiyun void rtl8192e_stop_thread(_adapter *padapter); 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 316*4882a593Smuzhiyun BOOLEAN InterruptRecognized8192EE(PADAPTER Adapter); 317*4882a593Smuzhiyun u16 get_txbd_rw_reg(u16 ff_hwaddr); 318*4882a593Smuzhiyun #endif 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI 321*4882a593Smuzhiyun #ifdef CONFIG_SDIO_TX_ENABLE_AVAL_INT 322*4882a593Smuzhiyun void _init_available_page_threshold(PADAPTER padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ); 323*4882a593Smuzhiyun #endif 324*4882a593Smuzhiyun #endif 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST 327*4882a593Smuzhiyun void rtl8192e_combo_card_WifiOnlyHwInit(PADAPTER Adapter); 328*4882a593Smuzhiyun #endif 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #endif /* __RTL8192E_HAL_H__ */ 331