1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HAL_INTF_H__ 16*4882a593Smuzhiyun #define __HAL_INTF_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun enum RTL871X_HCI_TYPE { 20*4882a593Smuzhiyun RTW_PCIE = BIT0, 21*4882a593Smuzhiyun RTW_USB = BIT1, 22*4882a593Smuzhiyun RTW_SDIO = BIT2, 23*4882a593Smuzhiyun RTW_GSPI = BIT3, 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun enum _CHIP_TYPE { 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun NULL_CHIP_TYPE, 29*4882a593Smuzhiyun RTL8188E, 30*4882a593Smuzhiyun RTL8192E, 31*4882a593Smuzhiyun RTL8812, 32*4882a593Smuzhiyun RTL8821, /* RTL8811 */ 33*4882a593Smuzhiyun RTL8723B, 34*4882a593Smuzhiyun RTL8814A, 35*4882a593Smuzhiyun RTL8703B, 36*4882a593Smuzhiyun RTL8188F, 37*4882a593Smuzhiyun RTL8188GTV, 38*4882a593Smuzhiyun RTL8822B, 39*4882a593Smuzhiyun RTL8723D, 40*4882a593Smuzhiyun RTL8821C, 41*4882a593Smuzhiyun RTL8710B, 42*4882a593Smuzhiyun RTL8192F, 43*4882a593Smuzhiyun RTL8822C, 44*4882a593Smuzhiyun RTL8814B, 45*4882a593Smuzhiyun RTL8723F, 46*4882a593Smuzhiyun MAX_CHIP_TYPE 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #ifdef RTW_HALMAC 50*4882a593Smuzhiyun enum fw_mem { 51*4882a593Smuzhiyun FW_EMEM, 52*4882a593Smuzhiyun FW_IMEM, 53*4882a593Smuzhiyun FW_DMEM, 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun #endif 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun extern const u32 _chip_type_to_odm_ic_type[]; 58*4882a593Smuzhiyun #define chip_type_to_odm_ic_type(chip_type) (((chip_type) >= MAX_CHIP_TYPE) ? _chip_type_to_odm_ic_type[MAX_CHIP_TYPE] : _chip_type_to_odm_ic_type[(chip_type)]) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun typedef enum _HAL_HW_TIMER_TYPE { 61*4882a593Smuzhiyun HAL_TIMER_NONE = 0, 62*4882a593Smuzhiyun HAL_TIMER_TXBF = 1, 63*4882a593Smuzhiyun HAL_TIMER_EARLYMODE = 2, 64*4882a593Smuzhiyun } HAL_HW_TIMER_TYPE, *PHAL_HW_TIMER_TYPE; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun typedef enum _HW_VARIABLES { 68*4882a593Smuzhiyun HW_VAR_MEDIA_STATUS, 69*4882a593Smuzhiyun HW_VAR_SET_OPMODE, 70*4882a593Smuzhiyun HW_VAR_MAC_ADDR, 71*4882a593Smuzhiyun HW_VAR_BSSID, 72*4882a593Smuzhiyun HW_VAR_INIT_RTS_RATE, 73*4882a593Smuzhiyun HW_VAR_BASIC_RATE, 74*4882a593Smuzhiyun HW_VAR_TXPAUSE, 75*4882a593Smuzhiyun HW_VAR_BCN_FUNC, 76*4882a593Smuzhiyun HW_VAR_BCN_CTRL_ADDR, 77*4882a593Smuzhiyun HW_VAR_CORRECT_TSF, 78*4882a593Smuzhiyun HW_VAR_RCR, 79*4882a593Smuzhiyun HW_VAR_MLME_DISCONNECT, 80*4882a593Smuzhiyun HW_VAR_MLME_SITESURVEY, 81*4882a593Smuzhiyun HW_VAR_MLME_JOIN, 82*4882a593Smuzhiyun HW_VAR_ON_RCR_AM, 83*4882a593Smuzhiyun HW_VAR_OFF_RCR_AM, 84*4882a593Smuzhiyun HW_VAR_BEACON_INTERVAL, 85*4882a593Smuzhiyun HW_VAR_SLOT_TIME, 86*4882a593Smuzhiyun HW_VAR_RESP_SIFS, 87*4882a593Smuzhiyun HW_VAR_ACK_PREAMBLE, 88*4882a593Smuzhiyun HW_VAR_SEC_CFG, 89*4882a593Smuzhiyun HW_VAR_SEC_DK_CFG, 90*4882a593Smuzhiyun HW_VAR_BCN_VALID, 91*4882a593Smuzhiyun HW_VAR_FREECNT, 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* PHYDM odm->SupportAbility */ 94*4882a593Smuzhiyun HW_VAR_CAM_EMPTY_ENTRY, 95*4882a593Smuzhiyun HW_VAR_CAM_INVALID_ALL, 96*4882a593Smuzhiyun HW_VAR_AC_PARAM_VO, 97*4882a593Smuzhiyun HW_VAR_AC_PARAM_VI, 98*4882a593Smuzhiyun HW_VAR_AC_PARAM_BE, 99*4882a593Smuzhiyun HW_VAR_AC_PARAM_BK, 100*4882a593Smuzhiyun HW_VAR_ACM_CTRL, 101*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA 102*4882a593Smuzhiyun HW_VAR_UAPSD_TID, 103*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */ 104*4882a593Smuzhiyun HW_VAR_AMPDU_MIN_SPACE, 105*4882a593Smuzhiyun #ifdef CONFIG_80211N_HT 106*4882a593Smuzhiyun HW_VAR_AMPDU_FACTOR, 107*4882a593Smuzhiyun #endif /* CONFIG_80211N_HT */ 108*4882a593Smuzhiyun HW_VAR_RXDMA_AGG_PG_TH, 109*4882a593Smuzhiyun HW_VAR_SET_RPWM, 110*4882a593Smuzhiyun HW_VAR_CPWM, 111*4882a593Smuzhiyun HW_VAR_H2C_FW_PWRMODE, 112*4882a593Smuzhiyun HW_VAR_H2C_FW_PWRMODE_RFON_CTRL, 113*4882a593Smuzhiyun HW_VAR_H2C_INACTIVE_IPS, 114*4882a593Smuzhiyun HW_VAR_H2C_PS_TUNE_PARAM, 115*4882a593Smuzhiyun HW_VAR_H2C_FW_JOINBSSRPT, 116*4882a593Smuzhiyun HW_VAR_FWLPS_RF_ON, 117*4882a593Smuzhiyun HW_VAR_H2C_FW_P2P_PS_OFFLOAD, 118*4882a593Smuzhiyun #ifdef CONFIG_LPS_POFF 119*4882a593Smuzhiyun HW_VAR_LPS_POFF_INIT, 120*4882a593Smuzhiyun HW_VAR_LPS_POFF_DEINIT, 121*4882a593Smuzhiyun HW_VAR_LPS_POFF_SET_MODE, 122*4882a593Smuzhiyun HW_VAR_LPS_POFF_WOW_EN, 123*4882a593Smuzhiyun #endif 124*4882a593Smuzhiyun #ifdef CONFIG_LPS_PG 125*4882a593Smuzhiyun HW_VAR_LPS_PG_HANDLE, 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun HW_VAR_TRIGGER_GPIO_0, 128*4882a593Smuzhiyun HW_VAR_BT_SET_COEXIST, 129*4882a593Smuzhiyun HW_VAR_BT_ISSUE_DELBA, 130*4882a593Smuzhiyun HW_VAR_SWITCH_EPHY_WoWLAN, 131*4882a593Smuzhiyun HW_VAR_EFUSE_USAGE, 132*4882a593Smuzhiyun HW_VAR_EFUSE_BYTES, 133*4882a593Smuzhiyun HW_VAR_EFUSE_BT_USAGE, 134*4882a593Smuzhiyun HW_VAR_EFUSE_BT_BYTES, 135*4882a593Smuzhiyun HW_VAR_FIFO_CLEARN_UP, 136*4882a593Smuzhiyun HW_VAR_RESTORE_HW_SEQ, 137*4882a593Smuzhiyun HW_VAR_CHECK_TXBUF, 138*4882a593Smuzhiyun HW_VAR_PCIE_STOP_TX_DMA, 139*4882a593Smuzhiyun HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 140*4882a593Smuzhiyun HW_VAR_HCI_SUS_STATE, 141*4882a593Smuzhiyun /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */ 142*4882a593Smuzhiyun /* Unit in microsecond. 0 means disable this function. */ 143*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 144*4882a593Smuzhiyun HW_VAR_WOWLAN, 145*4882a593Smuzhiyun HW_VAR_WAKEUP_REASON, 146*4882a593Smuzhiyun #endif 147*4882a593Smuzhiyun HW_VAR_RPWM_TOG, 148*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 149*4882a593Smuzhiyun HW_VAR_WOW_OUTPUT_GPIO, 150*4882a593Smuzhiyun HW_VAR_WOW_INPUT_GPIO, 151*4882a593Smuzhiyun HW_SET_GPIO_WL_CTRL, 152*4882a593Smuzhiyun #endif 153*4882a593Smuzhiyun HW_VAR_SYS_CLKR, 154*4882a593Smuzhiyun HW_VAR_NAV_UPPER, 155*4882a593Smuzhiyun HW_VAR_RPT_TIMER_SETTING, 156*4882a593Smuzhiyun HW_VAR_TX_RPT_MAX_MACID, 157*4882a593Smuzhiyun HW_VAR_CHK_HI_QUEUE_EMPTY, 158*4882a593Smuzhiyun HW_VAR_CHK_MGQ_CPU_EMPTY, 159*4882a593Smuzhiyun HW_VAR_DL_BCN_SEL, 160*4882a593Smuzhiyun HW_VAR_AMPDU_MAX_TIME, 161*4882a593Smuzhiyun HW_VAR_USB_MODE, 162*4882a593Smuzhiyun HW_VAR_PORT_SWITCH, 163*4882a593Smuzhiyun HW_VAR_PORT_CFG, 164*4882a593Smuzhiyun HW_VAR_DO_IQK, 165*4882a593Smuzhiyun HW_VAR_DM_IN_LPS_LCLK,/*flag CONFIG_LPS_LCLK_WD_TIMER*/ 166*4882a593Smuzhiyun HW_VAR_SET_REQ_FW_PS, 167*4882a593Smuzhiyun HW_VAR_FW_PS_STATE, 168*4882a593Smuzhiyun HW_VAR_SOUNDING_ENTER, 169*4882a593Smuzhiyun HW_VAR_SOUNDING_LEAVE, 170*4882a593Smuzhiyun HW_VAR_SOUNDING_RATE, 171*4882a593Smuzhiyun HW_VAR_SOUNDING_STATUS, 172*4882a593Smuzhiyun HW_VAR_SOUNDING_FW_NDPA, 173*4882a593Smuzhiyun HW_VAR_SOUNDING_CLK, 174*4882a593Smuzhiyun HW_VAR_SOUNDING_SET_GID_TABLE, 175*4882a593Smuzhiyun HW_VAR_SOUNDING_CSI_REPORT, 176*4882a593Smuzhiyun /*Add by YuChen for TXBF HW timer*/ 177*4882a593Smuzhiyun HW_VAR_HW_REG_TIMER_INIT, 178*4882a593Smuzhiyun HW_VAR_HW_REG_TIMER_RESTART, 179*4882a593Smuzhiyun HW_VAR_HW_REG_TIMER_START, 180*4882a593Smuzhiyun HW_VAR_HW_REG_TIMER_STOP, 181*4882a593Smuzhiyun /*Add by YuChen for TXBF HW timer*/ 182*4882a593Smuzhiyun HW_VAR_DL_RSVD_PAGE, 183*4882a593Smuzhiyun HW_VAR_MACID_LINK, 184*4882a593Smuzhiyun HW_VAR_MACID_NOLINK, 185*4882a593Smuzhiyun HW_VAR_DUMP_MAC_QUEUE_INFO, 186*4882a593Smuzhiyun HW_VAR_ASIX_IOT, 187*4882a593Smuzhiyun #ifdef CONFIG_MBSSID_CAM 188*4882a593Smuzhiyun HW_VAR_MBSSID_CAM_WRITE, 189*4882a593Smuzhiyun HW_VAR_MBSSID_CAM_CLEAR, 190*4882a593Smuzhiyun HW_VAR_RCR_MBSSID_EN, 191*4882a593Smuzhiyun #endif 192*4882a593Smuzhiyun HW_VAR_EN_HW_UPDATE_TSF, 193*4882a593Smuzhiyun HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO, 194*4882a593Smuzhiyun HW_VAR_CH_SW_IQK_INFO_BACKUP, 195*4882a593Smuzhiyun HW_VAR_CH_SW_IQK_INFO_RESTORE, 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun HW_VAR_DBI, 198*4882a593Smuzhiyun HW_VAR_MDIO, 199*4882a593Smuzhiyun HW_VAR_L1OFF_CAPABILITY, 200*4882a593Smuzhiyun HW_VAR_L1OFF_NIC_SUPPORT, 201*4882a593Smuzhiyun HW_VAR_BCN_EARLY_C2H_RPT, 202*4882a593Smuzhiyun HW_VAR_SET_DRV_ERLY_INT, 203*4882a593Smuzhiyun HW_VAR_DUMP_MAC_TXFIFO, 204*4882a593Smuzhiyun HW_VAR_PWR_CMD, 205*4882a593Smuzhiyun #ifdef CONFIG_FW_HANDLE_TXBCN 206*4882a593Smuzhiyun HW_VAR_BCN_HEAD_SEL, 207*4882a593Smuzhiyun #endif 208*4882a593Smuzhiyun HW_VAR_SET_SOML_PARAM, 209*4882a593Smuzhiyun HW_VAR_ENABLE_RX_BAR, 210*4882a593Smuzhiyun HW_VAR_TSF_AUTO_SYNC, 211*4882a593Smuzhiyun HW_VAR_LPS_STATE_CHK, 212*4882a593Smuzhiyun HW_VAR_LPS_RFON_CHK, 213*4882a593Smuzhiyun #ifdef CONFIG_RTS_FULL_BW 214*4882a593Smuzhiyun HW_VAR_SET_RTS_BW, 215*4882a593Smuzhiyun #endif 216*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI) 217*4882a593Smuzhiyun HW_VAR_ENSWBCN, 218*4882a593Smuzhiyun #endif 219*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 220*4882a593Smuzhiyun HW_VAR_VENDOR_WOW_MODE, 221*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 222*4882a593Smuzhiyun #ifdef CONFIG_WAKE_ON_BT 223*4882a593Smuzhiyun HW_VAR_WAKE_ON_BT_GPIO_SWITCH, 224*4882a593Smuzhiyun #endif 225*4882a593Smuzhiyun } HW_VARIABLES; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun typedef enum _HAL_DEF_VARIABLE { 228*4882a593Smuzhiyun HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, 229*4882a593Smuzhiyun HAL_DEF_IS_SUPPORT_ANT_DIV, 230*4882a593Smuzhiyun HAL_DEF_DRVINFO_SZ, 231*4882a593Smuzhiyun HAL_DEF_MAX_RECVBUF_SZ, 232*4882a593Smuzhiyun HAL_DEF_RX_PACKET_OFFSET, 233*4882a593Smuzhiyun HAL_DEF_RX_DMA_SZ_WOW, 234*4882a593Smuzhiyun HAL_DEF_RX_DMA_SZ, 235*4882a593Smuzhiyun HAL_DEF_RX_PAGE_SIZE, 236*4882a593Smuzhiyun HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ 237*4882a593Smuzhiyun HAL_DEF_RA_DECISION_RATE, 238*4882a593Smuzhiyun HAL_DEF_RA_SGI, 239*4882a593Smuzhiyun HAL_DEF_PT_PWR_STATUS, 240*4882a593Smuzhiyun HAL_DEF_TX_LDPC, /* LDPC support */ 241*4882a593Smuzhiyun HAL_DEF_RX_LDPC, /* LDPC support */ 242*4882a593Smuzhiyun HAL_DEF_TX_STBC, /* TX STBC support */ 243*4882a593Smuzhiyun HAL_DEF_RX_STBC, /* RX STBC support */ 244*4882a593Smuzhiyun HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit Compressed Steering Capable */ 245*4882a593Smuzhiyun HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */ 246*4882a593Smuzhiyun HAL_DEF_VHT_MU_BEAMFORMER, /* VHT MU Beamformer support */ 247*4882a593Smuzhiyun HAL_DEF_VHT_MU_BEAMFORMEE, /* VHT MU Beamformee support */ 248*4882a593Smuzhiyun HAL_DEF_BEAMFORMER_CAP, 249*4882a593Smuzhiyun HAL_DEF_BEAMFORMEE_CAP, 250*4882a593Smuzhiyun HW_VAR_MAX_RX_AMPDU_FACTOR, 251*4882a593Smuzhiyun HW_DEF_RA_INFO_DUMP, 252*4882a593Smuzhiyun HAL_DEF_DBG_DUMP_TXPKT, 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun HAL_DEF_TX_PAGE_SIZE, 255*4882a593Smuzhiyun HAL_DEF_TX_PAGE_BOUNDARY, 256*4882a593Smuzhiyun HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN, 257*4882a593Smuzhiyun HAL_DEF_TX_BUFFER_LAST_ENTRY, 258*4882a593Smuzhiyun HAL_DEF_ANT_DETECT,/* to do for 8723a */ 259*4882a593Smuzhiyun HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */ 260*4882a593Smuzhiyun HAL_DEF_EFUSE_USAGE, /* Get current EFUSE utilization. 2008.12.19. Added by Roger. */ 261*4882a593Smuzhiyun HAL_DEF_EFUSE_BYTES, 262*4882a593Smuzhiyun HW_VAR_BEST_AMPDU_DENSITY, 263*4882a593Smuzhiyun } HAL_DEF_VARIABLE; 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun typedef enum _HAL_ODM_VARIABLE { 266*4882a593Smuzhiyun HAL_ODM_STA_INFO, 267*4882a593Smuzhiyun HAL_ODM_P2P_STATE, 268*4882a593Smuzhiyun HAL_ODM_WIFI_DISPLAY_STATE, 269*4882a593Smuzhiyun HAL_ODM_INITIAL_GAIN, 270*4882a593Smuzhiyun HAL_ODM_RX_INFO_DUMP, 271*4882a593Smuzhiyun HAL_ODM_RX_Dframe_INFO, 272*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY 273*4882a593Smuzhiyun HAL_ODM_ANTDIV_SELECT 274*4882a593Smuzhiyun #endif 275*4882a593Smuzhiyun } HAL_ODM_VARIABLE; 276*4882a593Smuzhiyun 277*4882a593Smuzhiyun typedef enum _HAL_INTF_PS_FUNC { 278*4882a593Smuzhiyun HAL_USB_SELECT_SUSPEND, 279*4882a593Smuzhiyun HAL_MAX_ID, 280*4882a593Smuzhiyun } HAL_INTF_PS_FUNC; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun typedef s32(*c2h_id_filter)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun struct txpwr_idx_comp; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun struct hal_ops { 287*4882a593Smuzhiyun /*** initialize section ***/ 288*4882a593Smuzhiyun void (*read_chip_version)(_adapter *padapter); 289*4882a593Smuzhiyun void (*init_default_value)(_adapter *padapter); 290*4882a593Smuzhiyun void (*intf_chip_configure)(_adapter *padapter); 291*4882a593Smuzhiyun u8 (*read_adapter_info)(_adapter *padapter); 292*4882a593Smuzhiyun u32(*hal_power_on)(_adapter *padapter); 293*4882a593Smuzhiyun void (*hal_power_off)(_adapter *padapter); 294*4882a593Smuzhiyun u32(*hal_init)(_adapter *padapter); 295*4882a593Smuzhiyun u32(*hal_deinit)(_adapter *padapter); 296*4882a593Smuzhiyun void (*dm_init)(_adapter *padapter); 297*4882a593Smuzhiyun void (*dm_deinit)(_adapter *padapter); 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /*** xmit section ***/ 300*4882a593Smuzhiyun s32(*init_xmit_priv)(_adapter *padapter); 301*4882a593Smuzhiyun void (*free_xmit_priv)(_adapter *padapter); 302*4882a593Smuzhiyun s32(*hal_xmit)(_adapter *padapter, struct xmit_frame *pxmitframe); 303*4882a593Smuzhiyun /* 304*4882a593Smuzhiyun * mgnt_xmit should be implemented to run in interrupt context 305*4882a593Smuzhiyun */ 306*4882a593Smuzhiyun s32(*mgnt_xmit)(_adapter *padapter, struct xmit_frame *pmgntframe); 307*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 308*4882a593Smuzhiyun s32(*hal_mgmt_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe); 309*4882a593Smuzhiyun #endif 310*4882a593Smuzhiyun s32(*hal_xmitframe_enqueue)(_adapter *padapter, struct xmit_frame *pxmitframe); 311*4882a593Smuzhiyun #if defined (CONFIG_CONCURRENT_MODE) && defined (CONFIG_TSF_SYNC) 312*4882a593Smuzhiyun void(*tsf_sync)(_adapter *Adapter); 313*4882a593Smuzhiyun #endif 314*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE 315*4882a593Smuzhiyun s32(*xmit_thread_handler)(_adapter *padapter); 316*4882a593Smuzhiyun #endif 317*4882a593Smuzhiyun void (*run_thread)(_adapter *padapter); 318*4882a593Smuzhiyun void (*cancel_thread)(_adapter *padapter); 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun /*** recv section ***/ 321*4882a593Smuzhiyun s32(*init_recv_priv)(_adapter *padapter); 322*4882a593Smuzhiyun void (*free_recv_priv)(_adapter *padapter); 323*4882a593Smuzhiyun #ifdef CONFIG_RECV_THREAD_MODE 324*4882a593Smuzhiyun s32 (*recv_hdl)(_adapter *adapter); 325*4882a593Smuzhiyun #endif 326*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) 327*4882a593Smuzhiyun u32(*inirp_init)(_adapter *padapter); 328*4882a593Smuzhiyun u32(*inirp_deinit)(_adapter *padapter); 329*4882a593Smuzhiyun #endif 330*4882a593Smuzhiyun /*** interrupt hdl section ***/ 331*4882a593Smuzhiyun void (*enable_interrupt)(_adapter *padapter); 332*4882a593Smuzhiyun void (*disable_interrupt)(_adapter *padapter); 333*4882a593Smuzhiyun u8(*check_ips_status)(_adapter *padapter); 334*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI) 335*4882a593Smuzhiyun s32(*interrupt_handler)(_adapter *padapter); 336*4882a593Smuzhiyun void (*unmap_beacon_icf)(_adapter *padapter); 337*4882a593Smuzhiyun #endif 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) 340*4882a593Smuzhiyun void (*interrupt_handler)(_adapter *padapter, u16 pkt_len, u8 *pbuf); 341*4882a593Smuzhiyun #endif 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI) 344*4882a593Smuzhiyun void (*irp_reset)(_adapter *padapter); 345*4882a593Smuzhiyun #endif 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun /*** DM section ***/ 348*4882a593Smuzhiyun #ifdef CONFIG_RTW_SW_LED 349*4882a593Smuzhiyun void (*InitSwLeds)(_adapter *padapter); 350*4882a593Smuzhiyun void (*DeInitSwLeds)(_adapter *padapter); 351*4882a593Smuzhiyun #endif 352*4882a593Smuzhiyun void (*set_chnl_bw_handler)(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun void (*set_tx_power_level_handler)(_adapter *adapter, u8 channel); 355*4882a593Smuzhiyun void (*set_txpwr_done)(_adapter *adapter); 356*4882a593Smuzhiyun void (*set_tx_power_index_handler)(_adapter *adapter, u32 powerindex, enum rf_path rfpath, u8 rate); 357*4882a593Smuzhiyun 358*4882a593Smuzhiyun u8 (*get_tx_power_index_handler)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate 359*4882a593Smuzhiyun , enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch, struct txpwr_idx_comp *tic); 360*4882a593Smuzhiyun s8 (*get_txpwr_target_extra_bias)(_adapter *adapter, enum rf_path rfpath, RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch); 361*4882a593Smuzhiyun 362*4882a593Smuzhiyun void (*hal_dm_watchdog)(_adapter *padapter); 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun u8 (*set_hw_reg_handler)(_adapter *padapter, u8 variable, u8 *val); 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun void (*GetHwRegHandler)(_adapter *padapter, u8 variable, u8 *val); 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun u8 (*get_hal_def_var_handler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue); 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun u8(*SetHalDefVarHandler)(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue); 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun void (*GetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2); 375*4882a593Smuzhiyun void (*SetHalODMVarHandler)(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet); 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun void (*SetBeaconRelatedRegistersHandler)(_adapter *padapter); 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun u8(*interface_ps_func)(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun u32(*read_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask); 382*4882a593Smuzhiyun void (*write_bbreg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 383*4882a593Smuzhiyun u32 (*read_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); 384*4882a593Smuzhiyun void (*write_rfreg)(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); 385*4882a593Smuzhiyun #ifdef CONFIG_SYSON_INDIRECT_ACCESS 386*4882a593Smuzhiyun u32 (*read_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask); 387*4882a593Smuzhiyun void (*write_syson_reg)(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 388*4882a593Smuzhiyun #endif 389*4882a593Smuzhiyun void (*read_wmmedca_reg)(_adapter *padapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params); 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun #ifdef CONFIG_HOSTAPD_MLME 392*4882a593Smuzhiyun s32(*hostap_mgnt_xmit_entry)(_adapter *padapter, _pkt *pkt); 393*4882a593Smuzhiyun #endif 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun void (*EfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); 396*4882a593Smuzhiyun void (*BTEfusePowerSwitch)(_adapter *padapter, u8 bWrite, u8 PwrState); 397*4882a593Smuzhiyun void (*ReadEFuse)(_adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest); 398*4882a593Smuzhiyun void (*EFUSEGetEfuseDefinition)(_adapter *padapter, u8 efuseType, u8 type, void *pOut, BOOLEAN bPseudoTest); 399*4882a593Smuzhiyun u16(*EfuseGetCurrentSize)(_adapter *padapter, u8 efuseType, BOOLEAN bPseudoTest); 400*4882a593Smuzhiyun int (*Efuse_PgPacketRead)(_adapter *padapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); 401*4882a593Smuzhiyun int (*Efuse_PgPacketWrite)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); 402*4882a593Smuzhiyun u8(*Efuse_WordEnableDataWrite)(_adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); 403*4882a593Smuzhiyun BOOLEAN(*Efuse_PgPacketWrite_BT)(_adapter *padapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); 404*4882a593Smuzhiyun #if defined(CONFIG_RTL8710B) 405*4882a593Smuzhiyun BOOLEAN(*efuse_indirect_read4)(_adapter *padapter, u16 regaddr, u8 *value); 406*4882a593Smuzhiyun #endif 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT 409*4882a593Smuzhiyun void (*sreset_init_value)(_adapter *padapter); 410*4882a593Smuzhiyun void (*sreset_reset_value)(_adapter *padapter); 411*4882a593Smuzhiyun void (*silentreset)(_adapter *padapter); 412*4882a593Smuzhiyun void (*sreset_xmit_status_check)(_adapter *padapter); 413*4882a593Smuzhiyun void (*sreset_linked_status_check)(_adapter *padapter); 414*4882a593Smuzhiyun u8(*sreset_get_wifi_status)(_adapter *padapter); 415*4882a593Smuzhiyun bool (*sreset_inprogress)(_adapter *padapter); 416*4882a593Smuzhiyun #endif 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun #ifdef CONFIG_IOL 419*4882a593Smuzhiyun int (*IOL_exec_cmds_sync)(_adapter *padapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); 420*4882a593Smuzhiyun #endif 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun void (*hal_notch_filter)(_adapter *adapter, bool enable); 423*4882a593Smuzhiyun #ifdef RTW_HALMAC 424*4882a593Smuzhiyun void (*hal_mac_c2h_handler)(_adapter *adapter, u8 *pbuf, u16 length); 425*4882a593Smuzhiyun #else 426*4882a593Smuzhiyun s32(*c2h_handler)(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); 427*4882a593Smuzhiyun #endif 428*4882a593Smuzhiyun void (*reqtxrpt)(_adapter *padapter, u8 macid); 429*4882a593Smuzhiyun s32(*fill_h2c_cmd)(PADAPTER, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); 430*4882a593Smuzhiyun void (*fill_fake_txdesc)(PADAPTER, u8 *pDesc, u32 BufferLen, 431*4882a593Smuzhiyun u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 432*4882a593Smuzhiyun s32(*fw_dl)(_adapter *adapter, u8 wowlan); 433*4882a593Smuzhiyun #ifdef RTW_HALMAC 434*4882a593Smuzhiyun s32 (*fw_mem_dl)(_adapter *adapter, enum fw_mem mem); 435*4882a593Smuzhiyun #endif 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI) 438*4882a593Smuzhiyun void (*clear_interrupt)(_adapter *padapter); 439*4882a593Smuzhiyun #endif 440*4882a593Smuzhiyun u8(*hal_get_tx_buff_rsvd_page_num)(_adapter *adapter, bool wowlan); 441*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API 442*4882a593Smuzhiyun void (*update_hisr_hsisr_ind)(PADAPTER padapter, u32 flag); 443*4882a593Smuzhiyun int (*hal_gpio_func_check)(_adapter *padapter, u8 gpio_num); 444*4882a593Smuzhiyun void (*hal_gpio_multi_func_reset)(_adapter *padapter, u8 gpio_num); 445*4882a593Smuzhiyun #endif 446*4882a593Smuzhiyun #ifdef CONFIG_FW_CORRECT_BCN 447*4882a593Smuzhiyun void (*fw_correct_bcn)(PADAPTER padapter); 448*4882a593Smuzhiyun #endif 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun #ifdef RTW_HALMAC 451*4882a593Smuzhiyun u8(*init_mac_register)(PADAPTER); 452*4882a593Smuzhiyun u8(*init_phy)(PADAPTER); 453*4882a593Smuzhiyun #endif /* RTW_HALMAC */ 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 456*4882a593Smuzhiyun void (*hal_set_l1ssbackdoor_handler)(_adapter *padapter, u8 enable); 457*4882a593Smuzhiyun #endif 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun #ifdef CONFIG_RFKILL_POLL 460*4882a593Smuzhiyun bool (*hal_radio_onoff_check)(_adapter *adapter, u8 *valid); 461*4882a593Smuzhiyun #endif 462*4882a593Smuzhiyun #ifdef CONFIG_PCI_TX_POLLING 463*4882a593Smuzhiyun void (*tx_poll_handler)(_adapter *adapter); 464*4882a593Smuzhiyun #endif 465*4882a593Smuzhiyun void (*hci_flush)(_adapter *adapter, u32 queue); 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun typedef enum _RT_EEPROM_TYPE { 469*4882a593Smuzhiyun EEPROM_93C46, 470*4882a593Smuzhiyun EEPROM_93C56, 471*4882a593Smuzhiyun EEPROM_BOOT_EFUSE, 472*4882a593Smuzhiyun } RT_EEPROM_TYPE, *PRT_EEPROM_TYPE; 473*4882a593Smuzhiyun 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun 476*4882a593Smuzhiyun #define RF_CHANGE_BY_INIT 0 477*4882a593Smuzhiyun #define RF_CHANGE_BY_IPS BIT28 478*4882a593Smuzhiyun #define RF_CHANGE_BY_PS BIT29 479*4882a593Smuzhiyun #define RF_CHANGE_BY_HW BIT30 480*4882a593Smuzhiyun #define RF_CHANGE_BY_SW BIT31 481*4882a593Smuzhiyun 482*4882a593Smuzhiyun typedef enum _HARDWARE_TYPE { 483*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188EE, 484*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188EU, 485*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188ES, 486*4882a593Smuzhiyun /* NEW_GENERATION_IC */ 487*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192EE, 488*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192EU, 489*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192ES, 490*4882a593Smuzhiyun HARDWARE_TYPE_RTL8812E, 491*4882a593Smuzhiyun HARDWARE_TYPE_RTL8812AU, 492*4882a593Smuzhiyun HARDWARE_TYPE_RTL8811AU, 493*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821E, 494*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821U, 495*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821S, 496*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723BE, 497*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723BU, 498*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723BS, 499*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814AE, 500*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814AU, 501*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814AS, 502*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821BE, 503*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821BU, 504*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821BS, 505*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822BE, 506*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822BU, 507*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822BS, 508*4882a593Smuzhiyun HARDWARE_TYPE_RTL8703BE, 509*4882a593Smuzhiyun HARDWARE_TYPE_RTL8703BU, 510*4882a593Smuzhiyun HARDWARE_TYPE_RTL8703BS, 511*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188FE, 512*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188FU, 513*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188FS, 514*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188GTVU, 515*4882a593Smuzhiyun HARDWARE_TYPE_RTL8188GTVS, 516*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723DE, 517*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723DU, 518*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723DS, 519*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821CE, 520*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821CU, 521*4882a593Smuzhiyun HARDWARE_TYPE_RTL8821CS, 522*4882a593Smuzhiyun HARDWARE_TYPE_RTL8710BU, 523*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192FS, 524*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192FU, 525*4882a593Smuzhiyun HARDWARE_TYPE_RTL8192FE, 526*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822CE, 527*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822CU, 528*4882a593Smuzhiyun HARDWARE_TYPE_RTL8822CS, 529*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814BE, 530*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814BU, 531*4882a593Smuzhiyun HARDWARE_TYPE_RTL8814BS, 532*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723FU, 533*4882a593Smuzhiyun HARDWARE_TYPE_RTL8723FS, 534*4882a593Smuzhiyun HARDWARE_TYPE_MAX, 535*4882a593Smuzhiyun } HARDWARE_TYPE; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun #define IS_NEW_GENERATION_IC(_Adapter) (rtw_get_hw_type(_Adapter) >= HARDWARE_TYPE_RTL8192EE) 538*4882a593Smuzhiyun /* 539*4882a593Smuzhiyun * RTL8188E Series 540*4882a593Smuzhiyun * */ 541*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EE) 542*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188EU) 543*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188ES) 544*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188E(_Adapter) \ 545*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8188EE(_Adapter) || IS_HARDWARE_TYPE_8188EU(_Adapter) || IS_HARDWARE_TYPE_8188ES(_Adapter)) 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun /* RTL8812 Series */ 548*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812E) 549*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8812AU) 550*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8812(_Adapter) \ 551*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8812E(_Adapter) || IS_HARDWARE_TYPE_8812AU(_Adapter)) 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun /* RTL8821 Series */ 554*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821E(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821E) 555*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8811AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) 556*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821U(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821U || \ 557*4882a593Smuzhiyun rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8811AU) 558*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821S(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821S) 559*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821(_Adapter) \ 560*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8821E(_Adapter) || IS_HARDWARE_TYPE_8821U(_Adapter) || IS_HARDWARE_TYPE_8821S(_Adapter)) 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR(_Adapter) \ 563*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8812(_Adapter) || IS_HARDWARE_TYPE_8821(_Adapter)) 564*4882a593Smuzhiyun 565*4882a593Smuzhiyun /* RTL8192E Series */ 566*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192EE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EE) 567*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192EU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192EU) 568*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192ES(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192ES) 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192E(_Adapter) \ 571*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8192EE(_Adapter) || IS_HARDWARE_TYPE_8192EU(_Adapter) || IS_HARDWARE_TYPE_8192ES(_Adapter)) 572*4882a593Smuzhiyun 573*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BE) 574*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BU) 575*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723BS) 576*4882a593Smuzhiyun 577*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723B(_Adapter) \ 578*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8723BE(_Adapter) || IS_HARDWARE_TYPE_8723BU(_Adapter) || IS_HARDWARE_TYPE_8723BS(_Adapter)) 579*4882a593Smuzhiyun 580*4882a593Smuzhiyun /* RTL8814A Series */ 581*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AE) 582*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AU) 583*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814AS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814AS) 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814A(_Adapter) \ 586*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8814AE(_Adapter) || IS_HARDWARE_TYPE_8814AU(_Adapter) || IS_HARDWARE_TYPE_8814AS(_Adapter)) 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun /* RTL8703B Series */ 589*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BE) 590*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BS) 591*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8703BU) 592*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8703B(_Adapter) \ 593*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8703BE(_Adapter) || IS_HARDWARE_TYPE_8703BU(_Adapter) || IS_HARDWARE_TYPE_8703BS(_Adapter)) 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun /* RTL8723D Series */ 596*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DE(_Adapter)\ 597*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DE) 598*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DS(_Adapter)\ 599*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DS) 600*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723DU(_Adapter)\ 601*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723DU) 602*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723D(_Adapter)\ 603*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8723DE(_Adapter) || \ 604*4882a593Smuzhiyun IS_HARDWARE_TYPE_8723DU(_Adapter) || \ 605*4882a593Smuzhiyun IS_HARDWARE_TYPE_8723DS(_Adapter)) 606*4882a593Smuzhiyun 607*4882a593Smuzhiyun /* RTL8192F Series */ 608*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FS(_Adapter)\ 609*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FS) 610*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FU(_Adapter)\ 611*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FU) 612*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192FE(_Adapter)\ 613*4882a593Smuzhiyun (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8192FE) 614*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8192F(_Adapter)\ 615*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8192FS(_Adapter) ||\ 616*4882a593Smuzhiyun IS_HARDWARE_TYPE_8192FU(_Adapter) ||\ 617*4882a593Smuzhiyun IS_HARDWARE_TYPE_8192FE(_Adapter)) 618*4882a593Smuzhiyun 619*4882a593Smuzhiyun /* RTL8188F Series */ 620*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FE) 621*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FS) 622*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188FU) 623*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188F(_Adapter) \ 624*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8188FE(_Adapter) || IS_HARDWARE_TYPE_8188FU(_Adapter) || IS_HARDWARE_TYPE_8188FS(_Adapter)) 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188GTVU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVU) 627*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188GTVS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8188GTVS) 628*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8188GTV(_Adapter) \ 629*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8188GTVU(_Adapter) || IS_HARDWARE_TYPE_8188GTVS(_Adapter)) 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun /* RTL8710B Series */ 632*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8710BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8710BU) 633*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8710B(_Adapter) (IS_HARDWARE_TYPE_8710BU(_Adapter)) 634*4882a593Smuzhiyun 635*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BE) 636*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BU) 637*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821BS) 638*4882a593Smuzhiyun 639*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821B(_Adapter) \ 640*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8821BE(_Adapter) || IS_HARDWARE_TYPE_8821BU(_Adapter) || IS_HARDWARE_TYPE_8821BS(_Adapter)) 641*4882a593Smuzhiyun 642*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BE) 643*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BU) 644*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822BS) 645*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822B(_Adapter) \ 646*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8822BE(_Adapter) || IS_HARDWARE_TYPE_8822BU(_Adapter) || IS_HARDWARE_TYPE_8822BS(_Adapter)) 647*4882a593Smuzhiyun 648*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CE) 649*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CU) 650*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8821CS) 651*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8821C(_Adapter) \ 652*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8821CE(_Adapter) || IS_HARDWARE_TYPE_8821CU(_Adapter) || IS_HARDWARE_TYPE_8821CS(_Adapter)) 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CE) 655*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CU) 656*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822CS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8822CS) 657*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8822C(_Adapter) \ 658*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8822CE(_Adapter) || IS_HARDWARE_TYPE_8822CU(_Adapter) || IS_HARDWARE_TYPE_8822CS(_Adapter)) 659*4882a593Smuzhiyun 660*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BE(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BE) 661*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BU) 662*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814BS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8814BS) 663*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8814B(_Adapter) \ 664*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8814BE(_Adapter) || IS_HARDWARE_TYPE_8814BU(_Adapter) || IS_HARDWARE_TYPE_8814BS(_Adapter)) 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723FU(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FU) 667*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723FS(_Adapter) (rtw_get_hw_type(_Adapter) == HARDWARE_TYPE_RTL8723FS) 668*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_8723F(_Adapter) \ 669*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8723FU(_Adapter) || IS_HARDWARE_TYPE_8723FS(_Adapter)) 670*4882a593Smuzhiyun 671*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR2(_Adapter) \ 672*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8814A(_Adapter) || IS_HARDWARE_TYPE_8821B(_Adapter) || IS_HARDWARE_TYPE_8822B(_Adapter) || IS_HARDWARE_TYPE_8821C(_Adapter)) 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) \ 675*4882a593Smuzhiyun (IS_HARDWARE_TYPE_JAGUAR(_Adapter) || IS_HARDWARE_TYPE_JAGUAR2(_Adapter)) 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR3(_Adapter) \ 678*4882a593Smuzhiyun (IS_HARDWARE_TYPE_8814B(_Adapter) || IS_HARDWARE_TYPE_8822C(_Adapter)) 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR3_11N(_Adapter) IS_HARDWARE_TYPE_8723F(_Adapter) 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun #define IS_HARDWARE_TYPE_JAGUAR_ALL(_Adapter) \ 683*4882a593Smuzhiyun (IS_HARDWARE_TYPE_JAGUAR_AND_JAGUAR2(_Adapter) || IS_HARDWARE_TYPE_JAGUAR3(_Adapter)) 684*4882a593Smuzhiyun 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun typedef enum _wowlan_subcode { 687*4882a593Smuzhiyun WOWLAN_ENABLE = 0, 688*4882a593Smuzhiyun WOWLAN_DISABLE = 1, 689*4882a593Smuzhiyun WOWLAN_AP_ENABLE = 2, 690*4882a593Smuzhiyun WOWLAN_AP_DISABLE = 3, 691*4882a593Smuzhiyun WOWLAN_PATTERN_CLEAN = 4 692*4882a593Smuzhiyun } wowlan_subcode; 693*4882a593Smuzhiyun 694*4882a593Smuzhiyun struct wowlan_ioctl_param { 695*4882a593Smuzhiyun unsigned int subcode; 696*4882a593Smuzhiyun unsigned int subcode_value; 697*4882a593Smuzhiyun unsigned int wakeup_reason; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun u8 rtw_hal_data_init(_adapter *padapter); 701*4882a593Smuzhiyun void rtw_hal_data_deinit(_adapter *padapter); 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun void rtw_hal_def_value_init(_adapter *padapter); 704*4882a593Smuzhiyun 705*4882a593Smuzhiyun void rtw_hal_free_data(_adapter *padapter); 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun void rtw_hal_dm_init(_adapter *padapter); 708*4882a593Smuzhiyun void rtw_hal_dm_deinit(_adapter *padapter); 709*4882a593Smuzhiyun #ifdef CONFIG_RTW_SW_LED 710*4882a593Smuzhiyun void rtw_hal_sw_led_init(_adapter *padapter); 711*4882a593Smuzhiyun void rtw_hal_sw_led_deinit(_adapter *padapter); 712*4882a593Smuzhiyun #endif 713*4882a593Smuzhiyun u32 rtw_hal_power_on(_adapter *padapter); 714*4882a593Smuzhiyun void rtw_hal_power_off(_adapter *padapter); 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun uint rtw_hal_init(_adapter *padapter); 717*4882a593Smuzhiyun #ifdef CONFIG_NEW_NETDEV_HDL 718*4882a593Smuzhiyun uint rtw_hal_iface_init(_adapter *adapter); 719*4882a593Smuzhiyun #endif 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun enum rf_type rtw_chip_rftype_to_hal_rftype(_adapter *adapter, u8 limit); 722*4882a593Smuzhiyun void dump_hal_runtime_trx_mode(void *sel, _adapter *adapter); 723*4882a593Smuzhiyun void dump_hal_trx_mode(void *sel, _adapter *adapter); 724*4882a593Smuzhiyun u8 rtw_hal_rfpath_init(_adapter *adapter); 725*4882a593Smuzhiyun u8 rtw_hal_trxnss_init(_adapter *adapter); 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun uint rtw_hal_deinit(_adapter *padapter); 728*4882a593Smuzhiyun void rtw_hal_stop(_adapter *padapter); 729*4882a593Smuzhiyun u8 rtw_hal_set_hwreg(PADAPTER padapter, u8 variable, u8 *val); 730*4882a593Smuzhiyun void rtw_hal_get_hwreg(PADAPTER padapter, u8 variable, u8 *val); 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun void rtw_hal_chip_configure(_adapter *padapter); 733*4882a593Smuzhiyun u8 rtw_hal_read_chip_info(_adapter *padapter); 734*4882a593Smuzhiyun void rtw_hal_read_chip_version(_adapter *padapter); 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun u8 rtw_hal_set_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue); 737*4882a593Smuzhiyun u8 rtw_hal_get_def_var(_adapter *padapter, HAL_DEF_VARIABLE eVariable, void *pValue); 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun void rtw_hal_set_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, BOOLEAN bSet); 740*4882a593Smuzhiyun void rtw_hal_get_odm_var(_adapter *padapter, HAL_ODM_VARIABLE eVariable, void *pValue1, void *pValue2); 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun void rtw_hal_enable_interrupt(_adapter *padapter); 743*4882a593Smuzhiyun void rtw_hal_disable_interrupt(_adapter *padapter); 744*4882a593Smuzhiyun 745*4882a593Smuzhiyun u8 rtw_hal_check_ips_status(_adapter *padapter); 746*4882a593Smuzhiyun 747*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI) 748*4882a593Smuzhiyun u32 rtw_hal_inirp_init(_adapter *padapter); 749*4882a593Smuzhiyun u32 rtw_hal_inirp_deinit(_adapter *padapter); 750*4882a593Smuzhiyun #endif 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI) 753*4882a593Smuzhiyun void rtw_hal_irp_reset(_adapter *padapter); 754*4882a593Smuzhiyun void rtw_hal_pci_dbi_write(_adapter *padapter, u16 addr, u8 data); 755*4882a593Smuzhiyun u8 rtw_hal_pci_dbi_read(_adapter *padapter, u16 addr); 756*4882a593Smuzhiyun void rtw_hal_pci_mdio_write(_adapter *padapter, u8 addr, u16 data); 757*4882a593Smuzhiyun u16 rtw_hal_pci_mdio_read(_adapter *padapter, u8 addr); 758*4882a593Smuzhiyun u8 rtw_hal_pci_l1off_nic_support(_adapter *padapter); 759*4882a593Smuzhiyun u8 rtw_hal_pci_l1off_capability(_adapter *padapter); 760*4882a593Smuzhiyun #endif 761*4882a593Smuzhiyun 762*4882a593Smuzhiyun u8 rtw_hal_intf_ps_func(_adapter *padapter, HAL_INTF_PS_FUNC efunc_id, u8 *val); 763*4882a593Smuzhiyun 764*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE 765*4882a593Smuzhiyun s32 rtw_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 766*4882a593Smuzhiyun #endif 767*4882a593Smuzhiyun s32 rtw_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); 768*4882a593Smuzhiyun s32 rtw_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); 769*4882a593Smuzhiyun s32 rtw_hal_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun s32 rtw_hal_init_xmit_priv(_adapter *padapter); 772*4882a593Smuzhiyun void rtw_hal_free_xmit_priv(_adapter *padapter); 773*4882a593Smuzhiyun 774*4882a593Smuzhiyun s32 rtw_hal_init_recv_priv(_adapter *padapter); 775*4882a593Smuzhiyun void rtw_hal_free_recv_priv(_adapter *padapter); 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun void rtw_hal_update_ra_mask(struct sta_info *psta); 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun void rtw_hal_start_thread(_adapter *padapter); 780*4882a593Smuzhiyun void rtw_hal_stop_thread(_adapter *padapter); 781*4882a593Smuzhiyun 782*4882a593Smuzhiyun void rtw_hal_bcn_related_reg_setting(_adapter *padapter); 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun u32 rtw_hal_read_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask); 785*4882a593Smuzhiyun void rtw_hal_write_bbreg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 786*4882a593Smuzhiyun u32 rtw_hal_read_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask); 787*4882a593Smuzhiyun void rtw_hal_write_rfreg(_adapter *padapter, enum rf_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun 790*4882a593Smuzhiyun #define phy_query_bb_reg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) 791*4882a593Smuzhiyun #define phy_set_bb_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) 792*4882a593Smuzhiyun #define phy_query_rf_reg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) 793*4882a593Smuzhiyun #define phy_set_rf_reg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) 794*4882a593Smuzhiyun 795*4882a593Smuzhiyun #ifdef CONFIG_SYSON_INDIRECT_ACCESS 796*4882a593Smuzhiyun u32 rtw_hal_read_syson_reg(PADAPTER padapter, u32 RegAddr, u32 BitMask); 797*4882a593Smuzhiyun void rtw_hal_write_syson_reg(_adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 798*4882a593Smuzhiyun #define hal_query_syson_reg(Adapter, RegAddr, BitMask) rtw_hal_read_syson_reg((Adapter), (RegAddr), (BitMask)) 799*4882a593Smuzhiyun #define hal_set_syson_reg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_syson_reg((Adapter), (RegAddr), (BitMask), (Data)) 800*4882a593Smuzhiyun #endif 801*4882a593Smuzhiyun 802*4882a593Smuzhiyun #define phy_set_mac_reg phy_set_bb_reg 803*4882a593Smuzhiyun #define phy_query_mac_reg phy_query_bb_reg 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI) 806*4882a593Smuzhiyun s32 rtw_hal_interrupt_handler(_adapter *padapter); 807*4882a593Smuzhiyun void rtw_hal_unmap_beacon_icf(_adapter *padapter); 808*4882a593Smuzhiyun #endif 809*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT) 810*4882a593Smuzhiyun void rtw_hal_interrupt_handler(_adapter *padapter, u16 pkt_len, u8 *pbuf); 811*4882a593Smuzhiyun #endif 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun void rtw_hal_set_chnl_bw(_adapter *padapter, u8 channel, enum channel_width Bandwidth, u8 Offset40, u8 Offset80); 814*4882a593Smuzhiyun void rtw_hal_dm_watchdog(_adapter *padapter); 815*4882a593Smuzhiyun void rtw_hal_dm_watchdog_in_lps(_adapter *padapter); 816*4882a593Smuzhiyun 817*4882a593Smuzhiyun #ifdef CONFIG_HOSTAPD_MLME 818*4882a593Smuzhiyun s32 rtw_hal_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); 819*4882a593Smuzhiyun #endif 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT 822*4882a593Smuzhiyun void rtw_hal_sreset_init(_adapter *padapter); 823*4882a593Smuzhiyun void rtw_hal_sreset_reset(_adapter *padapter); 824*4882a593Smuzhiyun void rtw_hal_sreset_reset_value(_adapter *padapter); 825*4882a593Smuzhiyun void rtw_hal_sreset_xmit_status_check(_adapter *padapter); 826*4882a593Smuzhiyun void rtw_hal_sreset_linked_status_check(_adapter *padapter); 827*4882a593Smuzhiyun u8 rtw_hal_sreset_get_wifi_status(_adapter *padapter); 828*4882a593Smuzhiyun bool rtw_hal_sreset_inprogress(_adapter *padapter); 829*4882a593Smuzhiyun #endif 830*4882a593Smuzhiyun 831*4882a593Smuzhiyun #ifdef CONFIG_IOL 832*4882a593Smuzhiyun int rtw_hal_iol_cmd(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms, u32 bndy_cnt); 833*4882a593Smuzhiyun #endif 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE 836*4882a593Smuzhiyun s32 rtw_hal_xmit_thread_handler(_adapter *padapter); 837*4882a593Smuzhiyun #endif 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun #ifdef CONFIG_RECV_THREAD_MODE 840*4882a593Smuzhiyun s32 rtw_hal_recv_hdl(_adapter *adapter); 841*4882a593Smuzhiyun #endif 842*4882a593Smuzhiyun 843*4882a593Smuzhiyun void rtw_hal_notch_filter(_adapter *adapter, bool enable); 844*4882a593Smuzhiyun 845*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_REG 846*4882a593Smuzhiyun bool rtw_hal_c2h_reg_hdr_parse(_adapter *adapter, u8 *buf, u8 *id, u8 *seq, u8 *plen, u8 **payload); 847*4882a593Smuzhiyun bool rtw_hal_c2h_valid(_adapter *adapter, u8 *buf); 848*4882a593Smuzhiyun s32 rtw_hal_c2h_evt_read(_adapter *adapter, u8 *buf); 849*4882a593Smuzhiyun #endif 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun #ifdef CONFIG_FW_C2H_PKT 852*4882a593Smuzhiyun bool rtw_hal_c2h_pkt_hdr_parse(_adapter *adapter, u8 *buf, u16 len, u8 *id, u8 *seq, u8 *plen, u8 **payload); 853*4882a593Smuzhiyun #endif 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun s32 c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); 856*4882a593Smuzhiyun #ifndef RTW_HALMAC 857*4882a593Smuzhiyun s32 rtw_hal_c2h_handler(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); 858*4882a593Smuzhiyun s32 rtw_hal_c2h_id_handle_directly(_adapter *adapter, u8 id, u8 seq, u8 plen, u8 *payload); 859*4882a593Smuzhiyun #endif 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun s32 rtw_hal_macid_sleep(_adapter *adapter, u8 macid); 862*4882a593Smuzhiyun s32 rtw_hal_macid_wakeup(_adapter *adapter, u8 macid); 863*4882a593Smuzhiyun s32 rtw_hal_macid_sleep_all_used(_adapter *adapter); 864*4882a593Smuzhiyun s32 rtw_hal_macid_wakeup_all_used(_adapter *adapter); 865*4882a593Smuzhiyun 866*4882a593Smuzhiyun s32 rtw_hal_macid_drop(_adapter *adapter, u8 macid); 867*4882a593Smuzhiyun s32 rtw_hal_macid_undrop(_adapter *adapter, u8 macid); 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun s32 rtw_hal_fill_h2c_cmd(PADAPTER padapter, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); 870*4882a593Smuzhiyun void rtw_hal_fill_fake_txdesc(_adapter *padapter, u8 *pDesc, u32 BufferLen, 871*4882a593Smuzhiyun u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame); 872*4882a593Smuzhiyun u8 rtw_hal_get_txbuff_rsvd_page_num(_adapter *adapter, bool wowlan); 873*4882a593Smuzhiyun 874*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API 875*4882a593Smuzhiyun void rtw_hal_update_hisr_hsisr_ind(_adapter *padapter, u32 flag); 876*4882a593Smuzhiyun int rtw_hal_gpio_func_check(_adapter *padapter, u8 gpio_num); 877*4882a593Smuzhiyun void rtw_hal_gpio_multi_func_reset(_adapter *padapter, u8 gpio_num); 878*4882a593Smuzhiyun #endif 879*4882a593Smuzhiyun #ifdef CONFIG_FW_CORRECT_BCN 880*4882a593Smuzhiyun void rtw_hal_fw_correct_bcn(_adapter *padapter); 881*4882a593Smuzhiyun #endif 882*4882a593Smuzhiyun s32 rtw_hal_fw_dl(_adapter *padapter, u8 wowlan); 883*4882a593Smuzhiyun 884*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 885*4882a593Smuzhiyun void rtw_hal_clear_interrupt(_adapter *padapter); 886*4882a593Smuzhiyun #endif 887*4882a593Smuzhiyun 888*4882a593Smuzhiyun void rtw_hal_set_tx_power_level(_adapter *adapter, u8 channel); 889*4882a593Smuzhiyun void rtw_hal_update_txpwr_level(_adapter *adapter); 890*4882a593Smuzhiyun void rtw_hal_set_txpwr_done(_adapter *adapter); 891*4882a593Smuzhiyun void rtw_hal_set_tx_power_index(_adapter *adapter, u32 powerindex 892*4882a593Smuzhiyun , enum rf_path rfpath, u8 rate); 893*4882a593Smuzhiyun 894*4882a593Smuzhiyun u8 rtw_hal_get_tx_power_index(_adapter *adapter, enum rf_path rfpath 895*4882a593Smuzhiyun , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch, u8 opch 896*4882a593Smuzhiyun , struct txpwr_idx_comp *tic); 897*4882a593Smuzhiyun s8 rtw_hal_get_txpwr_target_extra_bias(_adapter *adapter, enum rf_path rfpath 898*4882a593Smuzhiyun , RATE_SECTION rs, enum MGN_RATE rate, enum channel_width bw, BAND_TYPE band, u8 cch); 899*4882a593Smuzhiyun 900*4882a593Smuzhiyun u8 rtw_hal_ops_check(_adapter *padapter); 901*4882a593Smuzhiyun 902*4882a593Smuzhiyun #ifdef RTW_HALMAC 903*4882a593Smuzhiyun u8 rtw_hal_init_mac_register(PADAPTER); 904*4882a593Smuzhiyun u8 rtw_hal_init_phy(PADAPTER); 905*4882a593Smuzhiyun s32 rtw_hal_fw_mem_dl(_adapter *padapter, enum fw_mem mem); 906*4882a593Smuzhiyun #endif /* RTW_HALMAC */ 907*4882a593Smuzhiyun 908*4882a593Smuzhiyun #ifdef CONFIG_RFKILL_POLL 909*4882a593Smuzhiyun bool rtw_hal_rfkill_poll(_adapter *adapter, u8 *valid); 910*4882a593Smuzhiyun #endif 911*4882a593Smuzhiyun 912*4882a593Smuzhiyun #endif /* __HAL_INTF_H__ */ 913