1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2019 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __HAL_IC_CFG_H__ 16*4882a593Smuzhiyun #define __HAL_IC_CFG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define RTL8188E_SUPPORT 0 19*4882a593Smuzhiyun #define RTL8812A_SUPPORT 0 20*4882a593Smuzhiyun #define RTL8821A_SUPPORT 0 21*4882a593Smuzhiyun #define RTL8723B_SUPPORT 0 22*4882a593Smuzhiyun #define RTL8723D_SUPPORT 0 23*4882a593Smuzhiyun #define RTL8723F_SUPPORT 0 24*4882a593Smuzhiyun #define RTL8192E_SUPPORT 0 25*4882a593Smuzhiyun #define RTL8192F_SUPPORT 0 26*4882a593Smuzhiyun #define RTL8814A_SUPPORT 0 27*4882a593Smuzhiyun #define RTL8195A_SUPPORT 0 28*4882a593Smuzhiyun #define RTL8197F_SUPPORT 0 29*4882a593Smuzhiyun #define RTL8703B_SUPPORT 0 30*4882a593Smuzhiyun #define RTL8188F_SUPPORT 0 31*4882a593Smuzhiyun #define RTL8822B_SUPPORT 0 32*4882a593Smuzhiyun #define RTL8821B_SUPPORT 0 33*4882a593Smuzhiyun #define RTL8821C_SUPPORT 0 34*4882a593Smuzhiyun #define RTL8710B_SUPPORT 0 35*4882a593Smuzhiyun #define RTL8814B_SUPPORT 0 36*4882a593Smuzhiyun #define RTL8824B_SUPPORT 0 37*4882a593Smuzhiyun #define RTL8198F_SUPPORT 0 38*4882a593Smuzhiyun #define RTL8195B_SUPPORT 0 39*4882a593Smuzhiyun #define RTL8822C_SUPPORT 0 40*4882a593Smuzhiyun #define RTL8721D_SUPPORT 0 41*4882a593Smuzhiyun #define RTL8812F_SUPPORT 0 42*4882a593Smuzhiyun #define RTL8197G_SUPPORT 0 43*4882a593Smuzhiyun #define RTL8710C_SUPPORT 0 44*4882a593Smuzhiyun #define RTL8814C_SUPPORT 0 45*4882a593Smuzhiyun #define RTL8735B_SUPPORT 0 46*4882a593Smuzhiyun #define RTL8730A_SUPPORT 0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /*#if (RTL8188E_SUPPORT==1)*/ 49*4882a593Smuzhiyun #define RATE_ADAPTIVE_SUPPORT 0 50*4882a593Smuzhiyun #define POWER_TRAINING_ACTIVE 0 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #ifdef CONFIG_MULTIDRV 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #ifdef CONFIG_RTL8188E 56*4882a593Smuzhiyun #undef RTL8188E_SUPPORT 57*4882a593Smuzhiyun #undef RATE_ADAPTIVE_SUPPORT 58*4882a593Smuzhiyun #undef POWER_TRAINING_ACTIVE 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define RTL8188E_SUPPORT 1 61*4882a593Smuzhiyun #define RATE_ADAPTIVE_SUPPORT 1 62*4882a593Smuzhiyun #define POWER_TRAINING_ACTIVE 1 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 65*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 66*4882a593Smuzhiyun #endif 67*4882a593Smuzhiyun #endif 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #ifdef CONFIG_RTL8812A 70*4882a593Smuzhiyun #undef RTL8812A_SUPPORT 71*4882a593Smuzhiyun #define RTL8812A_SUPPORT 1 72*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 73*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 74*4882a593Smuzhiyun #endif 75*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 76*4882a593Smuzhiyun #define CONFIG_BEAMFORMER_FW_NDPA 77*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 78*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 79*4882a593Smuzhiyun #endif /*CONFIG_BEAMFORMING*/ 80*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 83*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 84*4882a593Smuzhiyun #endif 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifdef CONFIG_RTL8821A 88*4882a593Smuzhiyun #undef RTL8821A_SUPPORT 89*4882a593Smuzhiyun #define RTL8821A_SUPPORT 1 90*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 91*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 92*4882a593Smuzhiyun #endif 93*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 94*4882a593Smuzhiyun #define CONFIG_BEAMFORMER_FW_NDPA 95*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 96*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 97*4882a593Smuzhiyun #endif 98*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 101*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 102*4882a593Smuzhiyun #endif 103*4882a593Smuzhiyun #endif 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun #ifdef CONFIG_RTL8192E 106*4882a593Smuzhiyun #undef RTL8192E_SUPPORT 107*4882a593Smuzhiyun #define RTL8192E_SUPPORT 1 108*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 109*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 114*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 115*4882a593Smuzhiyun #endif 116*4882a593Smuzhiyun #endif 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #ifdef CONFIG_RTL8192F 119*4882a593Smuzhiyun #undef RTL8192F_SUPPORT 120*4882a593Smuzhiyun #define RTL8192F_SUPPORT 1 121*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 122*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 123*4882a593Smuzhiyun #endif 124*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 125*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 126*4882a593Smuzhiyun #endif 127*4882a593Smuzhiyun /*#define CONFIG_AMPDU_PRETX_CD*/ 128*4882a593Smuzhiyun /*#define DBG_LA_MODE*/ 129*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 130*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 131*4882a593Smuzhiyun #endif 132*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 133*4882a593Smuzhiyun /* #define CONFIG_NARROWBAND_SUPPORTING */ 134*4882a593Smuzhiyun #ifdef CONFIG_NARROWBAND_SUPPORTING 135*4882a593Smuzhiyun #define CONFIG_NB_VALUE RTW_NB_CONFIG_NONE /*RTW_NB_CONFIG_WIDTH_10 or RTW_NB_CONFIG_WIDTH_5 */ 136*4882a593Smuzhiyun #endif 137*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 138*4882a593Smuzhiyun #define CONFIG_WOW_PATTERN_IN_TXFIFO 139*4882a593Smuzhiyun #endif 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 142*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 143*4882a593Smuzhiyun #endif 144*4882a593Smuzhiyun #define CONFIG_STOP_RESUME_BCN_BY_TXPAUSE /*to fixed no bcn issue*/ 145*4882a593Smuzhiyun #define CONFIG_TSF_SYNC 146*4882a593Smuzhiyun #endif 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #ifdef CONFIG_RTL8723B 149*4882a593Smuzhiyun #undef RTL8723B_SUPPORT 150*4882a593Smuzhiyun #define RTL8723B_SUPPORT 1 151*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 152*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 153*4882a593Smuzhiyun #endif 154*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 157*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 158*4882a593Smuzhiyun #endif 159*4882a593Smuzhiyun #endif 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #ifdef CONFIG_RTL8723D 162*4882a593Smuzhiyun #undef RTL8723D_SUPPORT 163*4882a593Smuzhiyun #define RTL8723D_SUPPORT 1 164*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 165*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 166*4882a593Smuzhiyun #endif 167*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 168*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 169*4882a593Smuzhiyun #endif 170*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 171*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 172*4882a593Smuzhiyun #endif 173*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 176*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 177*4882a593Smuzhiyun #endif 178*4882a593Smuzhiyun #endif 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #ifdef CONFIG_RTL8814A 181*4882a593Smuzhiyun #undef RTL8814A_SUPPORT 182*4882a593Smuzhiyun #define RTL8814A_SUPPORT 1 183*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 184*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 185*4882a593Smuzhiyun #endif 186*4882a593Smuzhiyun #define CONFIG_FW_CORRECT_BCN 187*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 188*4882a593Smuzhiyun #define BEAMFORMING_SUPPORT 1 /*for phydm beamforming*/ 189*4882a593Smuzhiyun #define SUPPORT_MU_BF 0 190*4882a593Smuzhiyun #endif 191*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 194*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 195*4882a593Smuzhiyun #endif 196*4882a593Smuzhiyun #endif 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun #ifdef CONFIG_RTL8703B 199*4882a593Smuzhiyun #undef RTL8703B_SUPPORT 200*4882a593Smuzhiyun #define RTL8703B_SUPPORT 1 201*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 202*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 203*4882a593Smuzhiyun #endif 204*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 205*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 206*4882a593Smuzhiyun #endif 207*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 210*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 211*4882a593Smuzhiyun #endif 212*4882a593Smuzhiyun #endif 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #ifdef CONFIG_RTL8188F 215*4882a593Smuzhiyun #undef RTL8188F_SUPPORT 216*4882a593Smuzhiyun #define RTL8188F_SUPPORT 1 217*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 218*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 219*4882a593Smuzhiyun #endif 220*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 221*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 222*4882a593Smuzhiyun #endif 223*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 224*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 225*4882a593Smuzhiyun #endif 226*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 229*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 230*4882a593Smuzhiyun #endif 231*4882a593Smuzhiyun #endif 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #ifdef CONFIG_RTL8188GTV 234*4882a593Smuzhiyun #undef RTL8188F_SUPPORT 235*4882a593Smuzhiyun #define RTL8188F_SUPPORT 1 236*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 237*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 238*4882a593Smuzhiyun #endif 239*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 240*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 241*4882a593Smuzhiyun #endif 242*4882a593Smuzhiyun #ifndef CONFIG_RTW_CUSTOMER_STR 243*4882a593Smuzhiyun #define CONFIG_RTW_CUSTOMER_STR 244*4882a593Smuzhiyun #endif 245*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 248*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 249*4882a593Smuzhiyun #endif 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && !defined(CONFIG_FW_OFFLOAD_SET_TXPWR_IDX) 252*4882a593Smuzhiyun #define CONFIG_FW_OFFLOAD_SET_TXPWR_IDX 253*4882a593Smuzhiyun #endif 254*4882a593Smuzhiyun #endif 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun #ifdef CONFIG_RTL8822B 257*4882a593Smuzhiyun #undef RTL8822B_SUPPORT 258*4882a593Smuzhiyun #define RTL8822B_SUPPORT 1 259*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 260*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 261*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 262*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 263*4882a593Smuzhiyun #define RTW_AMPDU_AGG_RETRY_AND_NEW 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 266*4882a593Smuzhiyun #define CONFIG_GTK_OL 267*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 270*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 271*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 272*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 273*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 274*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 277*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 278*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 279*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun /* 282*4882a593Smuzhiyun * Beamforming related definition 283*4882a593Smuzhiyun */ 284*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 285*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 286*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 287*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 290*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 291*4882a593Smuzhiyun #endif /* CONFIG_RTW_MAC_HIDDEN_RPT */ 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 294*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 295*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 298*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 299*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* Checksum offload feature */ 302*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ 303*4882a593Smuzhiyun #if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG) 304*4882a593Smuzhiyun #define CONFIG_RTW_NETIF_SG 305*4882a593Smuzhiyun #endif 306*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 311*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 312*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 313*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 316*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 317*4882a593Smuzhiyun #endif 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 320*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 321*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 322*4882a593Smuzhiyun #endif 323*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 326*4882a593Smuzhiyun /* Supported since fw v22.1 */ 327*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 328*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 329*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 330*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 331*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 332*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 333*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 334*4882a593Smuzhiyun #endif 335*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 336*4882a593Smuzhiyun 337*4882a593Smuzhiyun #ifdef CONFIG_LPS 338*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v30 & v27.9 */ 339*4882a593Smuzhiyun #endif 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 342*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 343*4882a593Smuzhiyun #endif 344*4882a593Smuzhiyun #endif /* CONFIG_RTL8822B */ 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C 347*4882a593Smuzhiyun #undef RTL8822C_SUPPORT 348*4882a593Smuzhiyun #define RTL8822C_SUPPORT 1 349*4882a593Smuzhiyun /*#define DBG_LA_MODE*/ 350*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 351*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 352*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 353*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 354*4882a593Smuzhiyun 355*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 356*4882a593Smuzhiyun #define CONFIG_GTK_OL 357*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 360*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 361*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 362*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 363*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 364*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 367*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 368*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 369*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun /* 372*4882a593Smuzhiyun * Beamforming related definition 373*4882a593Smuzhiyun */ 374*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 375*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 376*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 377*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun #ifdef CONFIG_NO_FW 380*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 381*4882a593Smuzhiyun #undef CONFIG_RTW_MAC_HIDDEN_RPT 382*4882a593Smuzhiyun #endif 383*4882a593Smuzhiyun #else 384*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 385*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 386*4882a593Smuzhiyun #endif 387*4882a593Smuzhiyun #endif 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 390*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 391*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 394*4882a593Smuzhiyun /* #define RTW_IQK_FW_OFFLOAD */ 395*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 396*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 399*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 400*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 401*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 404*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 405*4882a593Smuzhiyun #endif 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 408*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 409*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 410*4882a593Smuzhiyun #endif 411*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 414*4882a593Smuzhiyun /* Supported since fw v22.1 */ 415*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 416*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 417*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 418*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 419*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 420*4882a593Smuzhiyun 421*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ 422*4882a593Smuzhiyun #if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG) 423*4882a593Smuzhiyun #define CONFIG_RTW_NETIF_SG 424*4882a593Smuzhiyun #endif 425*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 428*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 429*4882a593Smuzhiyun #endif 430*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun #ifdef CONFIG_LPS 433*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v07 */ 434*4882a593Smuzhiyun #define CONFIG_LPS_1T1R /* Supported after FW v07 */ 435*4882a593Smuzhiyun #endif 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun #define CONFIG_BT_EFUSE_MASK 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 440*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 441*4882a593Smuzhiyun #endif 442*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 443*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 444*4882a593Smuzhiyun #endif 445*4882a593Smuzhiyun 446*4882a593Smuzhiyun #define CONFIG_RTL8822C_XCAP_NEW_POLICY 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun /*#define CONFIG_NARROWBAND_SUPPORTING*/ 449*4882a593Smuzhiyun #ifdef CONFIG_NARROWBAND_SUPPORTING 450*4882a593Smuzhiyun #define CONFIG_NB_VALUE RTW_NB_CONFIG_WIDTH_10 /* RTW_NB_CONFIG_NONE / RTW_NB_CONFIG_WIDTH_10 / RTW_NB_CONFIG_WIDTH_5 */ 451*4882a593Smuzhiyun #endif 452*4882a593Smuzhiyun #define CONFIG_SUPPORT_DYNAMIC_TXPWR 453*4882a593Smuzhiyun #endif /* CONFIG_RTL8822C */ 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #ifdef CONFIG_RTL8821C 456*4882a593Smuzhiyun #undef RTL8821C_SUPPORT 457*4882a593Smuzhiyun #define RTL8821C_SUPPORT 1 458*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 459*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 460*4882a593Smuzhiyun #endif 461*4882a593Smuzhiyun #ifdef CONFIG_NO_FW 462*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 463*4882a593Smuzhiyun #undef CONFIG_RTW_MAC_HIDDEN_RPT 464*4882a593Smuzhiyun #endif 465*4882a593Smuzhiyun #else 466*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 467*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 468*4882a593Smuzhiyun #endif 469*4882a593Smuzhiyun #endif 470*4882a593Smuzhiyun #define LOAD_FW_HEADER_FROM_DRIVER 471*4882a593Smuzhiyun #define CONFIG_PHY_CAPABILITY_QUERY 472*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 473*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 474*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 475*4882a593Smuzhiyun #endif 476*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 477*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 478*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 479*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 480*4882a593Smuzhiyun /*#define CONFIG_AMPDU_PRETX_CD*/ 481*4882a593Smuzhiyun /*#define DBG_PRE_TX_HANG*/ 482*4882a593Smuzhiyun 483*4882a593Smuzhiyun /* Beamforming related definition */ 484*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 485*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 486*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 487*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 488*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 489*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 490*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 491*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 492*4882a593Smuzhiyun #endif 493*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 494*4882a593Smuzhiyun 495*4882a593Smuzhiyun #ifdef CONFIG_LPS 496*4882a593Smuzhiyun /* #define CONFIG_LPS_ACK */ /* Supported after FW v25 */ 497*4882a593Smuzhiyun #endif 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 500*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 501*4882a593Smuzhiyun #endif 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun #define CONFIG_BT_EFUSE_MASK 504*4882a593Smuzhiyun #endif /*CONFIG_RTL8821C*/ 505*4882a593Smuzhiyun 506*4882a593Smuzhiyun #ifdef CONFIG_RTL8710B 507*4882a593Smuzhiyun #undef RTL8710B_SUPPORT 508*4882a593Smuzhiyun #define RTL8710B_SUPPORT 1 509*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 510*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 511*4882a593Smuzhiyun #endif 512*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 513*4882a593Smuzhiyun 514*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 515*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 516*4882a593Smuzhiyun #endif 517*4882a593Smuzhiyun #endif 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun #ifdef CONFIG_RTL8814B 520*4882a593Smuzhiyun #undef RTL8814B_SUPPORT 521*4882a593Smuzhiyun #define RTL8814B_SUPPORT 1 522*4882a593Smuzhiyun #ifdef CONFIG_RTL8814C 523*4882a593Smuzhiyun #undef RTL8814C_SUPPORT 524*4882a593Smuzhiyun #define RTL8814C_SUPPORT 1 525*4882a593Smuzhiyun #endif 526*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 527*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 528*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 529*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 530*4882a593Smuzhiyun #define RTW_AMPDU_AGG_RETRY_AND_NEW 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 533*4882a593Smuzhiyun #define CONFIG_GTK_OL 534*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 537*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 538*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 6 /* WIFI Chip Side */ 539*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 540*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 541*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 544*4882a593Smuzhiyun /*#define CONFIG_AP_PORT_SWAP*/ 545*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 546*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 547*4882a593Smuzhiyun 548*4882a593Smuzhiyun /* 549*4882a593Smuzhiyun * Beamforming related definition 550*4882a593Smuzhiyun */ 551*4882a593Smuzhiyun /* Only support new beamforming mechanism */ 552*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING 553*4882a593Smuzhiyun #define RTW_BEAMFORMING_VERSION_2 554*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */ 555*4882a593Smuzhiyun 556*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 557*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 558*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun #ifndef RTW_IQK_FW_OFFLOAD 561*4882a593Smuzhiyun #define RTW_IQK_FW_OFFLOAD 562*4882a593Smuzhiyun #endif /* RTW_IQK_FW_OFFLOAD */ 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun /* Checksum offload feature */ 565*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ /* not ready */ 566*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 571*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 572*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 573*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 576*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 577*4882a593Smuzhiyun #endif 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 580*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 581*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 582*4882a593Smuzhiyun #endif 583*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 584*4882a593Smuzhiyun 585*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 586*4882a593Smuzhiyun /* Supported since fw v22.1 */ 587*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 588*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 589*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 590*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 591*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 592*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 593*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 594*4882a593Smuzhiyun #endif 595*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 596*4882a593Smuzhiyun 597*4882a593Smuzhiyun #define CONFIG_PROTSEL_PORT 598*4882a593Smuzhiyun #define CONFIG_PROTSEL_ATIMDTIM 599*4882a593Smuzhiyun #define CONFIG_PROTSEL_MACSLEEP 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_BCN_CTRL_ADDR 602*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_BCN_FUNC 603*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_MLME_DISCONNECT 604*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_MLME_JOIN 605*4882a593Smuzhiyun #define CONFIG_HAS_HW_VAR_CORRECT_TSF 606*4882a593Smuzhiyun #define CONFIG_HAS_TX_BEACON_PAUSE 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun #define CONFIG_RTW_TX_NPATH_EN /* 8814B is always 4TX */ 609*4882a593Smuzhiyun 610*4882a593Smuzhiyun #ifdef CONFIG_LPS 611*4882a593Smuzhiyun #define CONFIG_LPS_ACK /* Supported after FW v04 */ 612*4882a593Smuzhiyun #endif 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 615*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 616*4882a593Smuzhiyun #endif 617*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 618*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 619*4882a593Smuzhiyun #endif 620*4882a593Smuzhiyun #endif /* CONFIG_RTL8814B */ 621*4882a593Smuzhiyun #ifdef CONFIG_RTL8723F 622*4882a593Smuzhiyun #undef RTL8723F_SUPPORT 623*4882a593Smuzhiyun #define RTL8723F_SUPPORT 1 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun /* Use HALMAC architecture, necessary for 8723F */ 626*4882a593Smuzhiyun #define RTW_HALMAC 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun /*#define DBG_LA_MODE*/ 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun #ifndef CONFIG_FW_C2H_PKT 631*4882a593Smuzhiyun #define CONFIG_FW_C2H_PKT 632*4882a593Smuzhiyun #endif /* CONFIG_FW_C2H_PKT */ 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun #define RTW_TX_PA_BIAS /* Adjust TX PA Bias from eFuse */ 635*4882a593Smuzhiyun 636*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 637*4882a593Smuzhiyun #define CONFIG_WOW_PATTERN_IN_TXFIFO 638*4882a593Smuzhiyun #endif 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN 641*4882a593Smuzhiyun #define CONFIG_GTK_OL 642*4882a593Smuzhiyun /*#define CONFIG_ARP_KEEP_ALIVE*/ 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP 645*4882a593Smuzhiyun #ifndef WAKEUP_GPIO_IDX 646*4882a593Smuzhiyun #define WAKEUP_GPIO_IDX 12 /* WIFI Chip Side */ 647*4882a593Smuzhiyun #endif /* !WAKEUP_GPIO_IDX */ 648*4882a593Smuzhiyun #endif /* CONFIG_GPIO_WAKEUP */ 649*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */ 650*4882a593Smuzhiyun 651*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE 652*4882a593Smuzhiyun #define CONFIG_AP_PORT_SWAP 653*4882a593Smuzhiyun #define CONFIG_FW_MULTI_PORT_SUPPORT 654*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */ 655*4882a593Smuzhiyun 656*4882a593Smuzhiyun #ifdef CONFIG_NO_FW 657*4882a593Smuzhiyun #ifdef CONFIG_RTW_MAC_HIDDEN_RPT 658*4882a593Smuzhiyun #undef CONFIG_RTW_MAC_HIDDEN_RPT 659*4882a593Smuzhiyun #endif 660*4882a593Smuzhiyun #else 661*4882a593Smuzhiyun #ifndef CONFIG_RTW_MAC_HIDDEN_RPT 662*4882a593Smuzhiyun #define CONFIG_RTW_MAC_HIDDEN_RPT 663*4882a593Smuzhiyun #endif 664*4882a593Smuzhiyun #endif 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun #ifndef DBG_RX_DFRAME_RAW_DATA 667*4882a593Smuzhiyun #define DBG_RX_DFRAME_RAW_DATA 668*4882a593Smuzhiyun #endif /* DBG_RX_DFRAME_RAW_DATA */ 669*4882a593Smuzhiyun 670*4882a593Smuzhiyun /*#define RTW_IQK_FW_OFFLOAD*/ 671*4882a593Smuzhiyun #define CONFIG_ADVANCE_OTA 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE 674*4882a593Smuzhiyun #define CONFIG_MCC_MODE_V2 675*4882a593Smuzhiyun #define CONFIG_MCC_PHYDM_OFFLOAD 676*4882a593Smuzhiyun #endif /* CONFIG_MCC_MODE */ 677*4882a593Smuzhiyun 678*4882a593Smuzhiyun #if defined(CONFIG_TDLS) && defined(CONFIG_TDLS_CH_SW) 679*4882a593Smuzhiyun #define CONFIG_TDLS_CH_SW_V2 680*4882a593Smuzhiyun #endif 681*4882a593Smuzhiyun 682*4882a593Smuzhiyun #ifndef RTW_CHANNEL_SWITCH_OFFLOAD 683*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW_V2 684*4882a593Smuzhiyun #define RTW_CHANNEL_SWITCH_OFFLOAD 685*4882a593Smuzhiyun #endif 686*4882a593Smuzhiyun #endif /* RTW_CHANNEL_SWITCH_OFFLOAD */ 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun #if defined(CONFIG_RTW_MESH) && !defined(RTW_PER_CMD_SUPPORT_FW) 689*4882a593Smuzhiyun /* Supported since fw v22.1 */ 690*4882a593Smuzhiyun #define RTW_PER_CMD_SUPPORT_FW 691*4882a593Smuzhiyun #endif /* RTW_PER_CMD_SUPPORT_FW */ 692*4882a593Smuzhiyun #define CONFIG_SUPPORT_FIFO_DUMP 693*4882a593Smuzhiyun #define CONFIG_HW_P0_TSF_SYNC 694*4882a593Smuzhiyun #define CONFIG_BCN_RECV_TIME 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun /*#define CONFIG_TCP_CSUM_OFFLOAD_TX*/ 697*4882a593Smuzhiyun #if defined(CONFIG_TCP_CSUM_OFFLOAD_TX) && !defined(CONFIG_RTW_NETIF_SG) 698*4882a593Smuzhiyun #define CONFIG_RTW_NETIF_SG 699*4882a593Smuzhiyun #endif 700*4882a593Smuzhiyun #define CONFIG_TCP_CSUM_OFFLOAD_RX 701*4882a593Smuzhiyun 702*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS 703*4882a593Smuzhiyun #define CONFIG_P2P_PS_NOA_USE_MACID_SLEEP 704*4882a593Smuzhiyun #endif 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun #define CONFIG_RTS_FULL_BW 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun #ifdef CONFIG_LPS 709*4882a593Smuzhiyun #define CONFIG_LPS_ACK 710*4882a593Smuzhiyun #endif 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_PWR_IDX 713*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_PWR_IDX 714*4882a593Smuzhiyun #endif 715*4882a593Smuzhiyun #ifndef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 716*4882a593Smuzhiyun #define CONFIG_TXPWR_PG_WITH_TSSI_OFFSET 717*4882a593Smuzhiyun #endif 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun #define CONFIG_BT_EFUSE_MASK 720*4882a593Smuzhiyun 721*4882a593Smuzhiyun #define CONFIG_WRITE_BCN_LEN_TO_FW 722*4882a593Smuzhiyun #endif /* CONFIG_RTL8723F */ 723*4882a593Smuzhiyun #endif /*__HAL_IC_CFG_H__*/ 724