1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun *****************************************************************************/ 15*4882a593Smuzhiyun #ifndef __INC_HAL8812PHYCFG_H__ 16*4882a593Smuzhiyun #define __INC_HAL8812PHYCFG_H__ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/ 20*4882a593Smuzhiyun #define LOOP_LIMIT 5 21*4882a593Smuzhiyun #define MAX_STALL_TIME 50 /* us */ 22*4882a593Smuzhiyun #define AntennaDiversityValue 0x80 /* (Adapter->bSoftwareAntennaDiversity ? 0x00 : 0x80) */ 23*4882a593Smuzhiyun #define MAX_TXPWR_IDX_NMODE_92S 63 24*4882a593Smuzhiyun #define Reset_Cnt_Limit 3 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI 28*4882a593Smuzhiyun #define MAX_AGGR_NUM 0x0B 29*4882a593Smuzhiyun #else 30*4882a593Smuzhiyun #define MAX_AGGR_NUM 0x07 31*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */ 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /*--------------------------Define Parameters-------------------------------*/ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* BB/RF related */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /*------------------------------Define structure----------------------------*/ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/ 45*4882a593Smuzhiyun /*------------------------Export global variable----------------------------*/ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/ 49*4882a593Smuzhiyun /*------------------------Export Marco Definition---------------------------*/ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/ 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * BB and RF register read/write 55*4882a593Smuzhiyun * */ 56*4882a593Smuzhiyun u32 PHY_QueryBBReg8812(PADAPTER Adapter, 57*4882a593Smuzhiyun u32 RegAddr, 58*4882a593Smuzhiyun u32 BitMask); 59*4882a593Smuzhiyun void PHY_SetBBReg8812(PADAPTER Adapter, 60*4882a593Smuzhiyun u32 RegAddr, 61*4882a593Smuzhiyun u32 BitMask, 62*4882a593Smuzhiyun u32 Data); 63*4882a593Smuzhiyun u32 PHY_QueryRFReg8812(PADAPTER Adapter, 64*4882a593Smuzhiyun enum rf_path eRFPath, 65*4882a593Smuzhiyun u32 RegAddr, 66*4882a593Smuzhiyun u32 BitMask); 67*4882a593Smuzhiyun void PHY_SetRFReg8812(PADAPTER Adapter, 68*4882a593Smuzhiyun enum rf_path eRFPath, 69*4882a593Smuzhiyun u32 RegAddr, 70*4882a593Smuzhiyun u32 BitMask, 71*4882a593Smuzhiyun u32 Data); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * Initialization related function 75*4882a593Smuzhiyun * 76*4882a593Smuzhiyun * MAC/BB/RF HAL config */ 77*4882a593Smuzhiyun int PHY_MACConfig8812(PADAPTER Adapter); 78*4882a593Smuzhiyun int PHY_BBConfig8812(PADAPTER Adapter); 79*4882a593Smuzhiyun void PHY_BB8812_Config_1T(PADAPTER Adapter); 80*4882a593Smuzhiyun int PHY_RFConfig8812(PADAPTER Adapter); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* RF config */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun s32 85*4882a593Smuzhiyun PHY_SwitchWirelessBand8812( 86*4882a593Smuzhiyun PADAPTER Adapter, 87*4882a593Smuzhiyun u8 Band 88*4882a593Smuzhiyun ); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* 91*4882a593Smuzhiyun * BB TX Power R/W 92*4882a593Smuzhiyun * */ 93*4882a593Smuzhiyun void PHY_SetTxPowerLevel8812(PADAPTER Adapter, u8 Channel); 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun bool phy_get_txpwr_target_skip_by_rate_8812a(_adapter *adapter, enum MGN_RATE rate); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun u32 phy_get_tx_bb_swing_8812a( 98*4882a593Smuzhiyun PADAPTER Adapter, 99*4882a593Smuzhiyun BAND_TYPE Band, 100*4882a593Smuzhiyun enum rf_path RFPath 101*4882a593Smuzhiyun ); 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun void 104*4882a593Smuzhiyun PHY_SetTxPowerIndex_8812A( 105*4882a593Smuzhiyun PADAPTER Adapter, 106*4882a593Smuzhiyun u32 PowerIndex, 107*4882a593Smuzhiyun enum rf_path RFPath, 108*4882a593Smuzhiyun u8 Rate 109*4882a593Smuzhiyun ); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* 112*4882a593Smuzhiyun * channel switch related funciton 113*4882a593Smuzhiyun * */ 114*4882a593Smuzhiyun void 115*4882a593Smuzhiyun PHY_SetSwChnlBWMode8812( 116*4882a593Smuzhiyun PADAPTER Adapter, 117*4882a593Smuzhiyun u8 channel, 118*4882a593Smuzhiyun enum channel_width Bandwidth, 119*4882a593Smuzhiyun u8 Offset40, 120*4882a593Smuzhiyun u8 Offset80 121*4882a593Smuzhiyun ); 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* 124*4882a593Smuzhiyun * BB/MAC/RF other monitor API 125*4882a593Smuzhiyun * */ 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun void 128*4882a593Smuzhiyun phy_set_rf_path_switch_8812a( 129*4882a593Smuzhiyun struct dm_struct *phydm, 130*4882a593Smuzhiyun bool bMain 131*4882a593Smuzhiyun ); 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /*--------------------------Exported Function prototype---------------------*/ 134*4882a593Smuzhiyun #endif /* __INC_HAL8192CPHYCFG_H */ 135