1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2015 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #define _RTL8822C_OPS_C_
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <drv_types.h> /* basic_types.h, rtw_io.h and etc. */
18*4882a593Smuzhiyun #include <rtw_xmit.h> /* struct xmit_priv */
19*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
20*4882a593Smuzhiyun #include <rtw_sreset.h>
21*4882a593Smuzhiyun #endif /* DBG_CONFIG_ERROR_DETECT */
22*4882a593Smuzhiyun #include <hal_data.h> /* PHAL_DATA_TYPE, GET_HAL_DATA() */
23*4882a593Smuzhiyun #include <hal_com.h> /* dump_chip_info() and etc. */
24*4882a593Smuzhiyun #include "../hal_halmac.h" /* GET_RX_DESC_XXX_8822C() */
25*4882a593Smuzhiyun #include "rtl8822c.h"
26*4882a593Smuzhiyun #include "rtl8822c_hal.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun static const struct hw_port_reg port_cfg[] = {
30*4882a593Smuzhiyun /*port 0*/
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun .net_type = (REG_CR_8822C + 2),
33*4882a593Smuzhiyun .net_type_shift = 0,
34*4882a593Smuzhiyun .macaddr = REG_MACID_8822C,
35*4882a593Smuzhiyun .bssid = REG_BSSID_8822C,
36*4882a593Smuzhiyun .bcn_ctl = REG_BCN_CTRL_8822C,
37*4882a593Smuzhiyun .tsf_rst = REG_DUAL_TSF_RST,
38*4882a593Smuzhiyun .tsf_rst_bit = BIT_TSFTR_RST_8822C,
39*4882a593Smuzhiyun .bcn_space = REG_MBSSID_BCN_SPACE_8822C,
40*4882a593Smuzhiyun .bcn_space_shift = 0,
41*4882a593Smuzhiyun .bcn_space_mask = 0xffff,
42*4882a593Smuzhiyun .ps_aid = REG_BCN_PSR_RPT_8822C,
43*4882a593Smuzhiyun .ta = REG_TRANSMIT_ADDRSS_0_8822C,
44*4882a593Smuzhiyun },
45*4882a593Smuzhiyun /*port 1*/
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun .net_type = (REG_CR_8822C + 2),
48*4882a593Smuzhiyun .net_type_shift = 2,
49*4882a593Smuzhiyun .macaddr = REG_MACID1_8822C,
50*4882a593Smuzhiyun .bssid = REG_BSSID1_8822C,
51*4882a593Smuzhiyun .bcn_ctl = REG_BCN_CTRL_CLINT0_8822C,
52*4882a593Smuzhiyun .tsf_rst = REG_DUAL_TSF_RST,
53*4882a593Smuzhiyun .tsf_rst_bit = BIT_TSFTR_CLI0_RST_8822C,
54*4882a593Smuzhiyun .bcn_space = REG_MBSSID_BCN_SPACE_8822C,
55*4882a593Smuzhiyun .bcn_space_shift = 16,
56*4882a593Smuzhiyun .bcn_space_mask = 0xfff,
57*4882a593Smuzhiyun .ps_aid = REG_BCN_PSR_RPT1_8822C,
58*4882a593Smuzhiyun .ta = REG_TRANSMIT_ADDRSS_1_8822C,
59*4882a593Smuzhiyun },
60*4882a593Smuzhiyun /*port 2*/
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun .net_type = REG_CR_EXT_8822C,
63*4882a593Smuzhiyun .net_type_shift = 0,
64*4882a593Smuzhiyun .macaddr = REG_MACID2_8822C,
65*4882a593Smuzhiyun .bssid = REG_BSSID2_8822C,
66*4882a593Smuzhiyun .bcn_ctl = REG_BCN_CTRL_CLINT1_8822C,
67*4882a593Smuzhiyun .tsf_rst = REG_DUAL_TSF_RST,
68*4882a593Smuzhiyun .tsf_rst_bit = BIT_TSFTR_CLI1_RST_8822C,
69*4882a593Smuzhiyun .bcn_space = REG_MBSSID_BCN_SPACE2_8822C,
70*4882a593Smuzhiyun .bcn_space_shift = 0,
71*4882a593Smuzhiyun .bcn_space_mask = 0xfff,
72*4882a593Smuzhiyun .ps_aid = REG_BCN_PSR_RPT2_8822C,
73*4882a593Smuzhiyun .ta = REG_TRANSMIT_ADDRSS_2_8822C,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun /*port 3*/
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun .net_type = REG_CR_EXT_8822C,
78*4882a593Smuzhiyun .net_type_shift = 2,
79*4882a593Smuzhiyun .macaddr = REG_MACID3_8822C,
80*4882a593Smuzhiyun .bssid = REG_BSSID3_8822C,
81*4882a593Smuzhiyun .bcn_ctl = REG_BCN_CTRL_CLINT2_8822C,
82*4882a593Smuzhiyun .tsf_rst = REG_DUAL_TSF_RST,
83*4882a593Smuzhiyun .tsf_rst_bit = BIT_TSFTR_CLI2_RST_8822C,
84*4882a593Smuzhiyun .bcn_space = REG_MBSSID_BCN_SPACE2_8822C,
85*4882a593Smuzhiyun .bcn_space_shift = 16,
86*4882a593Smuzhiyun .bcn_space_mask = 0xfff,
87*4882a593Smuzhiyun .ps_aid = REG_BCN_PSR_RPT3_8822C,
88*4882a593Smuzhiyun .ta = REG_TRANSMIT_ADDRSS_3_8822C,
89*4882a593Smuzhiyun },
90*4882a593Smuzhiyun /*port 4*/
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun .net_type = REG_CR_EXT_8822C,
93*4882a593Smuzhiyun .net_type_shift = 4,
94*4882a593Smuzhiyun .macaddr = REG_MACID4_8822C,
95*4882a593Smuzhiyun .bssid = REG_BSSID4_8822C,
96*4882a593Smuzhiyun .bcn_ctl = REG_BCN_CTRL_CLINT3_8822C,
97*4882a593Smuzhiyun .tsf_rst = REG_DUAL_TSF_RST,
98*4882a593Smuzhiyun .tsf_rst_bit = BIT_TSFTR_CLI3_RST_8822C,
99*4882a593Smuzhiyun .bcn_space = REG_MBSSID_BCN_SPACE3_8822C,
100*4882a593Smuzhiyun .bcn_space_shift = 0,
101*4882a593Smuzhiyun .bcn_space_mask = 0xfff,
102*4882a593Smuzhiyun .ps_aid = REG_BCN_PSR_RPT4_8822C,
103*4882a593Smuzhiyun .ta = REG_TRANSMIT_ADDRSS_4_8822C,
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
hw_bcn_ctrl_addr(_adapter * adapter,u8 hw_port)107*4882a593Smuzhiyun static u32 hw_bcn_ctrl_addr(_adapter *adapter, u8 hw_port)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
110*4882a593Smuzhiyun u32 addr = 0;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun if (hw_port >= hal_spec->port_num) {
113*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
114*4882a593Smuzhiyun rtw_warn_on(1);
115*4882a593Smuzhiyun goto exit;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun addr = port_cfg[hw_port].bcn_ctl;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun exit:
121*4882a593Smuzhiyun return addr;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun #ifdef CONFIG_CLIENT_PORT_CFG
hw_bcn_ctrl_set(_adapter * adapter,u8 hw_port,u8 bcn_ctl_val)124*4882a593Smuzhiyun static void hw_bcn_ctrl_set(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun u32 bcn_ctl_addr = 0;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun if (hw_port >= MAX_HW_PORT) {
129*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
130*4882a593Smuzhiyun rtw_warn_on(1);
131*4882a593Smuzhiyun return;
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
135*4882a593Smuzhiyun rtw_write8(adapter, bcn_ctl_addr, bcn_ctl_val);
136*4882a593Smuzhiyun }
137*4882a593Smuzhiyun #endif
hw_bcn_ctrl_add(_adapter * adapter,u8 hw_port,u8 bcn_ctl_val)138*4882a593Smuzhiyun static void hw_bcn_ctrl_add(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun u32 bcn_ctl_addr = 0;
141*4882a593Smuzhiyun u8 val8 = 0;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun if (hw_port >= MAX_HW_PORT) {
144*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
145*4882a593Smuzhiyun rtw_warn_on(1);
146*4882a593Smuzhiyun return;
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
150*4882a593Smuzhiyun val8 = rtw_read8(adapter, bcn_ctl_addr) | bcn_ctl_val;
151*4882a593Smuzhiyun rtw_write8(adapter, bcn_ctl_addr, val8);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
hw_bcn_ctrl_clr(_adapter * adapter,u8 hw_port,u8 bcn_ctl_val)154*4882a593Smuzhiyun static void hw_bcn_ctrl_clr(_adapter *adapter, u8 hw_port, u8 bcn_ctl_val)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun u32 bcn_ctl_addr = 0;
157*4882a593Smuzhiyun u8 val8 = 0;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun if (hw_port >= MAX_HW_PORT) {
160*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
161*4882a593Smuzhiyun rtw_warn_on(1);
162*4882a593Smuzhiyun return;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun bcn_ctl_addr = port_cfg[hw_port].bcn_ctl;
166*4882a593Smuzhiyun val8 = rtw_read8(adapter, bcn_ctl_addr);
167*4882a593Smuzhiyun val8 &= ~bcn_ctl_val;
168*4882a593Smuzhiyun rtw_write8(adapter, bcn_ctl_addr, val8);
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
read_chip_version(PADAPTER adapter)171*4882a593Smuzhiyun static void read_chip_version(PADAPTER adapter)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
174*4882a593Smuzhiyun u32 value32;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun value32 = rtw_read32(adapter, REG_SYS_CFG1_8822C);
180*4882a593Smuzhiyun hal->version_id.ICType = CHIP_8822C;
181*4882a593Smuzhiyun hal->version_id.ChipType = ((value32 & BIT_RTL_ID_8822C) ? TEST_CHIP : NORMAL_CHIP);
182*4882a593Smuzhiyun hal->version_id.CUTVersion = BIT_GET_CHIP_VER_8822C(value32);
183*4882a593Smuzhiyun hal->version_id.VendorType = BIT_GET_VENDOR_ID_8822C(value32);
184*4882a593Smuzhiyun hal->version_id.VendorType >>= 2;
185*4882a593Smuzhiyun switch (hal->version_id.VendorType) {
186*4882a593Smuzhiyun case 0:
187*4882a593Smuzhiyun hal->version_id.VendorType = CHIP_VENDOR_TSMC;
188*4882a593Smuzhiyun break;
189*4882a593Smuzhiyun case 1:
190*4882a593Smuzhiyun hal->version_id.VendorType = CHIP_VENDOR_SMIC;
191*4882a593Smuzhiyun break;
192*4882a593Smuzhiyun case 2:
193*4882a593Smuzhiyun hal->version_id.VendorType = CHIP_VENDOR_UMC;
194*4882a593Smuzhiyun break;
195*4882a593Smuzhiyun }
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun hal->version_id.RFType = ((value32 & BIT_RF_TYPE_ID_8822C) ? RF_TYPE_2T2R : RF_TYPE_1T1R);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* refer to sd7 code base*/
200*4882a593Smuzhiyun hal->RegulatorMode = ((value32 & BIT_INTERNAL_EXTERNAL_SWR_8822C) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun value32 = rtw_read32(adapter, REG_SYS_STATUS1_8822C);
203*4882a593Smuzhiyun hal->version_id.ROMVer = BIT_GET_RF_RL_ID_8822C(value32);
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun /* For multi-function consideration. */
206*4882a593Smuzhiyun hal->MultiFunc = RT_MULTI_FUNC_NONE;
207*4882a593Smuzhiyun value32 = rtw_read32(adapter, REG_WL_BT_PWR_CTRL_8822C);
208*4882a593Smuzhiyun hal->MultiFunc |= ((value32 & BIT_WL_FUNC_EN_8822C) ? RT_MULTI_FUNC_WIFI : 0);
209*4882a593Smuzhiyun hal->MultiFunc |= ((value32 & BIT_BT_FUNC_EN_8822C) ? RT_MULTI_FUNC_BT : 0);
210*4882a593Smuzhiyun hal->PolarityCtl = ((value32 & BIT_WL_HWPDN_SL_8822C) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun dump_chip_info(hal->version_id);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun /*
216*4882a593Smuzhiyun * Return:
217*4882a593Smuzhiyun * _TRUE valid ID
218*4882a593Smuzhiyun * _FALSE invalid ID
219*4882a593Smuzhiyun */
Hal_EfuseParseIDCode(PADAPTER adapter,u8 * map)220*4882a593Smuzhiyun static u8 Hal_EfuseParseIDCode(PADAPTER adapter, u8 *map)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun u16 EEPROMId;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun /* Check 0x8129 again for making sure autoload status!! */
226*4882a593Smuzhiyun EEPROMId = le16_to_cpu(*(u16 *)map);
227*4882a593Smuzhiyun RTW_INFO("EEPROM ID = 0x%04x\n", EEPROMId);
228*4882a593Smuzhiyun if (EEPROMId == RTL_EEPROM_ID)
229*4882a593Smuzhiyun return _TRUE;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun RTW_WARN("EEPROM ID is invalid!!\n");
232*4882a593Smuzhiyun return _FALSE;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
Hal_EfuseParseEEPROMVer(PADAPTER adapter,u8 * map,u8 mapvalid)235*4882a593Smuzhiyun static void Hal_EfuseParseEEPROMVer(PADAPTER adapter, u8 *map, u8 mapvalid)
236*4882a593Smuzhiyun {
237*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (_TRUE == mapvalid)
241*4882a593Smuzhiyun hal->EEPROMVersion = map[EEPROM_VERSION_8822C];
242*4882a593Smuzhiyun else
243*4882a593Smuzhiyun hal->EEPROMVersion = 1;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun RTW_INFO("EEPROM Version = %d\n", hal->EEPROMVersion);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
Hal_EfuseParseTxPowerInfo(PADAPTER adapter,u8 * map,u8 mapvalid)248*4882a593Smuzhiyun static int Hal_EfuseParseTxPowerInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
251*4882a593Smuzhiyun u8 tpt_mode = (map[EEPROM_TX_PWR_CALIBRATE_RATE_8822C] & 0xF0) >> 4;
252*4882a593Smuzhiyun int ret = _FAIL;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun if (GetRegPowerTrackingType(adapter) != 64) {
255*4882a593Smuzhiyun tpt_mode = GetRegPowerTrackingType(adapter);
256*4882a593Smuzhiyun RTW_INFO("%s force tpt_mode=%u\n", __func__, tpt_mode);
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun #ifdef CONFIG_TXPWR_PG_WITH_PWR_IDX
260*4882a593Smuzhiyun if (tpt_mode <= 3) { /* 0~3: thermal */
261*4882a593Smuzhiyun hal->txpwr_pg_mode = TXPWR_PG_WITH_PWR_IDX;
262*4882a593Smuzhiyun goto parse_tpt_mode_done;
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun #endif
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun #ifdef CONFIG_TXPWR_PG_WITH_TSSI_OFFSET
267*4882a593Smuzhiyun if (tpt_mode >= 4 && tpt_mode <= 7) { /* 4~7: TSSI */
268*4882a593Smuzhiyun hal->txpwr_pg_mode = TXPWR_PG_WITH_TSSI_OFFSET;
269*4882a593Smuzhiyun goto parse_tpt_mode_done;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun #endif
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun RTW_ERR("%s unknown tpt_mode=%u\n", __func__, tpt_mode);
274*4882a593Smuzhiyun goto exit;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun parse_tpt_mode_done:
277*4882a593Smuzhiyun RTW_INFO("%s tpt_mode=%u, PG with %s\n", __func__
278*4882a593Smuzhiyun , tpt_mode, txpwr_pg_mode_str(hal->txpwr_pg_mode));
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF))
281*4882a593Smuzhiyun hal->EEPROMRegulatory = map[EEPROM_RF_BOARD_OPTION_8822C] & 0x3; /* bit0~1 */
282*4882a593Smuzhiyun else
283*4882a593Smuzhiyun hal->EEPROMRegulatory = EEPROM_DEFAULT_BOARD_OPTION & 0x3; /* bit0~1 */
284*4882a593Smuzhiyun RTW_INFO("EEPROM Regulatory=0x%02x\n", hal->EEPROMRegulatory);
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun ret = _SUCCESS;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun exit:
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun
Hal_EfuseParseBoardType(PADAPTER adapter,u8 * map,u8 mapvalid)292*4882a593Smuzhiyun static void Hal_EfuseParseBoardType(PADAPTER adapter, u8 *map, u8 mapvalid)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF))
298*4882a593Smuzhiyun hal->InterfaceSel = (map[EEPROM_RF_BOARD_OPTION_8822C] & 0xE0) >> 5;
299*4882a593Smuzhiyun else
300*4882a593Smuzhiyun hal->InterfaceSel = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun RTW_INFO("EEPROM Board Type=0x%02x\n", hal->InterfaceSel);
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (mapvalid) {
305*4882a593Smuzhiyun if (map[EEPROM_RF_BOARD_OPTION_8822C] & BIT2) {
306*4882a593Smuzhiyun /* de-featured to 1 Tx/stream */
307*4882a593Smuzhiyun hal->eeprom_max_tx_cnt = 1;
308*4882a593Smuzhiyun RTW_INFO("EEPROM 0xC1[2]=1, de-featured to 1 Tx/stream\n");
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun if (map[EEPROM_RF_BOARD_OPTION_8822C] & BIT3) {
311*4882a593Smuzhiyun /* de-featured to 1 Rx/stream */
312*4882a593Smuzhiyun /* TODO, how and necessary? */
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun }
316*4882a593Smuzhiyun
Hal_EfuseParseBTCoexistInfo(PADAPTER adapter,u8 * map,u8 mapvalid)317*4882a593Smuzhiyun static void Hal_EfuseParseBTCoexistInfo(PADAPTER adapter, u8 *map, u8 mapvalid)
318*4882a593Smuzhiyun {
319*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
320*4882a593Smuzhiyun u8 setting;
321*4882a593Smuzhiyun u32 tmpu4;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun if ((_TRUE == mapvalid) && (map[EEPROM_RF_BOARD_OPTION_8822C] != 0xFF)) {
324*4882a593Smuzhiyun /* 0xc1[7:5] = 0x01 */
325*4882a593Smuzhiyun if (((map[EEPROM_RF_BOARD_OPTION_8822C] & 0xe0) >> 5) == 0x01)
326*4882a593Smuzhiyun hal->EEPROMBluetoothCoexist = _TRUE;
327*4882a593Smuzhiyun else
328*4882a593Smuzhiyun hal->EEPROMBluetoothCoexist = _FALSE;
329*4882a593Smuzhiyun } else
330*4882a593Smuzhiyun hal->EEPROMBluetoothCoexist = _FALSE;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun hal->EEPROMBluetoothType = BT_RTL8822C;
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun setting = map[EEPROM_RF_BT_SETTING_8822C];
335*4882a593Smuzhiyun if ((_TRUE == mapvalid) && (setting != 0xFF)) {
336*4882a593Smuzhiyun hal->EEPROMBluetoothAntNum = setting & BIT(0);
337*4882a593Smuzhiyun /*
338*4882a593Smuzhiyun * EFUSE_0xC3[6] == 0, S1(Main)-RF_PATH_A;
339*4882a593Smuzhiyun * EFUSE_0xC3[6] == 1, S0(Aux)-RF_PATH_B
340*4882a593Smuzhiyun */
341*4882a593Smuzhiyun hal->ant_path = (setting & BIT(6)) ? RF_PATH_B : RF_PATH_A;
342*4882a593Smuzhiyun } else {
343*4882a593Smuzhiyun hal->EEPROMBluetoothAntNum = Ant_x2;
344*4882a593Smuzhiyun hal->ant_path = RF_PATH_A;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun RTW_INFO("EEPROM %s BT-coex, ant_num=%d\n",
348*4882a593Smuzhiyun hal->EEPROMBluetoothCoexist == _TRUE ? "Enable" : "Disable",
349*4882a593Smuzhiyun hal->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
Hal_EfuseParseChnlPlan(PADAPTER adapter,u8 * map,u8 autoloadfail)352*4882a593Smuzhiyun static void Hal_EfuseParseChnlPlan(PADAPTER adapter, u8 *map, u8 autoloadfail)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun hal_com_config_channel_plan(
355*4882a593Smuzhiyun adapter,
356*4882a593Smuzhiyun map ? &map[EEPROM_COUNTRY_CODE_8822C] : NULL,
357*4882a593Smuzhiyun map ? map[EEPROM_ChannelPlan_8822C] : 0xFF,
358*4882a593Smuzhiyun RTW_CHPLAN_6G_NULL,
359*4882a593Smuzhiyun autoloadfail
360*4882a593Smuzhiyun );
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
364*4882a593Smuzhiyun #define GET_XCAP_VALUE_B9_8822C(x) (x & 0x7F)
365*4882a593Smuzhiyun #define GET_XCAP_VALUE_110_8822C(x) (x & 0x7F)
366*4882a593Smuzhiyun #define GET_XCAP_VALUE_111_8822C(x) ((x & 0x7F00) >> 8)
367*4882a593Smuzhiyun #define EFUSE_XCAP_VALID_CHK_B9_8822C(x) \
368*4882a593Smuzhiyun (!(GET_XCAP_VALUE_B9_8822C(x) == 0x7F))
369*4882a593Smuzhiyun #define EFUSE_XCAP_VALID_CHK_110_8822C(x) \
370*4882a593Smuzhiyun (!((GET_XCAP_VALUE_110_8822C(x) == EEPROM_Default_CrystalCap_110_8822C) || (GET_XCAP_VALUE_110_8822C(x) == 0x7F)))
371*4882a593Smuzhiyun #define EFUSE_XCAP_VALID_CHK_111_8822C(x) \
372*4882a593Smuzhiyun (!((GET_XCAP_VALUE_111_8822C(x) == EEPROM_Default_CrystalCap_111_8822C) || (GET_XCAP_VALUE_111_8822C(x) == 0x7F)))
hal_efuse_search_xtal_cap(PADAPTER adapter,u8 h_xcap_b9,u16 f_xcap_110_111,u8 f_xcap_b9)373*4882a593Smuzhiyun static s16 hal_efuse_search_xtal_cap(PADAPTER adapter, u8 h_xcap_b9, u16 f_xcap_110_111, u8 f_xcap_b9)
374*4882a593Smuzhiyun {
375*4882a593Smuzhiyun enum {
376*4882a593Smuzhiyun XCAP_SRC_H_EFUSE_B9_8822C = 0,
377*4882a593Smuzhiyun XCAP_SRC_F_EFUSE_110_8822C,
378*4882a593Smuzhiyun XCAP_SRC_F_EFUSE_B9_8822C,
379*4882a593Smuzhiyun XCAP_SRC_8822C_MAX
380*4882a593Smuzhiyun };
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun const char *const xcap_src_8822c_str[XCAP_SRC_8822C_MAX] = {
383*4882a593Smuzhiyun "XCAP_SRC_H_EFUSE_B9",
384*4882a593Smuzhiyun "XCAP_SRC_F_EFUSE_110",
385*4882a593Smuzhiyun "XCAP_SRC_F_EFUSE_B9"
386*4882a593Smuzhiyun };
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun /* this declaration also controls the priority while searching xcap value from the candidates,
389*4882a593Smuzhiyun the prior element in the array implies the higher priority, fill -1 to bypass the element */
390*4882a593Smuzhiyun s8 xcap_src_8822c[XCAP_SRC_8822C_MAX] =
391*4882a593Smuzhiyun {XCAP_SRC_F_EFUSE_B9_8822C, XCAP_SRC_F_EFUSE_110_8822C, XCAP_SRC_H_EFUSE_B9_8822C};
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun int i = 0;
394*4882a593Smuzhiyun s8 xcap_found = -1;
395*4882a593Smuzhiyun s16 xcap_value = -1;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun /* search for the valid xcap value from candidates */
398*4882a593Smuzhiyun for (i = 0; i < XCAP_SRC_8822C_MAX; i++) {
399*4882a593Smuzhiyun switch (xcap_src_8822c[i]) {
400*4882a593Smuzhiyun case XCAP_SRC_H_EFUSE_B9_8822C:
401*4882a593Smuzhiyun if (EFUSE_XCAP_VALID_CHK_B9_8822C(h_xcap_b9)) {
402*4882a593Smuzhiyun xcap_value = ((GET_XCAP_VALUE_B9_8822C(h_xcap_b9) << 8) | GET_XCAP_VALUE_B9_8822C(h_xcap_b9));
403*4882a593Smuzhiyun xcap_found = XCAP_SRC_H_EFUSE_B9_8822C;
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun break;
406*4882a593Smuzhiyun case XCAP_SRC_F_EFUSE_110_8822C:
407*4882a593Smuzhiyun if ((EFUSE_XCAP_VALID_CHK_110_8822C(f_xcap_110_111 )) && (EFUSE_XCAP_VALID_CHK_111_8822C(f_xcap_110_111 ))) {
408*4882a593Smuzhiyun xcap_value = (f_xcap_110_111 & 0x7F7F);
409*4882a593Smuzhiyun xcap_found = XCAP_SRC_F_EFUSE_110_8822C;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun break;
412*4882a593Smuzhiyun case XCAP_SRC_F_EFUSE_B9_8822C:
413*4882a593Smuzhiyun if (EFUSE_XCAP_VALID_CHK_B9_8822C(f_xcap_b9)) {
414*4882a593Smuzhiyun xcap_value = ((GET_XCAP_VALUE_B9_8822C(f_xcap_b9) << 8) | GET_XCAP_VALUE_B9_8822C(f_xcap_b9));
415*4882a593Smuzhiyun xcap_found = XCAP_SRC_F_EFUSE_B9_8822C;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun break;
418*4882a593Smuzhiyun case -1:
419*4882a593Smuzhiyun break;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if (xcap_found >= 0)
423*4882a593Smuzhiyun break;
424*4882a593Smuzhiyun }
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun if (xcap_found == -1)
427*4882a593Smuzhiyun RTW_INFO("valid crystall_cap value is not found in all sources!\n");
428*4882a593Smuzhiyun else
429*4882a593Smuzhiyun RTW_INFO("valid crystal_cap value 0x%04X is found in %s!\n", xcap_value, xcap_src_8822c_str[xcap_found]);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun return xcap_value;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
hal_efuse_parse_xtal_cap_new(PADAPTER adapter,u16 h_xcap_110_111,u8 h_xcap_b9,u16 f_xcap_110_111,u8 f_xcap_b9,u8 mapvalid)434*4882a593Smuzhiyun static void hal_efuse_parse_xtal_cap_new(PADAPTER adapter, u16 h_xcap_110_111, u8 h_xcap_b9,
435*4882a593Smuzhiyun u16 f_xcap_110_111, u8 f_xcap_b9, u8 mapvalid)
436*4882a593Smuzhiyun {
437*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
438*4882a593Smuzhiyun s16 xcap_value = -1;
439*4882a593Smuzhiyun u16 xcap_value_to_h_efuse = 0;
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun if (mapvalid == _FALSE) {
442*4882a593Smuzhiyun hal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;
443*4882a593Smuzhiyun goto exit;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
446*4882a593Smuzhiyun if (adapter->registrypriv.rtw_8822c_xcap_overwrite == 1) {
447*4882a593Smuzhiyun xcap_value = hal_efuse_search_xtal_cap(adapter, h_xcap_b9, f_xcap_110_111, f_xcap_b9);
448*4882a593Smuzhiyun if (xcap_value != -1) {
449*4882a593Smuzhiyun if (xcap_value != (h_xcap_110_111 & 0x7F7F)) {
450*4882a593Smuzhiyun xcap_value_to_h_efuse = ((h_xcap_110_111 & 0x8080) | xcap_value);
451*4882a593Smuzhiyun rtw_efuse_map_write(adapter, EEPROM_XTAL_110_8822C, 2, (u8*)&xcap_value_to_h_efuse);
452*4882a593Smuzhiyun RTW_INFO("update crystal_cap = 0x%02X into hw efuse!\n", xcap_value);
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun hal->crystal_cap = GET_XCAP_VALUE_110_8822C(xcap_value);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun else {
458*4882a593Smuzhiyun if ((EFUSE_XCAP_VALID_CHK_110_8822C(h_xcap_110_111)) && (EFUSE_XCAP_VALID_CHK_111_8822C(h_xcap_110_111)))
459*4882a593Smuzhiyun hal->crystal_cap = GET_XCAP_VALUE_110_8822C(h_xcap_110_111);
460*4882a593Smuzhiyun else
461*4882a593Smuzhiyun hal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun else {
465*4882a593Smuzhiyun if ((EFUSE_XCAP_VALID_CHK_110_8822C(h_xcap_110_111)) && (EFUSE_XCAP_VALID_CHK_111_8822C(h_xcap_110_111)))
466*4882a593Smuzhiyun hal->crystal_cap = GET_XCAP_VALUE_110_8822C(h_xcap_110_111);
467*4882a593Smuzhiyun else {
468*4882a593Smuzhiyun xcap_value = hal_efuse_search_xtal_cap(adapter, h_xcap_b9, f_xcap_110_111, f_xcap_b9);
469*4882a593Smuzhiyun if (xcap_value != -1) {
470*4882a593Smuzhiyun xcap_value_to_h_efuse = ((h_xcap_110_111 & 0x8080) | xcap_value);
471*4882a593Smuzhiyun rtw_efuse_map_write(adapter, EEPROM_XTAL_110_8822C, 2, (u8*)&xcap_value_to_h_efuse);
472*4882a593Smuzhiyun RTW_INFO("update crystal_cap = 0x%02X into hw efuse!\n", xcap_value);
473*4882a593Smuzhiyun hal->crystal_cap = GET_XCAP_VALUE_110_8822C(xcap_value);
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun else
476*4882a593Smuzhiyun hal->crystal_cap = EEPROM_Default_CrystalCap_110_8822C;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun }
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun exit:
481*4882a593Smuzhiyun RTW_INFO("EEPROM crystal_cap=0x%02x\n", hal->crystal_cap);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun #endif
Hal_EfuseParseXtal(PADAPTER adapter,u8 * map,u8 mapvalid)485*4882a593Smuzhiyun static void Hal_EfuseParseXtal(PADAPTER adapter, u8 *map, u8 mapvalid)
486*4882a593Smuzhiyun {
487*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if ((_TRUE == mapvalid) && map[EEPROM_XTAL_B9_8822C] != 0xFF)
491*4882a593Smuzhiyun hal->crystal_cap = map[EEPROM_XTAL_B9_8822C];
492*4882a593Smuzhiyun else
493*4882a593Smuzhiyun hal->crystal_cap = EEPROM_Default_CrystalCap_B9_8822C;
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun RTW_INFO("EEPROM crystal_cap=0x%02x\n", hal->crystal_cap);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
Hal_EfuseParseThermalMeter(PADAPTER adapter,u8 * map,u8 mapvalid)498*4882a593Smuzhiyun static void Hal_EfuseParseThermalMeter(PADAPTER adapter, u8 *map, u8 mapvalid)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun
503*4882a593Smuzhiyun /* ThermalMeter from EEPROM */
504*4882a593Smuzhiyun if ((_TRUE == mapvalid) && (map[EEPROM_THERMAL_METER_A_8822C] != 0xFF) \
505*4882a593Smuzhiyun && (map[EEPROM_THERMAL_METER_B_8822C] != 0xFF)) {
506*4882a593Smuzhiyun /* suggested by James@RF */
507*4882a593Smuzhiyun u8 eeprom_thermal_meter_a = map[EEPROM_THERMAL_METER_A_8822C];
508*4882a593Smuzhiyun u8 eeprom_thermal_meter_b = map[EEPROM_THERMAL_METER_B_8822C];
509*4882a593Smuzhiyun hal->eeprom_thermal_meter = (eeprom_thermal_meter_a + eeprom_thermal_meter_b)/2;
510*4882a593Smuzhiyun } else {
511*4882a593Smuzhiyun hal->eeprom_thermal_meter = EEPROM_Default_ThermalMeter;
512*4882a593Smuzhiyun hal->odmpriv.rf_calibrate_info.is_apk_thermal_meter_ignore = _TRUE;
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun RTW_INFO("EEPROM ThermalMeter=0x%02x\n", hal->eeprom_thermal_meter);
516*4882a593Smuzhiyun }
517*4882a593Smuzhiyun
Hal_EfuseParsePathSelection(PADAPTER adapter,u8 * map,u8 mapvalid)518*4882a593Smuzhiyun static void Hal_EfuseParsePathSelection(PADAPTER adapter, u8 *map, u8 mapvalid)
519*4882a593Smuzhiyun {
520*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
521*4882a593Smuzhiyun u8 trx_path_bmp = map[EEPROM_RF_ANTENNA_OPT_8822C];
522*4882a593Smuzhiyun
523*4882a593Smuzhiyun if (!mapvalid)
524*4882a593Smuzhiyun return;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun switch (trx_path_bmp) {
527*4882a593Smuzhiyun case 0x33: /* 2T2R - TX:AB, RX:AB */
528*4882a593Smuzhiyun case 0x13: /* 1T2R - TX:A, RX:AB */
529*4882a593Smuzhiyun case 0x23: /* 1T2R - TX:B, RX:AB */
530*4882a593Smuzhiyun case 0x11: /* 1T1R - TX:A, RX:A */
531*4882a593Smuzhiyun case 0x22: /* 1T1R - TX:B, RX:B */
532*4882a593Smuzhiyun hal->eeprom_trx_path_bmp = trx_path_bmp;
533*4882a593Smuzhiyun RTW_INFO("EEPROM efuse[0x%x]=0x%02x is valid\n"
534*4882a593Smuzhiyun , EEPROM_RF_ANTENNA_OPT_8822C, trx_path_bmp);
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun default:
537*4882a593Smuzhiyun RTW_INFO("EEPROM efuse[0x%x]=0x%02x is unknown type\n"
538*4882a593Smuzhiyun , EEPROM_RF_ANTENNA_OPT_8822C, trx_path_bmp);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun
Hal_EfuseParseCustomerID(PADAPTER adapter,u8 * map,u8 mapvalid)542*4882a593Smuzhiyun static void Hal_EfuseParseCustomerID(PADAPTER adapter, u8 *map, u8 mapvalid)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun if (_TRUE == mapvalid)
548*4882a593Smuzhiyun hal->EEPROMCustomerID = map[EEPROM_CustomID_8822C];
549*4882a593Smuzhiyun else
550*4882a593Smuzhiyun hal->EEPROMCustomerID = 0;
551*4882a593Smuzhiyun RTW_INFO("EEPROM Customer ID=0x%02x\n", hal->EEPROMCustomerID);
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun
Hal_DetectWoWMode(PADAPTER adapter)554*4882a593Smuzhiyun static void Hal_DetectWoWMode(PADAPTER adapter)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
557*4882a593Smuzhiyun adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _TRUE;
558*4882a593Smuzhiyun #else /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
559*4882a593Smuzhiyun adapter_to_pwrctl(adapter)->bSupportRemoteWakeup = _FALSE;
560*4882a593Smuzhiyun #endif /* !(CONFIG_WOWLAN || CONFIG_AP_WOWLAN) */
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun RTW_INFO("EEPROM SupportRemoteWakeup=%d\n", adapter_to_pwrctl(adapter)->bSupportRemoteWakeup);
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun
hal_ReadPAType(PADAPTER adapter,u8 * map,u8 mapvalid)565*4882a593Smuzhiyun static void hal_ReadPAType(PADAPTER adapter, u8 *map, u8 mapvalid)
566*4882a593Smuzhiyun {
567*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun if (mapvalid) {
570*4882a593Smuzhiyun /* AUTO */
571*4882a593Smuzhiyun if (GetRegAmplifierType2G(adapter) == 0) {
572*4882a593Smuzhiyun hal->PAType_2G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822C]);
573*4882a593Smuzhiyun hal->LNAType_2G = ReadLE1Byte(&map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C]);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun if (hal->PAType_2G == 0xFF)
576*4882a593Smuzhiyun hal->PAType_2G = 0;
577*4882a593Smuzhiyun
578*4882a593Smuzhiyun if (hal->LNAType_2G == 0xFF)
579*4882a593Smuzhiyun hal->LNAType_2G = 0;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun hal->ExternalPA_2G = (hal->PAType_2G & BIT4) ? 1 : 0;
582*4882a593Smuzhiyun hal->ExternalLNA_2G = (hal->LNAType_2G & BIT3) ? 1 : 0;
583*4882a593Smuzhiyun } else {
584*4882a593Smuzhiyun hal->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
585*4882a593Smuzhiyun hal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun /* AUTO */
589*4882a593Smuzhiyun if (GetRegAmplifierType5G(adapter) == 0) {
590*4882a593Smuzhiyun hal->PAType_5G = ReadLE1Byte(&map[EEPROM_2G_5G_PA_TYPE_8822C]);
591*4882a593Smuzhiyun hal->LNAType_5G = ReadLE1Byte(&map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C]);
592*4882a593Smuzhiyun if (hal->PAType_5G == 0xFF)
593*4882a593Smuzhiyun hal->PAType_5G = 0;
594*4882a593Smuzhiyun if (hal->LNAType_5G == 0xFF)
595*4882a593Smuzhiyun hal->LNAType_5G = 0;
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun hal->external_pa_5g = (hal->PAType_5G & BIT0) ? 1 : 0;
598*4882a593Smuzhiyun hal->external_lna_5g = (hal->LNAType_5G & BIT3) ? 1 : 0;
599*4882a593Smuzhiyun } else {
600*4882a593Smuzhiyun hal->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
601*4882a593Smuzhiyun hal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
602*4882a593Smuzhiyun }
603*4882a593Smuzhiyun } else {
604*4882a593Smuzhiyun hal->ExternalPA_2G = EEPROM_Default_PAType;
605*4882a593Smuzhiyun hal->external_pa_5g = 0xFF;
606*4882a593Smuzhiyun hal->ExternalLNA_2G = EEPROM_Default_LNAType;
607*4882a593Smuzhiyun hal->external_lna_5g = 0xFF;
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun /* AUTO */
610*4882a593Smuzhiyun if (GetRegAmplifierType2G(adapter) == 0) {
611*4882a593Smuzhiyun hal->ExternalPA_2G = 0;
612*4882a593Smuzhiyun hal->ExternalLNA_2G = 0;
613*4882a593Smuzhiyun } else {
614*4882a593Smuzhiyun hal->ExternalPA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_PA) ? 1 : 0;
615*4882a593Smuzhiyun hal->ExternalLNA_2G = (GetRegAmplifierType2G(adapter) & ODM_BOARD_EXT_LNA) ? 1 : 0;
616*4882a593Smuzhiyun }
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun /* AUTO */
619*4882a593Smuzhiyun if (GetRegAmplifierType5G(adapter) == 0) {
620*4882a593Smuzhiyun hal->external_pa_5g = 0;
621*4882a593Smuzhiyun hal->external_lna_5g = 0;
622*4882a593Smuzhiyun } else {
623*4882a593Smuzhiyun hal->external_pa_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_PA_5G) ? 1 : 0;
624*4882a593Smuzhiyun hal->external_lna_5g = (GetRegAmplifierType5G(adapter) & ODM_BOARD_EXT_LNA_5G) ? 1 : 0;
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun }
627*4882a593Smuzhiyun
628*4882a593Smuzhiyun RTW_INFO("EEPROM PAType_2G is 0x%x, ExternalPA_2G = %d\n", hal->PAType_2G, hal->ExternalPA_2G);
629*4882a593Smuzhiyun RTW_INFO("EEPROM PAType_5G is 0x%x, external_pa_5g = %d\n", hal->PAType_5G, hal->external_pa_5g);
630*4882a593Smuzhiyun RTW_INFO("EEPROM LNAType_2G is 0x%x, ExternalLNA_2G = %d\n", hal->LNAType_2G, hal->ExternalLNA_2G);
631*4882a593Smuzhiyun RTW_INFO("EEPROM LNAType_5G is 0x%x, external_lna_5g = %d\n", hal->LNAType_5G, hal->external_lna_5g);
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun
Hal_ReadAmplifierType(PADAPTER adapter,u8 * map,u8 mapvalid)634*4882a593Smuzhiyun static void Hal_ReadAmplifierType(PADAPTER adapter, u8 *map, u8 mapvalid)
635*4882a593Smuzhiyun {
636*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
637*4882a593Smuzhiyun u8 extTypePA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT2) >> 2;
638*4882a593Smuzhiyun u8 extTypePA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT6) >> 6;
639*4882a593Smuzhiyun u8 extTypePA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT2) >> 2;
640*4882a593Smuzhiyun u8 extTypePA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & BIT6) >> 6;
641*4882a593Smuzhiyun u8 extTypeLNA_2G_A = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT1 | BIT0)) >> 0;
642*4882a593Smuzhiyun u8 extTypeLNA_2G_B = (map[EEPROM_2G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4;
643*4882a593Smuzhiyun u8 extTypeLNA_5G_A = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT1 | BIT0)) >> 0;
644*4882a593Smuzhiyun u8 extTypeLNA_5G_B = (map[EEPROM_5G_LNA_TYPE_GAIN_SEL_AB_8822C] & (BIT5 | BIT4)) >> 4;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun hal_ReadPAType(adapter, map, mapvalid);
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /* [2.4G] Path A and B are both extPA */
649*4882a593Smuzhiyun if ((hal->PAType_2G & (BIT5 | BIT4)) == (BIT5 | BIT4))
650*4882a593Smuzhiyun hal->TypeGPA = extTypePA_2G_B << 2 | extTypePA_2G_A;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun /* [5G] Path A and B are both extPA */
653*4882a593Smuzhiyun if ((hal->PAType_5G & (BIT1 | BIT0)) == (BIT1 | BIT0))
654*4882a593Smuzhiyun hal->TypeAPA = extTypePA_5G_B << 2 | extTypePA_5G_A;
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun /* [2.4G] Path A and B are both extLNA */
657*4882a593Smuzhiyun if ((hal->LNAType_2G & (BIT7 | BIT3)) == (BIT7 | BIT3))
658*4882a593Smuzhiyun hal->TypeGLNA = extTypeLNA_2G_B << 2 | extTypeLNA_2G_A;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun /* [5G] Path A and B are both extLNA */
661*4882a593Smuzhiyun if ((hal->LNAType_5G & (BIT7 | BIT3)) == (BIT7 | BIT3))
662*4882a593Smuzhiyun hal->TypeALNA = extTypeLNA_5G_B << 2 | extTypeLNA_5G_A;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun RTW_INFO("EEPROM TypeGPA = 0x%X\n", hal->TypeGPA);
665*4882a593Smuzhiyun RTW_INFO("EEPROM TypeAPA = 0x%X\n", hal->TypeAPA);
666*4882a593Smuzhiyun RTW_INFO("EEPROM TypeGLNA = 0x%X\n", hal->TypeGLNA);
667*4882a593Smuzhiyun RTW_INFO("EEPROM TypeALNA = 0x%X\n", hal->TypeALNA);
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun
Hal_ReadRFEType(PADAPTER adapter,u8 * map,u8 mapvalid)670*4882a593Smuzhiyun static u8 Hal_ReadRFEType(PADAPTER adapter, u8 *map, u8 mapvalid)
671*4882a593Smuzhiyun {
672*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /* check registry value */
676*4882a593Smuzhiyun if (GetRegRFEType(adapter) != CONFIG_RTW_RFE_TYPE) {
677*4882a593Smuzhiyun hal->rfe_type = GetRegRFEType(adapter);
678*4882a593Smuzhiyun goto exit;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (mapvalid) {
682*4882a593Smuzhiyun /* check efuse map */
683*4882a593Smuzhiyun hal->rfe_type = ReadLE1Byte(&map[EEPROM_RFE_OPTION_8822C]);
684*4882a593Smuzhiyun if (0xFF != hal->rfe_type)
685*4882a593Smuzhiyun goto exit;
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
688*4882a593Smuzhiyun /* error handle */
689*4882a593Smuzhiyun hal->rfe_type = 0;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun /* If ignore incorrect rfe_type may cause card drop. */
692*4882a593Smuzhiyun /* it's DIFFICULT do debug especially on COB project */
693*4882a593Smuzhiyun RTW_ERR("\n\nEmpty EFUSE with unknown REF type!!\n\n");
694*4882a593Smuzhiyun RTW_ERR("please program efuse or specify correct RFE type.\n");
695*4882a593Smuzhiyun RTW_ERR("cmd: insmod rtl8822cx.ko rtw_RFE_type=<rfe_type>\n\n");
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun return _FAIL;
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun exit:
700*4882a593Smuzhiyun RTW_INFO("EEPROM rfe_type=0x%x\n", hal->rfe_type);
701*4882a593Smuzhiyun return _SUCCESS;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun
Hal_EfuseParsePackageType(PADAPTER adapter,u8 * map,u8 mapvalid)704*4882a593Smuzhiyun static void Hal_EfuseParsePackageType(PADAPTER adapter, u8 *map, u8 mapvalid)
705*4882a593Smuzhiyun {
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun #if 0
709*4882a593Smuzhiyun static void Hal_EfuseParsePABias(PADAPTER adapter)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun struct hal_com_data *hal;
712*4882a593Smuzhiyun u8 data[2] = {0xFF, 0xFF};
713*4882a593Smuzhiyun u8 ret;
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun ret = rtw_efuse_access(adapter, 0, 0x3D7, 2, data);
717*4882a593Smuzhiyun if (_FAIL == ret) {
718*4882a593Smuzhiyun RTW_ERR("%s: Fail to read PA Bias from eFuse!\n", __FUNCTION__);
719*4882a593Smuzhiyun return;
720*4882a593Smuzhiyun }
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
723*4882a593Smuzhiyun hal->efuse0x3d7 = data[0]; /* efuse[0x3D7] */
724*4882a593Smuzhiyun hal->efuse0x3d8 = data[1]; /* efuse[0x3D8] */
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun RTW_INFO("EEPROM efuse[0x3D7]=0x%x\n", hal->efuse0x3d7);
727*4882a593Smuzhiyun RTW_INFO("EEPROM efuse[0x3D8]=0x%x\n", hal->efuse0x3d8);
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun #endif
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
Hal_ReadUsbModeSwitch(PADAPTER adapter,u8 * map,u8 mapvalid)732*4882a593Smuzhiyun static void Hal_ReadUsbModeSwitch(PADAPTER adapter, u8 *map, u8 mapvalid)
733*4882a593Smuzhiyun {
734*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun if (_TRUE == mapvalid)
737*4882a593Smuzhiyun /* check efuse 0x06 bit7 */
738*4882a593Smuzhiyun hal->EEPROMUsbSwitch = (map[EEPROM_USB_MODE_8822CU] & BIT7) >> 7;
739*4882a593Smuzhiyun else
740*4882a593Smuzhiyun hal->EEPROMUsbSwitch = _FALSE;
741*4882a593Smuzhiyun
742*4882a593Smuzhiyun RTW_INFO("EEPROM USB Switch=%d\n", hal->EEPROMUsbSwitch);
743*4882a593Smuzhiyun }
744*4882a593Smuzhiyun
hal_read_usb_pid_vid(PADAPTER adapter,u8 * map,u8 mapvalid)745*4882a593Smuzhiyun static void hal_read_usb_pid_vid(PADAPTER adapter, u8 *map, u8 mapvalid)
746*4882a593Smuzhiyun {
747*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
748*4882a593Smuzhiyun
749*4882a593Smuzhiyun if (_TRUE == mapvalid) {
750*4882a593Smuzhiyun /* VID, PID */
751*4882a593Smuzhiyun hal->EEPROMVID = ReadLE2Byte(&map[EEPROM_VID_8822CU]);
752*4882a593Smuzhiyun hal->EEPROMPID = ReadLE2Byte(&map[EEPROM_PID_8822CU]);
753*4882a593Smuzhiyun } else {
754*4882a593Smuzhiyun hal->EEPROMVID = EEPROM_Default_VID;
755*4882a593Smuzhiyun hal->EEPROMPID = EEPROM_Default_PID;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun RTW_INFO("EEPROM VID = 0x%04X, PID = 0x%04X\n", hal->EEPROMVID, hal->EEPROMPID);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
761*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun /*
764*4882a593Smuzhiyun * Description:
765*4882a593Smuzhiyun * Collect all information from efuse or files.
766*4882a593Smuzhiyun * This function will do
767*4882a593Smuzhiyun * 1. Read registers to check hardware efuse available or not
768*4882a593Smuzhiyun * 2. Read Efuse/EEPROM
769*4882a593Smuzhiyun * 3. Read file if necessary
770*4882a593Smuzhiyun * 4. Parsing Efuse data
771*4882a593Smuzhiyun */
rtl8822c_read_efuse(PADAPTER adapter)772*4882a593Smuzhiyun u8 rtl8822c_read_efuse(PADAPTER adapter)
773*4882a593Smuzhiyun {
774*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
775*4882a593Smuzhiyun u8 val8;
776*4882a593Smuzhiyun u8 *efuse_map = NULL;
777*4882a593Smuzhiyun u8 valid;
778*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
779*4882a593Smuzhiyun u8 h_efuse_xcap_b9 = 0xFF;
780*4882a593Smuzhiyun u16 h_efuse_xcap_110_111 = 0xFFFF;
781*4882a593Smuzhiyun u8 f_efuse_xcap_b9 = 0xFF;
782*4882a593Smuzhiyun u16 f_efuse_xcap_110_111 = 0xFFFF;
783*4882a593Smuzhiyun #endif
784*4882a593Smuzhiyun u8 ret = _FAIL;
785*4882a593Smuzhiyun
786*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
787*4882a593Smuzhiyun efuse_map = hal->efuse_eeprom_data;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun /* 1. Read registers to check hardware eFuse available or not */
790*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_SYS_EEPROM_CTRL_8822C);
791*4882a593Smuzhiyun hal->EepromOrEfuse = (val8 & BIT_EERPOMSEL_8822C) ? _TRUE : _FALSE;
792*4882a593Smuzhiyun hal->bautoload_fail_flag = (val8 & BIT_AUTOLOAD_SUS_8822C) ? _FALSE : _TRUE;
793*4882a593Smuzhiyun if (hal->bautoload_fail_flag == _TRUE)
794*4882a593Smuzhiyun RTW_ERR("%s: HW %s AUTO LOAD FAIL!!\n", __func__, hal->EepromOrEfuse ? "EEPROM" : "EFUSE");
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun /*
797*4882a593Smuzhiyun * In 8822C, bautoload_fail_flag is used to present eFuse map is valid
798*4882a593Smuzhiyun * or not, no matter the map comes from hardware or files.
799*4882a593Smuzhiyun */
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun /* 2. Read eFuse */
802*4882a593Smuzhiyun EFUSE_ShadowMapUpdate(adapter, EFUSE_WIFI, 0);
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
805*4882a593Smuzhiyun h_efuse_xcap_b9 = efuse_map[EEPROM_XTAL_B9_8822C];
806*4882a593Smuzhiyun h_efuse_xcap_110_111 = ((efuse_map[EEPROM_XTAL_111_8822C] << 8) | efuse_map[EEPROM_XTAL_110_8822C]);
807*4882a593Smuzhiyun #endif
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun /* 3. Read Efuse file if necessary */
810*4882a593Smuzhiyun #ifdef CONFIG_EFUSE_CONFIG_FILE
811*4882a593Smuzhiyun if (check_phy_efuse_tx_power_info_valid(adapter) == _FALSE) {
812*4882a593Smuzhiyun if (Hal_readPGDataFromConfigFile(adapter) != _SUCCESS)
813*4882a593Smuzhiyun RTW_WARN("%s: invalid phy efuse and read from file fail, will use driver default!!\n", __FUNCTION__);
814*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
815*4882a593Smuzhiyun else {
816*4882a593Smuzhiyun f_efuse_xcap_b9 = efuse_map[EEPROM_XTAL_B9_8822C];
817*4882a593Smuzhiyun f_efuse_xcap_110_111 = ((efuse_map[EEPROM_XTAL_111_8822C] << 8) | efuse_map[EEPROM_XTAL_110_8822C]);
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun #endif
820*4882a593Smuzhiyun }
821*4882a593Smuzhiyun #endif /* CONFIG_EFUSE_CONFIG_FILE */
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun /* 4. Parse Efuse data */
824*4882a593Smuzhiyun valid = Hal_EfuseParseIDCode(adapter, efuse_map);
825*4882a593Smuzhiyun if (_TRUE == valid)
826*4882a593Smuzhiyun hal->bautoload_fail_flag = _FALSE;
827*4882a593Smuzhiyun else
828*4882a593Smuzhiyun hal->bautoload_fail_flag = _TRUE;
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun Hal_EfuseParseEEPROMVer(adapter, efuse_map, valid);
831*4882a593Smuzhiyun hal_config_macaddr(adapter, hal->bautoload_fail_flag);
832*4882a593Smuzhiyun if (Hal_EfuseParseTxPowerInfo(adapter, efuse_map, valid) != _SUCCESS)
833*4882a593Smuzhiyun goto exit;
834*4882a593Smuzhiyun Hal_EfuseParseBoardType(adapter, efuse_map, valid);
835*4882a593Smuzhiyun Hal_EfuseParseBTCoexistInfo(adapter, efuse_map, valid);
836*4882a593Smuzhiyun Hal_EfuseParseChnlPlan(adapter, efuse_map, hal->bautoload_fail_flag);
837*4882a593Smuzhiyun
838*4882a593Smuzhiyun #ifdef CONFIG_RTL8822C_XCAP_NEW_POLICY
839*4882a593Smuzhiyun if ((adapter->registrypriv.mp_mode == 0) && (hal->EEPROMBluetoothCoexist == _TRUE))
840*4882a593Smuzhiyun hal_efuse_parse_xtal_cap_new(adapter, h_efuse_xcap_110_111, h_efuse_xcap_b9, f_efuse_xcap_110_111, f_efuse_xcap_b9, valid);
841*4882a593Smuzhiyun else
842*4882a593Smuzhiyun #endif
843*4882a593Smuzhiyun Hal_EfuseParseXtal(adapter, efuse_map, valid);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun Hal_EfuseParseThermalMeter(adapter, efuse_map, valid);
846*4882a593Smuzhiyun Hal_EfuseParsePathSelection(adapter, efuse_map, valid);
847*4882a593Smuzhiyun Hal_EfuseParseCustomerID(adapter, efuse_map, valid);
848*4882a593Smuzhiyun Hal_DetectWoWMode(adapter);
849*4882a593Smuzhiyun Hal_ReadAmplifierType(adapter, efuse_map, valid);
850*4882a593Smuzhiyun if (Hal_ReadRFEType(adapter, efuse_map, valid) != _SUCCESS)
851*4882a593Smuzhiyun goto exit;
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun /* Data out of Efuse Map */
854*4882a593Smuzhiyun Hal_EfuseParsePackageType(adapter, efuse_map, valid);
855*4882a593Smuzhiyun /* Hal_EfuseParsePABias(adapter); */
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
858*4882a593Smuzhiyun Hal_ReadUsbModeSwitch(adapter, efuse_map, valid);
859*4882a593Smuzhiyun hal_read_usb_pid_vid(adapter, efuse_map, valid);
860*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun /* set coex. ant info once efuse parsing is done */
863*4882a593Smuzhiyun rtw_btcoex_set_ant_info(adapter);
864*4882a593Smuzhiyun
865*4882a593Smuzhiyun hal_read_mac_hidden_rpt(adapter);
866*4882a593Smuzhiyun {
867*4882a593Smuzhiyun struct hal_spec_t *hal_spec = GET_HAL_SPEC(adapter);
868*4882a593Smuzhiyun
869*4882a593Smuzhiyun if (hal_spec->hci_type <= 3 && hal_spec->hci_type >= 1) {
870*4882a593Smuzhiyun hal->EEPROMBluetoothCoexist = _FALSE;
871*4882a593Smuzhiyun RTW_INFO("EEPROM Disable BT-coex by hal_spec\n");
872*4882a593Smuzhiyun rtw_btcoex_wifionly_AntInfoSetting(adapter);
873*4882a593Smuzhiyun }
874*4882a593Smuzhiyun }
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun rtw_phydm_read_efuse(adapter);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun ret = _SUCCESS;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun exit:
881*4882a593Smuzhiyun return ret;
882*4882a593Smuzhiyun }
883*4882a593Smuzhiyun
rtl8822c_run_thread(PADAPTER adapter)884*4882a593Smuzhiyun void rtl8822c_run_thread(PADAPTER adapter)
885*4882a593Smuzhiyun {
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
rtl8822c_cancel_thread(PADAPTER adapter)888*4882a593Smuzhiyun void rtl8822c_cancel_thread(PADAPTER adapter)
889*4882a593Smuzhiyun {
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun /*
893*4882a593Smuzhiyun * Description:
894*4882a593Smuzhiyun * Using 0x100 to check the power status of FW.
895*4882a593Smuzhiyun */
check_ips_status(PADAPTER adapter)896*4882a593Smuzhiyun static u8 check_ips_status(PADAPTER adapter)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun u8 val8;
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": Read 0x100=0x%02x 0x86=0x%02x\n",
902*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter),
903*4882a593Smuzhiyun rtw_read8(adapter, 0x100), rtw_read8(adapter, 0x86));
904*4882a593Smuzhiyun
905*4882a593Smuzhiyun val8 = rtw_read8(adapter, 0x100);
906*4882a593Smuzhiyun if (val8 == 0xEA)
907*4882a593Smuzhiyun return _TRUE;
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun return _FALSE;
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun
InitBeaconParameters(PADAPTER adapter)912*4882a593Smuzhiyun static void InitBeaconParameters(PADAPTER adapter)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
915*4882a593Smuzhiyun u16 val16;
916*4882a593Smuzhiyun u8 val8;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun
919*4882a593Smuzhiyun val8 = BIT_DIS_TSF_UDT_8822C;
920*4882a593Smuzhiyun val16 = val8 | (val8 << 8); /* port0 and port1 */
921*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
922*4882a593Smuzhiyun if (hal->EEPROMBluetoothCoexist)
923*4882a593Smuzhiyun /* Enable port0 beacon function for PSTDMA under BTCOEX */
924*4882a593Smuzhiyun val16 |= EN_BCN_FUNCTION;
925*4882a593Smuzhiyun #endif
926*4882a593Smuzhiyun rtw_write16(adapter, REG_BCN_CTRL_8822C, val16);
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun /* TBTT setup time */
929*4882a593Smuzhiyun rtw_write8(adapter, REG_TBTT_PROHIBIT_8822C, TBTT_PROHIBIT_SETUP_TIME);
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun /* TBTT hold time: 0x540[19:8] */
932*4882a593Smuzhiyun rtw_write8(adapter, REG_TBTT_PROHIBIT_8822C + 1, TBTT_PROHIBIT_HOLD_TIME_STOP_BCN & 0xFF);
933*4882a593Smuzhiyun rtw_write8(adapter, REG_TBTT_PROHIBIT_8822C + 2,
934*4882a593Smuzhiyun (rtw_read8(adapter, REG_TBTT_PROHIBIT_8822C + 2) & 0xF0) | (TBTT_PROHIBIT_HOLD_TIME_STOP_BCN >> 8));
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun rtw_write8(adapter, REG_DRVERLYINT_8822C, DRIVER_EARLY_INT_TIME_8822C); /* 5ms */
937*4882a593Smuzhiyun rtw_write8(adapter, REG_BCNDMATIM_8822C, BCN_DMA_ATIME_INT_TIME_8822C); /* 2ms */
938*4882a593Smuzhiyun
939*4882a593Smuzhiyun /*
940*4882a593Smuzhiyun * Suggested by designer timchen. Change beacon AIFS to the largest number
941*4882a593Smuzhiyun * beacause test chip does not contension before sending beacon.
942*4882a593Smuzhiyun */
943*4882a593Smuzhiyun rtw_write16(adapter, REG_BCNTCFG_8822C, 0x4413);
944*4882a593Smuzhiyun }
945*4882a593Smuzhiyun
beacon_function_enable(PADAPTER adapter,u8 Enable,u8 Linked)946*4882a593Smuzhiyun static void beacon_function_enable(PADAPTER adapter, u8 Enable, u8 Linked)
947*4882a593Smuzhiyun {
948*4882a593Smuzhiyun u8 val8;
949*4882a593Smuzhiyun u32 bcn_ctrl_reg;
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun /* port0 */
952*4882a593Smuzhiyun bcn_ctrl_reg = REG_BCN_CTRL_8822C;
953*4882a593Smuzhiyun val8 = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;
954*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
955*4882a593Smuzhiyun /* port1 */
956*4882a593Smuzhiyun if (adapter->hw_port == HW_PORT1) {
957*4882a593Smuzhiyun bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822C;
958*4882a593Smuzhiyun val8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;
959*4882a593Smuzhiyun }
960*4882a593Smuzhiyun #endif
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun rtw_write8(adapter, bcn_ctrl_reg, val8);
963*4882a593Smuzhiyun rtw_write8(adapter, REG_RD_CTRL_8822C + 1, 0x6F);
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
set_beacon_related_registers(PADAPTER adapter)966*4882a593Smuzhiyun static void set_beacon_related_registers(PADAPTER adapter)
967*4882a593Smuzhiyun {
968*4882a593Smuzhiyun u8 val8;
969*4882a593Smuzhiyun u32 value32;
970*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
971*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
972*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
973*4882a593Smuzhiyun u32 bcn_ctrl_reg, bcn_interval_reg;
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun /* reset TSF, enable update TSF, correcting TSF On Beacon */
977*4882a593Smuzhiyun /*
978*4882a593Smuzhiyun * REG_MBSSID_BCN_SPACE
979*4882a593Smuzhiyun * REG_BCNDMATIM
980*4882a593Smuzhiyun * REG_ATIMWND
981*4882a593Smuzhiyun * REG_TBTT_PROHIBIT
982*4882a593Smuzhiyun * REG_DRVERLYINT
983*4882a593Smuzhiyun * REG_BCN_MAX_ERR
984*4882a593Smuzhiyun * REG_BCNTCFG (0x510)
985*4882a593Smuzhiyun * REG_DUAL_TSF_RST
986*4882a593Smuzhiyun * REG_BCN_CTRL (0x550)
987*4882a593Smuzhiyun */
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun bcn_ctrl_reg = REG_BCN_CTRL_8822C;
990*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
991*4882a593Smuzhiyun if (adapter->hw_port == HW_PORT1)
992*4882a593Smuzhiyun bcn_ctrl_reg = REG_BCN_CTRL_CLINT0_8822C;
993*4882a593Smuzhiyun #endif
994*4882a593Smuzhiyun
995*4882a593Smuzhiyun /*
996*4882a593Smuzhiyun * ATIM window
997*4882a593Smuzhiyun */
998*4882a593Smuzhiyun rtw_write16(adapter, REG_ATIMWND_8822C, 2);
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun /*
1001*4882a593Smuzhiyun * Beacon interval (in unit of TU).
1002*4882a593Smuzhiyun */
1003*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_BEACON_INTERVAL, (u8 *)&pmlmeinfo->bcn_interval);
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun InitBeaconParameters(adapter);
1006*4882a593Smuzhiyun
1007*4882a593Smuzhiyun rtw_write8(adapter, REG_SLOT_8822C, 0x09);
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun /* Reset TSF Timer to zero */
1010*4882a593Smuzhiyun val8 = BIT_TSFTR_RST_8822C;
1011*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1012*4882a593Smuzhiyun if (adapter->hw_port == HW_PORT1)
1013*4882a593Smuzhiyun val8 = BIT_TSFTR_CLI0_RST_8822C;
1014*4882a593Smuzhiyun #endif
1015*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);
1016*4882a593Smuzhiyun val8 = BIT_TSFTR_RST_8822C;
1017*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun rtw_write8(adapter, REG_RXTSF_OFFSET_CCK_8822C, 0x50);
1020*4882a593Smuzhiyun rtw_write8(adapter, REG_RXTSF_OFFSET_OFDM_8822C, 0x50);
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun beacon_function_enable(adapter, _TRUE, _TRUE);
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1025*4882a593Smuzhiyun }
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
xmit_status_check(PADAPTER p)1028*4882a593Smuzhiyun static void xmit_status_check(PADAPTER p)
1029*4882a593Smuzhiyun {
1030*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
1031*4882a593Smuzhiyun struct sreset_priv *psrtpriv = &hal->srestpriv;
1032*4882a593Smuzhiyun struct xmit_priv *pxmitpriv = &p->xmitpriv;
1033*4882a593Smuzhiyun systime current_time = 0;
1034*4882a593Smuzhiyun unsigned int diff_time = 0;
1035*4882a593Smuzhiyun u32 txdma_status = 0;
1036*4882a593Smuzhiyun
1037*4882a593Smuzhiyun txdma_status = rtw_read32(p, REG_TXDMA_STATUS_8822C);
1038*4882a593Smuzhiyun if (txdma_status != 0x00) {
1039*4882a593Smuzhiyun RTW_INFO("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status);
1040*4882a593Smuzhiyun psrtpriv->tx_dma_status_cnt++;
1041*4882a593Smuzhiyun psrtpriv->self_dect_case = 4;
1042*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1043*4882a593Smuzhiyun }
1044*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
1045*4882a593Smuzhiyun current_time = rtw_get_current_time();
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun if (0 == pxmitpriv->free_xmitbuf_cnt || 0 == pxmitpriv->free_xmit_extbuf_cnt) {
1048*4882a593Smuzhiyun diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_time);
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun if (diff_time > 2000) {
1051*4882a593Smuzhiyun if (psrtpriv->last_tx_complete_time == 0)
1052*4882a593Smuzhiyun psrtpriv->last_tx_complete_time = current_time;
1053*4882a593Smuzhiyun else {
1054*4882a593Smuzhiyun diff_time = rtw_get_passing_time_ms(psrtpriv->last_tx_complete_time);
1055*4882a593Smuzhiyun if (diff_time > 4000) {
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun RTW_INFO("%s tx hang %s\n", __FUNCTION__,
1058*4882a593Smuzhiyun !adapter_to_rfctl(p)->adaptivity_en ? "" :
1059*4882a593Smuzhiyun rtw_edcca_mode_str(rtw_get_edcca_mode(adapter_to_dvobj(p), hal->current_band_type)));
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun if (!adapter_to_rfctl(p)->adaptivity_en) {
1062*4882a593Smuzhiyun psrtpriv->self_dect_tx_cnt++;
1063*4882a593Smuzhiyun psrtpriv->self_dect_case = 1;
1064*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun }
1067*4882a593Smuzhiyun }
1068*4882a593Smuzhiyun }
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun if (psrtpriv->dbg_trigger_point == SRESET_TGP_XMIT_STATUS) {
1073*4882a593Smuzhiyun psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
1074*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1075*4882a593Smuzhiyun return;
1076*4882a593Smuzhiyun }
1077*4882a593Smuzhiyun }
1078*4882a593Smuzhiyun
1079*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
check_rx_count(PADAPTER p)1080*4882a593Smuzhiyun static void check_rx_count(PADAPTER p)
1081*4882a593Smuzhiyun {
1082*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
1083*4882a593Smuzhiyun struct sreset_priv *psrtpriv = &hal->srestpriv;
1084*4882a593Smuzhiyun u16 cur_mac_rxff_ptr;
1085*4882a593Smuzhiyun
1086*4882a593Smuzhiyun cur_mac_rxff_ptr = rtw_read16(p, REG_RXFF_PTR_V1_8822C);
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun #if 0
1089*4882a593Smuzhiyun RTW_INFO("%s,psrtpriv->last_mac_rxff_ptr = %d , cur_mac_rxff_ptr = %d\n", __func__, psrtpriv->last_mac_rxff_ptr, cur_mac_rxff_ptr);
1090*4882a593Smuzhiyun #endif
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun if (psrtpriv->last_mac_rxff_ptr == cur_mac_rxff_ptr) {
1093*4882a593Smuzhiyun psrtpriv->rx_cnt++;
1094*4882a593Smuzhiyun #if 0
1095*4882a593Smuzhiyun RTW_INFO("%s,MAC case rx_cnt=%d\n", __func__, psrtpriv->rx_cnt);
1096*4882a593Smuzhiyun #endif
1097*4882a593Smuzhiyun goto exit;
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun psrtpriv->rx_cnt = 0;
1101*4882a593Smuzhiyun
1102*4882a593Smuzhiyun exit:
1103*4882a593Smuzhiyun
1104*4882a593Smuzhiyun psrtpriv->last_mac_rxff_ptr = cur_mac_rxff_ptr;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun if (psrtpriv->rx_cnt > 3) {
1107*4882a593Smuzhiyun psrtpriv->self_dect_case = 2;
1108*4882a593Smuzhiyun psrtpriv->self_dect_rx_cnt++;
1109*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1110*4882a593Smuzhiyun }
1111*4882a593Smuzhiyun }
1112*4882a593Smuzhiyun #endif/*#ifdef CONFIG_USB_HCI*/
1113*4882a593Smuzhiyun
linked_status_check(PADAPTER p)1114*4882a593Smuzhiyun static void linked_status_check(PADAPTER p)
1115*4882a593Smuzhiyun {
1116*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(p);
1117*4882a593Smuzhiyun struct sreset_priv *psrtpriv = &hal->srestpriv;
1118*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(p);
1119*4882a593Smuzhiyun u32 rx_dma_status = 0;
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun rx_dma_status = rtw_read32(p, REG_RXDMA_STATUS_8822C);
1122*4882a593Smuzhiyun if (rx_dma_status != 0x00) {
1123*4882a593Smuzhiyun RTW_INFO("%s REG_RXDMA_STATUS:0x%08x\n", __FUNCTION__, rx_dma_status);
1124*4882a593Smuzhiyun psrtpriv->rx_dma_status_cnt++;
1125*4882a593Smuzhiyun psrtpriv->self_dect_case = 5;
1126*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
1127*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1128*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
1129*4882a593Smuzhiyun }
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun if (psrtpriv->self_dect_fw) {
1132*4882a593Smuzhiyun psrtpriv->self_dect_case = 3;
1133*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
1134*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1135*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI || CONFIG_PCI_HCI */
1136*4882a593Smuzhiyun }
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
1139*4882a593Smuzhiyun check_rx_count(p);
1140*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
1141*4882a593Smuzhiyun
1142*4882a593Smuzhiyun if (psrtpriv->dbg_trigger_point == SRESET_TGP_LINK_STATUS) {
1143*4882a593Smuzhiyun psrtpriv->dbg_trigger_point = SRESET_TGP_NULL;
1144*4882a593Smuzhiyun rtw_hal_sreset_reset(p);
1145*4882a593Smuzhiyun return;
1146*4882a593Smuzhiyun }
1147*4882a593Smuzhiyun }
1148*4882a593Smuzhiyun #endif /* DBG_CONFIG_ERROR_DETECT */
1149*4882a593Smuzhiyun
set_opmode_monitor(PADAPTER adapter)1150*4882a593Smuzhiyun static void set_opmode_monitor(PADAPTER adapter)
1151*4882a593Smuzhiyun {
1152*4882a593Smuzhiyun #ifdef CONFIG_WIFI_MONITOR
1153*4882a593Smuzhiyun u8 tmp_8bit;
1154*4882a593Smuzhiyun u32 tmp_32bit;
1155*4882a593Smuzhiyun struct net_device *ndev = adapter->pnetdev;
1156*4882a593Smuzhiyun struct mon_reg_backup *mon = &GET_HAL_DATA(adapter)->mon_backup;
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun mon->known_rcr = 1;
1159*4882a593Smuzhiyun rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)& mon->rcr);
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun /* Receive all type */
1162*4882a593Smuzhiyun tmp_32bit = BIT_AAP_8822C | BIT_APP_PHYSTS_8822C;
1163*4882a593Smuzhiyun
1164*4882a593Smuzhiyun if (ndev->type == ARPHRD_IEEE80211_RADIOTAP) {
1165*4882a593Smuzhiyun /* Append FCS */
1166*4882a593Smuzhiyun tmp_32bit |= BIT_APP_FCS_8822C;
1167*4882a593Smuzhiyun }
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)& tmp_32bit);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun if (1)
1172*4882a593Smuzhiyun rtw_halmac_config_rx_info(adapter_to_dvobj(adapter),
1173*4882a593Smuzhiyun HALMAC_DRV_INFO_PHY_SNIFFER);
1174*4882a593Smuzhiyun else
1175*4882a593Smuzhiyun rtw_halmac_config_rx_info(adapter_to_dvobj(adapter),
1176*4882a593Smuzhiyun HALMAC_DRV_INFO_PHY_PLCP);
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun tmp_8bit = rtw_read8(adapter, REG_RX_DRVINFO_SZ_8822C);
1179*4882a593Smuzhiyun rtw_write8(adapter, REG_RX_DRVINFO_SZ_8822C, (tmp_8bit | 0x80));
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun /* Receive all data frames */
1182*4882a593Smuzhiyun mon->known_rxfilter = 1;
1183*4882a593Smuzhiyun mon->rxfilter0 = rtw_read16(adapter, REG_RXFLTMAP0_8822C);
1184*4882a593Smuzhiyun mon->rxfilter1 = rtw_read16(adapter, REG_RXFLTMAP1_8822C);
1185*4882a593Smuzhiyun mon->rxfilter2 = rtw_read16(adapter, REG_RXFLTMAP2_8822C);
1186*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP0_8822C, 0xFFFF);
1187*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP1_8822C, 0xFFFF);
1188*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);
1189*4882a593Smuzhiyun #endif /* CONFIG_WIFI_MONITOR */
1190*4882a593Smuzhiyun }
1191*4882a593Smuzhiyun #ifndef CONFIG_MI_WITH_MBSSID_CAM
set_opmode_port0(PADAPTER adapter,u8 mode)1192*4882a593Smuzhiyun static void set_opmode_port0(PADAPTER adapter, u8 mode)
1193*4882a593Smuzhiyun {
1194*4882a593Smuzhiyun u8 is_tx_bcn;
1195*4882a593Smuzhiyun u8 val8;
1196*4882a593Smuzhiyun u16 val16;
1197*4882a593Smuzhiyun u32 val32;
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun
1200*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1201*4882a593Smuzhiyun is_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter);
1202*4882a593Smuzhiyun #else /* !CONFIG_CONCURRENT_MODE */
1203*4882a593Smuzhiyun is_tx_bcn = 0;
1204*4882a593Smuzhiyun #endif /* !CONFIG_CONCURRENT_MODE */
1205*4882a593Smuzhiyun
1206*4882a593Smuzhiyun /* disable Port0 TSF update */
1207*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1208*4882a593Smuzhiyun
1209*4882a593Smuzhiyun Set_MSR(adapter, mode);
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": hw_port(%d) mode=%d\n",
1212*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);
1213*4882a593Smuzhiyun
1214*4882a593Smuzhiyun switch (mode) {
1215*4882a593Smuzhiyun case _HW_STATE_NOLINK_:
1216*4882a593Smuzhiyun case _HW_STATE_STATION_:
1217*4882a593Smuzhiyun if (!is_tx_bcn) {
1218*4882a593Smuzhiyun StopTxBeacon(adapter);
1219*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
1220*4882a593Smuzhiyun UpdateInterruptMask8822CE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);
1221*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
1222*4882a593Smuzhiyun }
1223*4882a593Smuzhiyun
1224*4882a593Smuzhiyun /* disable beacon function */
1225*4882a593Smuzhiyun val8 = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;
1226*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_8822C, val8);
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun /* disable atim wnd(only for Port0) */
1229*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_DIS_ATIM_8822C);
1230*4882a593Smuzhiyun val8 |= BIT_DIS_ATIM_ROOT_8822C;
1231*4882a593Smuzhiyun rtw_write8(adapter, REG_DIS_ATIM_8822C, val8);
1232*4882a593Smuzhiyun break;
1233*4882a593Smuzhiyun
1234*4882a593Smuzhiyun case _HW_STATE_ADHOC_:
1235*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1236*4882a593Smuzhiyun val8 = BIT_DIS_TSF_UDT_8822C | BIT_EN_BCN_FUNCTION_8822C;
1237*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_8822C, val8);
1238*4882a593Smuzhiyun break;
1239*4882a593Smuzhiyun
1240*4882a593Smuzhiyun case _HW_STATE_AP_:
1241*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
1242*4882a593Smuzhiyun UpdateInterruptMask8822CE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);
1243*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
1244*4882a593Smuzhiyun
1245*4882a593Smuzhiyun /*
1246*4882a593Smuzhiyun * enable BCN0 Function for if1
1247*4882a593Smuzhiyun * disable update TSF0 for if1
1248*4882a593Smuzhiyun * enable TX BCN report:
1249*4882a593Smuzhiyun * Reg REG_FWHW_TXQ_CTRL_8822C [2] = 1
1250*4882a593Smuzhiyun * Reg REG_BCN_CTRL_8822C[3][5] = 1
1251*4882a593Smuzhiyun * Enable ATIM
1252*4882a593Smuzhiyun * Enable HW seq for BCN
1253*4882a593Smuzhiyun */
1254*4882a593Smuzhiyun /* enable TX BCN report */
1255*4882a593Smuzhiyun /* disable RX BCN report */
1256*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C);
1257*4882a593Smuzhiyun val8 |= BIT_EN_BCN_TRXRPT_V1_8822C;
1258*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C, val8);
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun /* enable BCN0 Function */
1261*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_BCN_CTRL_8822C);
1262*4882a593Smuzhiyun val8 |= BIT_EN_BCN_FUNCTION_8822C | BIT_DIS_TSF_UDT_8822C | BIT_P0_EN_TXBCN_RPT_8822C;
1263*4882a593Smuzhiyun val8 &= (~BIT_P0_EN_RXBCN_RPT_8822C);
1264*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_8822C, val8);
1265*4882a593Smuzhiyun
1266*4882a593Smuzhiyun /* Enable ATIM */
1267*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_DIS_ATIM_8822C);
1268*4882a593Smuzhiyun val8 &= ~BIT_DIS_ATIM_ROOT_8822C;
1269*4882a593Smuzhiyun rtw_write8(adapter, REG_DIS_ATIM_8822C, val8);
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun /* Enable HW seq for BCN
1272*4882a593Smuzhiyun 0x4FC[0]: EN_HWSEQ
1273*4882a593Smuzhiyun 0x4FC[1]: EN_HWSEQEXT
1274*4882a593Smuzhiyun According TX desc
1275*4882a593Smuzhiyun */
1276*4882a593Smuzhiyun rtw_write8(adapter, REG_DUMMY_PAGE4_V1_8822C, 0x01);
1277*4882a593Smuzhiyun
1278*4882a593Smuzhiyun /* enable to rx data frame */
1279*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);
1280*4882a593Smuzhiyun /* enable to rx ps-poll */
1281*4882a593Smuzhiyun val16 = rtw_read16(adapter, REG_RXFLTMAP1_8822C);
1282*4882a593Smuzhiyun val16 |= BIT_CTRLFLT10EN_8822C;
1283*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP1_8822C, val16);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun /* Beacon Control related register for first time */
1286*4882a593Smuzhiyun rtw_write8(adapter, REG_BCNDMATIM_8822C, 0x02); /* 2ms */
1287*4882a593Smuzhiyun
1288*4882a593Smuzhiyun rtw_write8(adapter, REG_ATIMWND_8822C, 0x0c); /* 12ms */
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun
1291*4882a593Smuzhiyun rtw_write16(adapter, REG_TSFTR_SYN_OFFSET_8822C, 0x7fff); /* +32767 (~32ms) */
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun /* reset TSF */
1294*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C);
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun /* SW_BCN_SEL - Port0 */
1297*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);
1298*4882a593Smuzhiyun
1299*4882a593Smuzhiyun /* select BCN on port 0 */
1300*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_CCK_CHECK_8822C);
1301*4882a593Smuzhiyun val8 &= ~BIT_BCN_PORT_SEL_8822C;
1302*4882a593Smuzhiyun rtw_write8(adapter, REG_CCK_CHECK_8822C, val8);
1303*4882a593Smuzhiyun break;
1304*4882a593Smuzhiyun }
1305*4882a593Smuzhiyun }
set_opmode_port1(PADAPTER adapter,u8 mode)1306*4882a593Smuzhiyun static void set_opmode_port1(PADAPTER adapter, u8 mode)
1307*4882a593Smuzhiyun {
1308*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1309*4882a593Smuzhiyun u8 is_tx_bcn;
1310*4882a593Smuzhiyun u8 val8;
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun is_tx_bcn = rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter);
1313*4882a593Smuzhiyun
1314*4882a593Smuzhiyun /* disable Port1 TSF update */
1315*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1316*4882a593Smuzhiyun
1317*4882a593Smuzhiyun Set_MSR(adapter, mode);
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": hw_port(%d) mode=%d\n",
1320*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), adapter->hw_port, mode);
1321*4882a593Smuzhiyun
1322*4882a593Smuzhiyun switch (mode) {
1323*4882a593Smuzhiyun case _HW_STATE_NOLINK_:
1324*4882a593Smuzhiyun case _HW_STATE_STATION_:
1325*4882a593Smuzhiyun if (!is_tx_bcn) {
1326*4882a593Smuzhiyun StopTxBeacon(adapter);
1327*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
1328*4882a593Smuzhiyun UpdateInterruptMask8822CE(adapter, 0, 0, RT_BCN_INT_MASKS, 0);
1329*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
1330*4882a593Smuzhiyun }
1331*4882a593Smuzhiyun
1332*4882a593Smuzhiyun /* disable beacon function */
1333*4882a593Smuzhiyun val8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;
1334*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);
1335*4882a593Smuzhiyun break;
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun case _HW_STATE_ADHOC_:
1338*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1339*4882a593Smuzhiyun val8 = BIT_CLI0_DIS_TSF_UDT_8822C | BIT_CLI0_EN_BCN_FUNCTION_8822C;
1340*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);
1341*4882a593Smuzhiyun break;
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun case _HW_STATE_AP_:
1344*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
1345*4882a593Smuzhiyun UpdateInterruptMask8822CE(adapter, RT_BCN_INT_MASKS, 0, 0, 0);
1346*4882a593Smuzhiyun #endif /* CONFIG_PCI_HCI */
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun /* ToDo */
1349*4882a593Smuzhiyun break;
1350*4882a593Smuzhiyun }
1351*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */
1352*4882a593Smuzhiyun }
1353*4882a593Smuzhiyun #endif /* !CONFIG_MI_WITH_MBSSID_CAM */
1354*4882a593Smuzhiyun
hw_tsf_reset(_adapter * adapter)1355*4882a593Smuzhiyun void hw_tsf_reset(_adapter *adapter)
1356*4882a593Smuzhiyun {
1357*4882a593Smuzhiyun u8 hw_port = rtw_hal_get_port(adapter);
1358*4882a593Smuzhiyun u32 tsf_rst_addr = 0;
1359*4882a593Smuzhiyun u8 tsf_rst_bit = 0;
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun if (hw_port >= MAX_HW_PORT) {
1362*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" HW Port(%d) invalid\n", FUNC_ADPT_ARG(adapter), hw_port);
1363*4882a593Smuzhiyun rtw_warn_on(1);
1364*4882a593Smuzhiyun return;
1365*4882a593Smuzhiyun }
1366*4882a593Smuzhiyun
1367*4882a593Smuzhiyun tsf_rst_addr = port_cfg[hw_port].tsf_rst;
1368*4882a593Smuzhiyun tsf_rst_bit = port_cfg[hw_port].tsf_rst_bit;
1369*4882a593Smuzhiyun rtw_write8(adapter, tsf_rst_addr, tsf_rst_bit);
1370*4882a593Smuzhiyun }
hw_set_ta(_adapter * adapter,u8 hw_port,u8 * val)1371*4882a593Smuzhiyun void hw_set_ta(_adapter *adapter, u8 hw_port, u8 *val)
1372*4882a593Smuzhiyun {
1373*4882a593Smuzhiyun u8 idx = 0;
1374*4882a593Smuzhiyun u32 reg = port_cfg[hw_port].ta;
1375*4882a593Smuzhiyun
1376*4882a593Smuzhiyun for (idx = 0 ; idx < ETH_ALEN; idx++)
1377*4882a593Smuzhiyun rtw_write8(adapter, (reg + idx), val[idx]);
1378*4882a593Smuzhiyun
1379*4882a593Smuzhiyun RTW_INFO("%s("ADPT_FMT") hw port -%d TA: "MAC_FMT"\n",
1380*4882a593Smuzhiyun __func__, ADPT_ARG(adapter), hw_port, MAC_ARG(val));
1381*4882a593Smuzhiyun }
hw_set_aid(_adapter * adapter,u8 hw_port,u8 aid)1382*4882a593Smuzhiyun void hw_set_aid(_adapter *adapter, u8 hw_port, u8 aid)
1383*4882a593Smuzhiyun {
1384*4882a593Smuzhiyun rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | aid));
1385*4882a593Smuzhiyun RTW_INFO("%s("ADPT_FMT") hw port -%d AID: %d\n",
1386*4882a593Smuzhiyun __func__, ADPT_ARG(adapter), hw_port, aid);
1387*4882a593Smuzhiyun }
1388*4882a593Smuzhiyun #ifdef CONFIG_CLIENT_PORT_CFG
rtw_hw_client_port_cfg(_adapter * adapter)1389*4882a593Smuzhiyun void rtw_hw_client_port_cfg(_adapter *adapter)
1390*4882a593Smuzhiyun {
1391*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
1392*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
1393*4882a593Smuzhiyun u8 clt_port = get_clt_port(adapter);
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun if (clt_port == CLT_PORT_INVALID)
1396*4882a593Smuzhiyun return;
1397*4882a593Smuzhiyun RTW_INFO("%s ("ADPT_FMT")\n", __func__, ADPT_ARG(adapter));
1398*4882a593Smuzhiyun
1399*4882a593Smuzhiyun /*Network type*/
1400*4882a593Smuzhiyun rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_STATION_);
1401*4882a593Smuzhiyun /*A1*/
1402*4882a593Smuzhiyun rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, adapter_mac_addr(adapter));
1403*4882a593Smuzhiyun /*A2*/
1404*4882a593Smuzhiyun hw_set_ta(adapter, clt_port, pmlmeinfo->network.MacAddress);
1405*4882a593Smuzhiyun /*A3*/
1406*4882a593Smuzhiyun rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->network.MacAddress);
1407*4882a593Smuzhiyun /*Beacon space*/
1408*4882a593Smuzhiyun rtw_halmac_set_bcn_interval(adapter_to_dvobj(adapter), clt_port, pmlmeinfo->bcn_interval);
1409*4882a593Smuzhiyun /*AID*/
1410*4882a593Smuzhiyun hw_set_aid(adapter, clt_port, pmlmeinfo->aid);
1411*4882a593Smuzhiyun /*Beacon control*/
1412*4882a593Smuzhiyun hw_bcn_ctrl_set(adapter, clt_port, (BIT_P0_EN_RXBCN_RPT | BIT_EN_BCN_FUNCTION));
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun RTW_INFO("%s ("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port);
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun /*#define DBG_TSF_MONITOR*/
rtw_hw_client_port_clr(_adapter * adapter)1418*4882a593Smuzhiyun void rtw_hw_client_port_clr(_adapter *adapter)
1419*4882a593Smuzhiyun {
1420*4882a593Smuzhiyun u8 null_addr[ETH_ALEN] = {0};
1421*4882a593Smuzhiyun u8 clt_port = get_clt_port(adapter);
1422*4882a593Smuzhiyun
1423*4882a593Smuzhiyun if (clt_port == CLT_PORT_INVALID)
1424*4882a593Smuzhiyun return;
1425*4882a593Smuzhiyun RTW_INFO("%s ("ADPT_FMT") ==> \n", __func__, ADPT_ARG(adapter));
1426*4882a593Smuzhiyun
1427*4882a593Smuzhiyun #ifdef DBG_TSF_MONITOR
1428*4882a593Smuzhiyun /*Beacon control*/
1429*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, clt_port, BIT_EN_BCN_FUNCTION);
1430*4882a593Smuzhiyun hw_tsf_reset(adapter);
1431*4882a593Smuzhiyun #endif
1432*4882a593Smuzhiyun
1433*4882a593Smuzhiyun /*Network type*/
1434*4882a593Smuzhiyun rtw_halmac_set_network_type(adapter_to_dvobj(adapter), clt_port, _HW_STATE_NOLINK_);
1435*4882a593Smuzhiyun /*A1*/
1436*4882a593Smuzhiyun rtw_halmac_set_mac_address(adapter_to_dvobj(adapter), clt_port, null_addr);
1437*4882a593Smuzhiyun /*A2*/
1438*4882a593Smuzhiyun hw_set_ta(adapter, clt_port, null_addr);
1439*4882a593Smuzhiyun /*A3*/
1440*4882a593Smuzhiyun rtw_halmac_set_bssid(adapter_to_dvobj(adapter), clt_port, null_addr);
1441*4882a593Smuzhiyun
1442*4882a593Smuzhiyun #ifdef DBG_TSF_MONITOR
1443*4882a593Smuzhiyun if (0)
1444*4882a593Smuzhiyun #endif
1445*4882a593Smuzhiyun /*Beacon control*/
1446*4882a593Smuzhiyun hw_bcn_ctrl_set(adapter, clt_port, (BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));
1447*4882a593Smuzhiyun
1448*4882a593Smuzhiyun /*AID*/
1449*4882a593Smuzhiyun hw_set_aid(adapter, clt_port, 0);
1450*4882a593Smuzhiyun RTW_INFO("%s("ADPT_FMT") clt_port:%d\n", __func__, ADPT_ARG(adapter), clt_port);
1451*4882a593Smuzhiyun }
1452*4882a593Smuzhiyun #endif
1453*4882a593Smuzhiyun
hw_var_set_opmode(PADAPTER adapter,u8 mode)1454*4882a593Smuzhiyun static void hw_var_set_opmode(PADAPTER adapter, u8 mode)
1455*4882a593Smuzhiyun {
1456*4882a593Smuzhiyun static u8 isMonitor = _FALSE;
1457*4882a593Smuzhiyun
1458*4882a593Smuzhiyun if (isMonitor == _TRUE) {
1459*4882a593Smuzhiyun #ifdef CONFIG_WIFI_MONITOR
1460*4882a593Smuzhiyun struct mon_reg_backup *backup = &GET_HAL_DATA(adapter)->mon_backup;
1461*4882a593Smuzhiyun
1462*4882a593Smuzhiyun if (backup->known_rcr) {
1463*4882a593Smuzhiyun backup->known_rcr = 0;
1464*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_RCR, (u8 *)&backup->rcr);
1465*4882a593Smuzhiyun
1466*4882a593Smuzhiyun if (!!(backup->rcr &= BIT_APP_PHYSTS_8822C))
1467*4882a593Smuzhiyun rtw_halmac_config_rx_info(adapter_to_dvobj(adapter),
1468*4882a593Smuzhiyun HALMAC_DRV_INFO_PHY_STATUS);
1469*4882a593Smuzhiyun else
1470*4882a593Smuzhiyun rtw_halmac_config_rx_info(adapter_to_dvobj(adapter),
1471*4882a593Smuzhiyun HALMAC_DRV_INFO_NONE);
1472*4882a593Smuzhiyun
1473*4882a593Smuzhiyun rtw_hal_rcr_set_chk_bssid(adapter, MLME_ACTION_NONE);
1474*4882a593Smuzhiyun }
1475*4882a593Smuzhiyun if (backup->known_rxfilter) {
1476*4882a593Smuzhiyun backup->known_rxfilter = 0;
1477*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP0_8822C, backup->rxfilter0);
1478*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP1_8822C, backup->rxfilter1);
1479*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, backup->rxfilter2);
1480*4882a593Smuzhiyun }
1481*4882a593Smuzhiyun #endif /* CONFIG_WIFI_MONITOR */
1482*4882a593Smuzhiyun isMonitor = _FALSE;
1483*4882a593Smuzhiyun }
1484*4882a593Smuzhiyun
1485*4882a593Smuzhiyun if (mode == _HW_STATE_MONITOR_) {
1486*4882a593Smuzhiyun isMonitor = _TRUE;
1487*4882a593Smuzhiyun
1488*4882a593Smuzhiyun Set_MSR(adapter, _HW_STATE_NOLINK_);
1489*4882a593Smuzhiyun set_opmode_monitor(adapter);
1490*4882a593Smuzhiyun return;
1491*4882a593Smuzhiyun }
1492*4882a593Smuzhiyun
1493*4882a593Smuzhiyun /* clear crc bit */
1494*4882a593Smuzhiyun if (rtw_hal_rcr_check(adapter, BIT_ACRC32_8822C))
1495*4882a593Smuzhiyun rtw_hal_rcr_clear(adapter, BIT_ACRC32_8822C);
1496*4882a593Smuzhiyun
1497*4882a593Smuzhiyun #ifdef CONFIG_MI_WITH_MBSSID_CAM /*For Port0 - MBSS CAM*/
1498*4882a593Smuzhiyun if (adapter->hw_port != HW_PORT0) {
1499*4882a593Smuzhiyun RTW_ERR(ADPT_FMT ": Configure MBSSID cam on HW_PORT%d\n", ADPT_ARG(adapter), adapter->hw_port);
1500*4882a593Smuzhiyun rtw_warn_on(1);
1501*4882a593Smuzhiyun } else
1502*4882a593Smuzhiyun hw_var_set_opmode_mbid(adapter, mode);
1503*4882a593Smuzhiyun #else
1504*4882a593Smuzhiyun
1505*4882a593Smuzhiyun switch (adapter->hw_port) {
1506*4882a593Smuzhiyun case HW_PORT0:
1507*4882a593Smuzhiyun set_opmode_port0(adapter, mode);
1508*4882a593Smuzhiyun break;
1509*4882a593Smuzhiyun
1510*4882a593Smuzhiyun case HW_PORT1:
1511*4882a593Smuzhiyun set_opmode_port1(adapter, mode);
1512*4882a593Smuzhiyun break;
1513*4882a593Smuzhiyun
1514*4882a593Smuzhiyun default:
1515*4882a593Smuzhiyun break;
1516*4882a593Smuzhiyun }
1517*4882a593Smuzhiyun #endif
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun
hw_var_hw_port_cfg(_adapter * adapter,u8 enable)1520*4882a593Smuzhiyun static void hw_var_hw_port_cfg(_adapter *adapter, u8 enable)
1521*4882a593Smuzhiyun {
1522*4882a593Smuzhiyun if (enable)
1523*4882a593Smuzhiyun hw_bcn_ctrl_add(adapter, get_hw_port(adapter), (BIT_P0_EN_RXBCN_RPT | BIT_DIS_TSF_UDT | BIT_EN_BCN_FUNCTION));
1524*4882a593Smuzhiyun else
1525*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_EN_BCN_FUNCTION);
1526*4882a593Smuzhiyun }
1527*4882a593Smuzhiyun
hw_var_set_bcn_func(PADAPTER adapter,u8 enable)1528*4882a593Smuzhiyun static void hw_var_set_bcn_func(PADAPTER adapter, u8 enable)
1529*4882a593Smuzhiyun {
1530*4882a593Smuzhiyun u8 val8 = 0;
1531*4882a593Smuzhiyun
1532*4882a593Smuzhiyun if (enable) {
1533*4882a593Smuzhiyun /* enable TX BCN report
1534*4882a593Smuzhiyun * Reg REG_FWHW_TXQ_CTRL_8822C[2] = 1
1535*4882a593Smuzhiyun * Reg REG_BCN_CTRL_8822C[3][5] = 1
1536*4882a593Smuzhiyun */
1537*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C);
1538*4882a593Smuzhiyun val8 |= BIT_EN_BCN_TRXRPT_V1_8822C;
1539*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C, val8);
1540*4882a593Smuzhiyun
1541*4882a593Smuzhiyun
1542*4882a593Smuzhiyun switch (adapter->hw_port) {
1543*4882a593Smuzhiyun case HW_PORT0:
1544*4882a593Smuzhiyun val8 = BIT_EN_BCN_FUNCTION_8822C | BIT_P0_EN_TXBCN_RPT_8822C;
1545*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_P0_EN_RXBCN_RPT_8822C);
1546*4882a593Smuzhiyun break;
1547*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1548*4882a593Smuzhiyun case HW_PORT1:
1549*4882a593Smuzhiyun val8 = BIT_CLI0_EN_BCN_FUNCTION_8822C;
1550*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI0_EN_RXBCN_RPT_8822C);
1551*4882a593Smuzhiyun break;
1552*4882a593Smuzhiyun case HW_PORT2:
1553*4882a593Smuzhiyun val8 = BIT_CLI1_EN_BCN_FUNCTION_8822C;
1554*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI1_EN_RXBCN_RPT_8822C);
1555*4882a593Smuzhiyun break;
1556*4882a593Smuzhiyun case HW_PORT3:
1557*4882a593Smuzhiyun val8 = BIT_CLI2_EN_BCN_FUNCTION_8822C;
1558*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI2_EN_RXBCN_RPT_8822C);
1559*4882a593Smuzhiyun break;
1560*4882a593Smuzhiyun case HW_PORT4:
1561*4882a593Smuzhiyun val8 = BIT_CLI3_EN_BCN_FUNCTION_8822C;
1562*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), BIT_CLI3_EN_RXBCN_RPT_8822C);
1563*4882a593Smuzhiyun break;
1564*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */
1565*4882a593Smuzhiyun default:
1566*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" Unknow hw port(%d) \n", FUNC_ADPT_ARG(adapter), adapter->hw_port);
1567*4882a593Smuzhiyun rtw_warn_on(1);
1568*4882a593Smuzhiyun break;
1569*4882a593Smuzhiyun
1570*4882a593Smuzhiyun }
1571*4882a593Smuzhiyun hw_bcn_ctrl_add(adapter, get_hw_port(adapter), val8);
1572*4882a593Smuzhiyun } else {
1573*4882a593Smuzhiyun
1574*4882a593Smuzhiyun switch (adapter->hw_port) {
1575*4882a593Smuzhiyun case HW_PORT0:
1576*4882a593Smuzhiyun val8 = BIT_EN_BCN_FUNCTION_8822C | BIT_P0_EN_TXBCN_RPT_8822C;
1577*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
1578*4882a593Smuzhiyun /* Always enable port0 beacon function for PSTDMA */
1579*4882a593Smuzhiyun if (GET_HAL_DATA(adapter)->EEPROMBluetoothCoexist)
1580*4882a593Smuzhiyun val8 = BIT_P0_EN_TXBCN_RPT_8822C;
1581*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
1582*4882a593Smuzhiyun break;
1583*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1584*4882a593Smuzhiyun case HW_PORT1:
1585*4882a593Smuzhiyun val8 = BIT_CLI0_EN_BCN_FUNCTION_8822C;
1586*4882a593Smuzhiyun break;
1587*4882a593Smuzhiyun case HW_PORT2:
1588*4882a593Smuzhiyun val8 = BIT_CLI1_EN_BCN_FUNCTION_8822C;
1589*4882a593Smuzhiyun break;
1590*4882a593Smuzhiyun case HW_PORT3:
1591*4882a593Smuzhiyun val8 = BIT_CLI2_EN_BCN_FUNCTION_8822C;
1592*4882a593Smuzhiyun break;
1593*4882a593Smuzhiyun case HW_PORT4:
1594*4882a593Smuzhiyun val8 = BIT_CLI3_EN_BCN_FUNCTION_8822C;
1595*4882a593Smuzhiyun break;
1596*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */
1597*4882a593Smuzhiyun default:
1598*4882a593Smuzhiyun RTW_ERR(FUNC_ADPT_FMT" Unknow hw port(%d) \n", FUNC_ADPT_ARG(adapter), adapter->hw_port);
1599*4882a593Smuzhiyun rtw_warn_on(1);
1600*4882a593Smuzhiyun break;
1601*4882a593Smuzhiyun }
1602*4882a593Smuzhiyun
1603*4882a593Smuzhiyun hw_bcn_ctrl_clr(adapter, get_hw_port(adapter), val8);
1604*4882a593Smuzhiyun }
1605*4882a593Smuzhiyun }
1606*4882a593Smuzhiyun
hw_var_set_mlme_disconnect(PADAPTER adapter)1607*4882a593Smuzhiyun static void hw_var_set_mlme_disconnect(PADAPTER adapter)
1608*4882a593Smuzhiyun {
1609*4882a593Smuzhiyun u8 val8;
1610*4882a593Smuzhiyun struct mi_state mstate;
1611*4882a593Smuzhiyun
1612*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1613*4882a593Smuzhiyun if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
1614*4882a593Smuzhiyun #endif
1615*4882a593Smuzhiyun /* reject all data frames under not link state */
1616*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0);
1617*4882a593Smuzhiyun
1618*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1619*4882a593Smuzhiyun if (adapter->hw_port == HW_PORT1) {
1620*4882a593Smuzhiyun /* reset TSF1(CLINT0) */
1621*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_CLI0_RST_8822C);
1622*4882a593Smuzhiyun
1623*4882a593Smuzhiyun /* disable update TSF1(CLINT0) */
1624*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun /* disable Port1's beacon function */
1627*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_BCN_CTRL_CLINT0_8822C);
1628*4882a593Smuzhiyun val8 &= ~BIT_CLI0_EN_BCN_FUNCTION_8822C;
1629*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_CLINT0_8822C, val8);
1630*4882a593Smuzhiyun } else
1631*4882a593Smuzhiyun #endif
1632*4882a593Smuzhiyun {
1633*4882a593Smuzhiyun /* reset TSF */
1634*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C);
1635*4882a593Smuzhiyun
1636*4882a593Smuzhiyun /* disable update TSF */
1637*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1638*4882a593Smuzhiyun }
1639*4882a593Smuzhiyun
1640*4882a593Smuzhiyun rtw_mi_status_no_self(adapter, &mstate);
1641*4882a593Smuzhiyun
1642*4882a593Smuzhiyun /* clear update TSF only BSSID match for no linked station */
1643*4882a593Smuzhiyun if (MSTATE_STA_LD_NUM(&mstate) == 0 && MSTATE_STA_LG_NUM(&mstate) == 0)
1644*4882a593Smuzhiyun rtl8822c_rx_tsf_addr_filter_config(adapter, 0);
1645*4882a593Smuzhiyun
1646*4882a593Smuzhiyun #ifdef CONFIG_CLIENT_PORT_CFG
1647*4882a593Smuzhiyun if (MLME_IS_STA(adapter))
1648*4882a593Smuzhiyun rtw_hw_client_port_clr(adapter);
1649*4882a593Smuzhiyun #endif
1650*4882a593Smuzhiyun
1651*4882a593Smuzhiyun }
1652*4882a593Smuzhiyun
hw_var_set_mlme_sitesurvey(PADAPTER adapter,u8 enable)1653*4882a593Smuzhiyun static void hw_var_set_mlme_sitesurvey(PADAPTER adapter, u8 enable)
1654*4882a593Smuzhiyun {
1655*4882a593Smuzhiyun struct dvobj_priv *dvobj;
1656*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
1657*4882a593Smuzhiyun struct mlme_priv *pmlmepriv;
1658*4882a593Smuzhiyun PADAPTER iface;
1659*4882a593Smuzhiyun u32 reg_bcn_ctl;
1660*4882a593Smuzhiyun u16 value_rxfltmap2;
1661*4882a593Smuzhiyun u8 val8, i;
1662*4882a593Smuzhiyun
1663*4882a593Smuzhiyun
1664*4882a593Smuzhiyun dvobj = adapter_to_dvobj(adapter);
1665*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
1666*4882a593Smuzhiyun pmlmepriv = &adapter->mlmepriv;
1667*4882a593Smuzhiyun
1668*4882a593Smuzhiyun #ifdef CONFIG_FIND_BEST_CHANNEL
1669*4882a593Smuzhiyun /* Receive all data frames */
1670*4882a593Smuzhiyun value_rxfltmap2 = 0xFFFF;
1671*4882a593Smuzhiyun #else
1672*4882a593Smuzhiyun /* not to receive data frame */
1673*4882a593Smuzhiyun value_rxfltmap2 = 0;
1674*4882a593Smuzhiyun #endif
1675*4882a593Smuzhiyun
1676*4882a593Smuzhiyun if (enable) {
1677*4882a593Smuzhiyun /*
1678*4882a593Smuzhiyun * 1. configure REG_RXFLTMAP2
1679*4882a593Smuzhiyun * 2. config RCR to receive different BSSID BCN or probe rsp
1680*4882a593Smuzhiyun */
1681*4882a593Smuzhiyun
1682*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, value_rxfltmap2);
1683*4882a593Smuzhiyun
1684*4882a593Smuzhiyun rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_ENTER);
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
1687*4882a593Smuzhiyun StopTxBeacon(adapter);
1688*4882a593Smuzhiyun } else {
1689*4882a593Smuzhiyun /* sitesurvey done
1690*4882a593Smuzhiyun * 1. enable rx data frame
1691*4882a593Smuzhiyun * 2. config RCR not to receive different BSSID BCN or probe rsp
1692*4882a593Smuzhiyun */
1693*4882a593Smuzhiyun
1694*4882a593Smuzhiyun if (rtw_mi_check_fwstate(adapter, WIFI_ASOC_STATE | WIFI_AP_STATE | WIFI_MESH_STATE))
1695*4882a593Smuzhiyun /* enable to rx data frame */
1696*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);
1697*4882a593Smuzhiyun
1698*4882a593Smuzhiyun rtw_hal_rcr_set_chk_bssid(adapter, MLME_SCAN_DONE);
1699*4882a593Smuzhiyun
1700*4882a593Smuzhiyun #ifdef CONFIG_AP_MODE
1701*4882a593Smuzhiyun if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
1702*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1703*4882a593Smuzhiyun rtw_mi_tx_beacon_hdl(adapter);
1704*4882a593Smuzhiyun }
1705*4882a593Smuzhiyun #endif
1706*4882a593Smuzhiyun }
1707*4882a593Smuzhiyun }
1708*4882a593Smuzhiyun
hw_var_set_mlme_join(PADAPTER adapter,u8 type)1709*4882a593Smuzhiyun static void hw_var_set_mlme_join(PADAPTER adapter, u8 type)
1710*4882a593Smuzhiyun {
1711*4882a593Smuzhiyun u8 val8;
1712*4882a593Smuzhiyun u16 val16;
1713*4882a593Smuzhiyun u32 val32;
1714*4882a593Smuzhiyun u8 RetryLimit;
1715*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
1716*4882a593Smuzhiyun struct mlme_priv *pmlmepriv;
1717*4882a593Smuzhiyun
1718*4882a593Smuzhiyun RetryLimit = RL_VAL_STA;
1719*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
1720*4882a593Smuzhiyun pmlmepriv = &adapter->mlmepriv;
1721*4882a593Smuzhiyun
1722*4882a593Smuzhiyun
1723*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
1724*4882a593Smuzhiyun if (type == 0) {
1725*4882a593Smuzhiyun /* prepare to join */
1726*4882a593Smuzhiyun if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter))
1727*4882a593Smuzhiyun StopTxBeacon(adapter);
1728*4882a593Smuzhiyun
1729*4882a593Smuzhiyun /* enable to rx data frame.Accept all data frame */
1730*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
1733*4882a593Smuzhiyun RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
1734*4882a593Smuzhiyun else /* Ad-hoc Mode */
1735*4882a593Smuzhiyun RetryLimit = RL_VAL_AP;
1736*4882a593Smuzhiyun
1737*4882a593Smuzhiyun /*
1738*4882a593Smuzhiyun * for 8822C, must enable BCN function if BIT_CBSSID_BCN_8822C(bit 7) of REG_RCR(0x608) is enable to recv BSSID bcn
1739*4882a593Smuzhiyun */
1740*4882a593Smuzhiyun hw_var_set_bcn_func(adapter, _TRUE);
1741*4882a593Smuzhiyun
1742*4882a593Smuzhiyun /* update TSF only BSSID match for station mode */
1743*4882a593Smuzhiyun rtl8822c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822C | BIT_CHK_TSF_CBSSID_8822C);
1744*4882a593Smuzhiyun #ifdef CONFIG_CLIENT_PORT_CFG
1745*4882a593Smuzhiyun rtw_hw_client_port_cfg(adapter);
1746*4882a593Smuzhiyun #endif
1747*4882a593Smuzhiyun
1748*4882a593Smuzhiyun rtw_iface_enable_tsf_update(adapter);
1749*4882a593Smuzhiyun
1750*4882a593Smuzhiyun } else if (type == 1) {
1751*4882a593Smuzhiyun /* joinbss_event call back when join res < 0 */
1752*4882a593Smuzhiyun if (rtw_mi_check_status(adapter, MI_LINKED) == _FALSE)
1753*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0x00);
1754*4882a593Smuzhiyun
1755*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1756*4882a593Smuzhiyun
1757*4882a593Smuzhiyun if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
1758*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1759*4882a593Smuzhiyun
1760*4882a593Smuzhiyun /* reset TSF 1/2 after resume_tx_beacon */
1761*4882a593Smuzhiyun val8 = BIT_TSFTR_RST_8822C | BIT_TSFTR_CLI0_RST_8822C;
1762*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, val8);
1763*4882a593Smuzhiyun }
1764*4882a593Smuzhiyun #ifdef CONFIG_CLIENT_PORT_CFG
1765*4882a593Smuzhiyun if (MLME_IS_STA(adapter))
1766*4882a593Smuzhiyun rtw_hw_client_port_clr(adapter);
1767*4882a593Smuzhiyun #endif
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun } else if (type == 2) {
1770*4882a593Smuzhiyun /* sta add event callback */
1771*4882a593Smuzhiyun if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
1772*4882a593Smuzhiyun rtw_write8(adapter, 0x542, 0x02);
1773*4882a593Smuzhiyun RetryLimit = RL_VAL_AP;
1774*4882a593Smuzhiyun }
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun if (rtw_mi_get_ap_num(adapter) || rtw_mi_get_mesh_num(adapter)) {
1777*4882a593Smuzhiyun ResumeTxBeacon(adapter);
1778*4882a593Smuzhiyun
1779*4882a593Smuzhiyun /* reset TSF 1/2 after resume_tx_beacon */
1780*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST_8822C, BIT_TSFTR_RST_8822C | BIT_TSFTR_CLI0_RST_8822C);
1781*4882a593Smuzhiyun }
1782*4882a593Smuzhiyun }
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun val16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);
1785*4882a593Smuzhiyun rtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);
1786*4882a593Smuzhiyun #else /* !CONFIG_CONCURRENT_MODE */
1787*4882a593Smuzhiyun if (type == 0) {
1788*4882a593Smuzhiyun /* prepare to join */
1789*4882a593Smuzhiyun
1790*4882a593Smuzhiyun /* enable to rx data frame. Accept all data frame */
1791*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0xFFFF);
1792*4882a593Smuzhiyun
1793*4882a593Smuzhiyun /*
1794*4882a593Smuzhiyun * for 8822C, must enable BCN function if BIT_CBSSID_BCN_8822C(bit 7) of REG_RCR(0x608) is enabled to recv BSSID bcn
1795*4882a593Smuzhiyun */
1796*4882a593Smuzhiyun hw_var_set_bcn_func(adapter, _TRUE);
1797*4882a593Smuzhiyun
1798*4882a593Smuzhiyun /* update TSF only BSSID match for station mode */
1799*4882a593Smuzhiyun rtl8822c_rx_tsf_addr_filter_config(adapter, BIT_CHK_TSF_EN_8822C | BIT_CHK_TSF_CBSSID_8822C);
1800*4882a593Smuzhiyun
1801*4882a593Smuzhiyun if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)
1802*4882a593Smuzhiyun RetryLimit = (hal->CustomerID == RT_CID_CCX) ? RL_VAL_AP : RL_VAL_STA;
1803*4882a593Smuzhiyun else /* Ad-hoc Mode */
1804*4882a593Smuzhiyun RetryLimit = RL_VAL_AP;
1805*4882a593Smuzhiyun
1806*4882a593Smuzhiyun rtw_iface_enable_tsf_update(adapter);
1807*4882a593Smuzhiyun
1808*4882a593Smuzhiyun } else if (type == 1) {
1809*4882a593Smuzhiyun /* joinbss_event call back when join res < 0 */
1810*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2_8822C, 0x00);
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun rtw_iface_disable_tsf_update(adapter);
1813*4882a593Smuzhiyun
1814*4882a593Smuzhiyun } else if (type == 2) {
1815*4882a593Smuzhiyun /* sta add event callback */
1816*4882a593Smuzhiyun if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE))
1817*4882a593Smuzhiyun RetryLimit = RL_VAL_AP;
1818*4882a593Smuzhiyun }
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun val16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);
1821*4882a593Smuzhiyun rtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);
1822*4882a593Smuzhiyun #endif /* !CONFIG_CONCURRENT_MODE */
1823*4882a593Smuzhiyun }
1824*4882a593Smuzhiyun
hw_var_set_acm_ctrl(PADAPTER adapter,u8 ctrl)1825*4882a593Smuzhiyun static void hw_var_set_acm_ctrl(PADAPTER adapter, u8 ctrl)
1826*4882a593Smuzhiyun {
1827*4882a593Smuzhiyun u8 hwctrl = 0;
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun if (ctrl) {
1830*4882a593Smuzhiyun hwctrl |= BIT_ACMHWEN_8822C;
1831*4882a593Smuzhiyun
1832*4882a593Smuzhiyun if (ctrl & BIT(1)) /* BE */
1833*4882a593Smuzhiyun hwctrl |= BIT_BEQ_ACM_EN_8822C;
1834*4882a593Smuzhiyun else
1835*4882a593Smuzhiyun hwctrl &= (~BIT_BEQ_ACM_EN_8822C);
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun if (ctrl & BIT(2)) /* VI */
1838*4882a593Smuzhiyun hwctrl |= BIT_VIQ_ACM_EN_8822C;
1839*4882a593Smuzhiyun else
1840*4882a593Smuzhiyun hwctrl &= (~BIT_VIQ_ACM_EN_8822C);
1841*4882a593Smuzhiyun
1842*4882a593Smuzhiyun if (ctrl & BIT(3)) /* VO */
1843*4882a593Smuzhiyun hwctrl |= BIT_VOQ_ACM_EN_8822C;
1844*4882a593Smuzhiyun else
1845*4882a593Smuzhiyun hwctrl &= (~BIT_VOQ_ACM_EN_8822C);
1846*4882a593Smuzhiyun }
1847*4882a593Smuzhiyun
1848*4882a593Smuzhiyun RTW_INFO("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl);
1849*4882a593Smuzhiyun rtw_write8(adapter, REG_ACMHWCTRL_8822C, hwctrl);
1850*4882a593Smuzhiyun }
1851*4882a593Smuzhiyun
hw_var_lps_rfon_chk(_adapter * adapter,u8 rfon_ctrl)1852*4882a593Smuzhiyun void hw_var_lps_rfon_chk(_adapter *adapter, u8 rfon_ctrl)
1853*4882a593Smuzhiyun {
1854*4882a593Smuzhiyun #ifdef CONFIG_LPS_ACK
1855*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun if (rfon_ctrl == rf_on) {
1858*4882a593Smuzhiyun if (rtw_sctx_wait(&pwrpriv->lps_ack_sctx, __func__)) {
1859*4882a593Smuzhiyun if (pwrpriv->lps_ack_status > 0)
1860*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT" RF_ON function is not ready !!!\n", FUNC_ADPT_ARG(adapter));
1861*4882a593Smuzhiyun } else {
1862*4882a593Smuzhiyun RTW_WARN("LPS RFON sctx query timeout, operation abort!!\n");
1863*4882a593Smuzhiyun }
1864*4882a593Smuzhiyun pwrpriv->lps_ack_status = -1;
1865*4882a593Smuzhiyun }
1866*4882a593Smuzhiyun #endif
1867*4882a593Smuzhiyun }
1868*4882a593Smuzhiyun
hw_var_set_sec_dk_cfg(PADAPTER adapter,u8 enable)1869*4882a593Smuzhiyun static void hw_var_set_sec_dk_cfg(PADAPTER adapter, u8 enable)
1870*4882a593Smuzhiyun {
1871*4882a593Smuzhiyun struct security_priv *sec = &adapter->securitypriv;
1872*4882a593Smuzhiyun u8 reg_scr = rtw_read8(adapter, REG_SECCFG_8822C);
1873*4882a593Smuzhiyun
1874*4882a593Smuzhiyun if (enable) {
1875*4882a593Smuzhiyun /* Enable default key related setting */
1876*4882a593Smuzhiyun reg_scr |= BIT_TXBCUSEDK_8822C;
1877*4882a593Smuzhiyun if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1878*4882a593Smuzhiyun reg_scr |= BIT_RXUHUSEDK_8822C | BIT_TXUHUSEDK_8822C;
1879*4882a593Smuzhiyun } else {
1880*4882a593Smuzhiyun /* Disable default key related setting */
1881*4882a593Smuzhiyun reg_scr &= ~(BIT_RXBCUSEDK_8822C | BIT_TXBCUSEDK_8822C | BIT_RXUHUSEDK_8822C | BIT_TXUHUSEDK_8822C);
1882*4882a593Smuzhiyun }
1883*4882a593Smuzhiyun
1884*4882a593Smuzhiyun rtw_write8(adapter, REG_SECCFG_8822C, reg_scr);
1885*4882a593Smuzhiyun
1886*4882a593Smuzhiyun RTW_INFO("%s: [HW_VAR_SEC_DK_CFG] 0x%x=0x%08x\n", __FUNCTION__,
1887*4882a593Smuzhiyun REG_SECCFG_8822C, rtw_read32(adapter, REG_SECCFG_8822C));
1888*4882a593Smuzhiyun }
1889*4882a593Smuzhiyun
hw_var_set_bcn_valid(PADAPTER adapter)1890*4882a593Smuzhiyun static void hw_var_set_bcn_valid(PADAPTER adapter)
1891*4882a593Smuzhiyun {
1892*4882a593Smuzhiyun u8 val8 = 0;
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun /* only port 0 can TX BCN */
1895*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1);
1896*4882a593Smuzhiyun val8 = val8 | BIT(7);
1897*4882a593Smuzhiyun rtw_write8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1, val8);
1898*4882a593Smuzhiyun }
1899*4882a593Smuzhiyun
hw_var_set_ack_preamble(PADAPTER adapter,u8 bShortPreamble)1900*4882a593Smuzhiyun static void hw_var_set_ack_preamble(PADAPTER adapter, u8 bShortPreamble)
1901*4882a593Smuzhiyun {
1902*4882a593Smuzhiyun u8 val8 = 0;
1903*4882a593Smuzhiyun
1904*4882a593Smuzhiyun
1905*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_WMAC_TRXPTCL_CTL_8822C + 2);
1906*4882a593Smuzhiyun val8 |= BIT(4) | BIT(5);
1907*4882a593Smuzhiyun
1908*4882a593Smuzhiyun if (bShortPreamble)
1909*4882a593Smuzhiyun val8 |= BIT1;
1910*4882a593Smuzhiyun else
1911*4882a593Smuzhiyun val8 &= (~BIT1);
1912*4882a593Smuzhiyun
1913*4882a593Smuzhiyun rtw_write8(adapter, REG_WMAC_TRXPTCL_CTL_8822C + 2, val8);
1914*4882a593Smuzhiyun }
1915*4882a593Smuzhiyun
hw_var_set_dl_rsvd_page(PADAPTER adapter,u8 mstatus)1916*4882a593Smuzhiyun void hw_var_set_dl_rsvd_page(PADAPTER adapter, u8 mstatus)
1917*4882a593Smuzhiyun {
1918*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
1919*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
1920*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1921*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
1922*4882a593Smuzhiyun u8 bcn_valid = _FALSE;
1923*4882a593Smuzhiyun u8 DLBcnCount = 0;
1924*4882a593Smuzhiyun u32 poll = 0;
1925*4882a593Smuzhiyun u8 val8;
1926*4882a593Smuzhiyun u8 restore[3];
1927*4882a593Smuzhiyun u8 hw_port = rtw_hal_get_port(adapter);
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ":+ hw_port=%d mstatus(%x)\n",
1930*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), hw_port, mstatus);
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun if (mstatus == RT_MEDIA_CONNECT) {
1933*4882a593Smuzhiyun #if 0
1934*4882a593Smuzhiyun u8 bRecover = _FALSE;
1935*4882a593Smuzhiyun #endif
1936*4882a593Smuzhiyun u8 v8;
1937*4882a593Smuzhiyun
1938*4882a593Smuzhiyun /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 8822C. */
1939*4882a593Smuzhiyun rtw_write16(adapter, port_cfg[hw_port].ps_aid, (0xF800 | pmlmeinfo->aid));
1940*4882a593Smuzhiyun
1941*4882a593Smuzhiyun /* Enable SW TX beacon */
1942*4882a593Smuzhiyun v8 = rtw_read8(adapter, REG_CR_8822C + 1);
1943*4882a593Smuzhiyun restore[0] = v8;
1944*4882a593Smuzhiyun v8 |= (BIT_ENSWBCN_8822C >> 8);
1945*4882a593Smuzhiyun rtw_write8(adapter, REG_CR_8822C + 1, v8);
1946*4882a593Smuzhiyun
1947*4882a593Smuzhiyun /*
1948*4882a593Smuzhiyun * Disable Hw protection for a time which revserd for Hw sending beacon.
1949*4882a593Smuzhiyun * Fix download reserved page packet fail that access collision with the protection time.
1950*4882a593Smuzhiyun */
1951*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_BCN_CTRL_8822C);
1952*4882a593Smuzhiyun restore[1] = val8;
1953*4882a593Smuzhiyun /* val8 &= ~BIT_EN_BCN_FUNCTION_8822C; */
1954*4882a593Smuzhiyun restore[2] = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2);
1955*4882a593Smuzhiyun if (restore[2] & BIT(6)) {
1956*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2,
1957*4882a593Smuzhiyun (restore[2] & ~BIT(6)));
1958*4882a593Smuzhiyun }
1959*4882a593Smuzhiyun val8 |= BIT_DIS_TSF_UDT_8822C;
1960*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_8822C, val8);
1961*4882a593Smuzhiyun
1962*4882a593Smuzhiyun #if 0
1963*4882a593Smuzhiyun /* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
1964*4882a593Smuzhiyun RegFwHwTxQCtrl = rtw_read8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2);
1965*4882a593Smuzhiyun
1966*4882a593Smuzhiyun if (RegFwHwTxQCtrl & BIT(6))
1967*4882a593Smuzhiyun bRecover = _TRUE;
1968*4882a593Smuzhiyun
1969*4882a593Smuzhiyun /* To tell Hw the packet is not a real beacon frame. */
1970*4882a593Smuzhiyun RegFwHwTxQCtrl &= ~BIT(6);
1971*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2, RegFwHwTxQCtrl);
1972*4882a593Smuzhiyun #endif
1973*4882a593Smuzhiyun
1974*4882a593Smuzhiyun /* Clear beacon valid check bit. */
1975*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_BCN_VALID, NULL);
1976*4882a593Smuzhiyun rtw_hal_set_hwreg(adapter, HW_VAR_DL_BCN_SEL, NULL);
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun DLBcnCount = 0;
1979*4882a593Smuzhiyun poll = 0;
1980*4882a593Smuzhiyun do {
1981*4882a593Smuzhiyun /* download rsvd page. */
1982*4882a593Smuzhiyun rtw_hal_set_fw_rsvd_page(adapter, _FALSE);
1983*4882a593Smuzhiyun DLBcnCount++;
1984*4882a593Smuzhiyun do {
1985*4882a593Smuzhiyun rtw_yield_os();
1986*4882a593Smuzhiyun
1987*4882a593Smuzhiyun /* check rsvd page download OK. */
1988*4882a593Smuzhiyun rtw_hal_get_hwreg(adapter, HW_VAR_BCN_VALID, (u8 *)&bcn_valid);
1989*4882a593Smuzhiyun poll++;
1990*4882a593Smuzhiyun } while (!bcn_valid && (poll % 10) != 0 && !RTW_CANNOT_RUN(adapter));
1991*4882a593Smuzhiyun
1992*4882a593Smuzhiyun } while (!bcn_valid && DLBcnCount <= 100 && !RTW_CANNOT_RUN(adapter));
1993*4882a593Smuzhiyun
1994*4882a593Smuzhiyun if (RTW_CANNOT_RUN(adapter))
1995*4882a593Smuzhiyun ;
1996*4882a593Smuzhiyun else if (!bcn_valid)
1997*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
1998*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), DLBcnCount, poll);
1999*4882a593Smuzhiyun else {
2000*4882a593Smuzhiyun struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(adapter);
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun pwrctl->fw_psmode_iface_id = adapter->iface_id;
2003*4882a593Smuzhiyun rtw_hal_set_fw_rsvd_page(adapter, _TRUE);
2004*4882a593Smuzhiyun RTW_INFO(ADPT_FMT ": DL RSVD page success! DLBcnCount:%u, poll:%u\n",
2005*4882a593Smuzhiyun ADPT_ARG(adapter), DLBcnCount, poll);
2006*4882a593Smuzhiyun }
2007*4882a593Smuzhiyun
2008*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2, restore[2]);
2009*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL, restore[1]);
2010*4882a593Smuzhiyun rtw_write8(adapter, REG_CR + 1, restore[0]);
2011*4882a593Smuzhiyun #if 0
2012*4882a593Smuzhiyun /*
2013*4882a593Smuzhiyun * To make sure that if there exists an adapter which would like to send beacon.
2014*4882a593Smuzhiyun * If exists, the origianl value of 0x422[6] will be 1, we should check this to
2015*4882a593Smuzhiyun * prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
2016*4882a593Smuzhiyun * the beacon cannot be sent by HW.
2017*4882a593Smuzhiyun */
2018*4882a593Smuzhiyun if (bRecover) {
2019*4882a593Smuzhiyun RegFwHwTxQCtrl |= BIT(6);
2020*4882a593Smuzhiyun rtw_write8(adapter, REG_FWHW_TXQ_CTRL_8822C + 2, RegFwHwTxQCtrl);
2021*4882a593Smuzhiyun }
2022*4882a593Smuzhiyun #endif
2023*4882a593Smuzhiyun #ifndef CONFIG_PCI_HCI
2024*4882a593Smuzhiyun /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
2025*4882a593Smuzhiyun v8 = rtw_read8(adapter, REG_CR_8822C + 1);
2026*4882a593Smuzhiyun v8 &= ~BIT(0); /* ~ENSWBCN */
2027*4882a593Smuzhiyun rtw_write8(adapter, REG_CR_8822C + 1, v8);
2028*4882a593Smuzhiyun #endif /* !CONFIG_PCI_HCI */
2029*4882a593Smuzhiyun }
2030*4882a593Smuzhiyun }
2031*4882a593Smuzhiyun
hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter,u8 mstatus)2032*4882a593Smuzhiyun static void hw_var_set_h2c_fw_joinbssrpt(PADAPTER adapter, u8 mstatus)
2033*4882a593Smuzhiyun {
2034*4882a593Smuzhiyun if (mstatus == RT_MEDIA_CONNECT)
2035*4882a593Smuzhiyun hw_var_set_dl_rsvd_page(adapter, RT_MEDIA_CONNECT);
2036*4882a593Smuzhiyun }
2037*4882a593Smuzhiyun
2038*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
hw_var_vendor_wow_mode(_adapter * adapter,u8 en)2039*4882a593Smuzhiyun static void hw_var_vendor_wow_mode(_adapter *adapter, u8 en)
2040*4882a593Smuzhiyun {
2041*4882a593Smuzhiyun #ifdef CONFIG_CONCURRENT_MODE
2042*4882a593Smuzhiyun _adapter *iface = NULL;
2043*4882a593Smuzhiyun struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
2044*4882a593Smuzhiyun struct mlme_priv *pmlmepriv = &adapter->mlmepriv;
2045*4882a593Smuzhiyun u8 igi = 0, mac_addr[ETH_ALEN];
2046*4882a593Smuzhiyun
2047*4882a593Smuzhiyun RTW_INFO("%s: en(%d)--->\n", __func__, en);
2048*4882a593Smuzhiyun if (en) {
2049*4882a593Smuzhiyun rtw_hal_get_hwreg(adapter, HW_VAR_MAC_ADDR, mac_addr);
2050*4882a593Smuzhiyun /* RTW_INFO("suspend mac addr: "MAC_FMT"\n", MAC_ARG(mac_addr)); */
2051*4882a593Smuzhiyun rtw_halmac_set_bssid(dvobj, HW_PORT4, mac_addr);
2052*4882a593Smuzhiyun dvobj->rxfltmap2_bf_suspend = rtw_read16(adapter, REG_RXFLTMAP2);
2053*4882a593Smuzhiyun dvobj->bcn_ctrl_clint3_bf_suspend = rtw_read8(adapter, REG_BCN_CTRL_CLINT3);
2054*4882a593Smuzhiyun dvobj->rcr_bf_suspend = rtw_read32(adapter, REG_RCR);
2055*4882a593Smuzhiyun dvobj->cr_ext_bf_suspend = rtw_read32(adapter, REG_CR_EXT);
2056*4882a593Smuzhiyun /*RTW_INFO("RCR: 0x%02x, REG_CR_EXT: 0x%02x , REG_BCN_CTRL_CLINT3: 0x%02x, REG_RXFLTMAP2:0x%02x, REG_MACID_DROP0_8822B:0x%02x\n"
2057*4882a593Smuzhiyun , rtw_read32(adapter, REG_RCR), rtw_read8(adapter, REG_CR_EXT), rtw_read8(adapter, REG_BCN_CTRL_CLINT3)
2058*4882a593Smuzhiyun , rtw_read32(adapter, REG_RXFLTMAP2), rtw_read8(adapter, REG_MACID_DROP0_8822B)); */
2059*4882a593Smuzhiyun rtw_write32(adapter, REG_RCR, (rtw_read32(adapter, REG_RCR) & (~(RCR_AM))) | RCR_CBSSID_DATA | RCR_CBSSID_BCN);
2060*4882a593Smuzhiyun /* set PORT4 to ad hoc mode to filter not necessary Beacons */
2061*4882a593Smuzhiyun rtw_write8(adapter, REG_CR_EXT, (rtw_read8(adapter, REG_CR_EXT)& (~BIT5)) | BIT4);
2062*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_CLINT3, rtw_read8(adapter, REG_BCN_CTRL_CLINT3) | BIT3);
2063*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2, 0xffff);
2064*4882a593Smuzhiyun /* RTW_INFO("RCR: 0x%02x, REG_CR_EXT: 0x%02x , REG_BCN_CTRL_CLINT3: 0x%02x, REG_RXFLTMAP2:0x%02x, REG_MACID_DROP0_8822B:0x%02x\n"
2065*4882a593Smuzhiyun , rtw_read32(adapter, REG_RCR), rtw_read8(adapter, REG_CR_EXT), rtw_read8(adapter, REG_BCN_CTRL_CLINT3)
2066*4882a593Smuzhiyun , rtw_read32(adapter, REG_RXFLTMAP2), rtw_read8(adapter, REG_MACID_DROP0_8822B)); */
2067*4882a593Smuzhiyun
2068*4882a593Smuzhiyun /* The WRC's RSSI is weak. Set the IGI to lower */
2069*4882a593Smuzhiyun odm_write_dig(adapter_to_phydm(adapter), 0x24);
2070*4882a593Smuzhiyun } else {
2071*4882a593Smuzhiyun /* restore the rcr, port ctrol setting */
2072*4882a593Smuzhiyun rtw_write32(adapter, REG_CR_EXT, dvobj->cr_ext_bf_suspend);
2073*4882a593Smuzhiyun rtw_write32(adapter, REG_RCR, dvobj->rcr_bf_suspend);
2074*4882a593Smuzhiyun rtw_write8(adapter, REG_BCN_CTRL_CLINT3, dvobj->bcn_ctrl_clint3_bf_suspend);
2075*4882a593Smuzhiyun rtw_write16(adapter, REG_RXFLTMAP2, dvobj->rxfltmap2_bf_suspend);
2076*4882a593Smuzhiyun
2077*4882a593Smuzhiyun /* RTW_INFO("RCR: 0x%02x, REG_CR_EXT: 0x%02x , REG_BCN_CTRL_CLINT3: 0x%02x, REG_RXFLTMAP2:0x%02x, REG_MACID_DROP0_8822B:0x%02x\n"
2078*4882a593Smuzhiyun , rtw_read32(adapter, REG_RCR), rtw_read8(adapter, REG_CR_EXT), rtw_read8(adapter, REG_BCN_CTRL_CLINT3)
2079*4882a593Smuzhiyun , rtw_read32(adapter, REG_RXFLTMAP2), rtw_read8(adapter, REG_MACID_DROP0_8822B)); */
2080*4882a593Smuzhiyun }
2081*4882a593Smuzhiyun #endif /* CONFIG_CONCURRENT_MODE */
2082*4882a593Smuzhiyun }
2083*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
2084*4882a593Smuzhiyun
2085*4882a593Smuzhiyun
2086*4882a593Smuzhiyun /*
2087*4882a593Smuzhiyun * Parameters:
2088*4882a593Smuzhiyun * adapter
2089*4882a593Smuzhiyun * enable _TRUE: enable; _FALSE: disable
2090*4882a593Smuzhiyun */
rx_agg_switch(PADAPTER adapter,u8 enable)2091*4882a593Smuzhiyun static u8 rx_agg_switch(PADAPTER adapter, u8 enable)
2092*4882a593Smuzhiyun {
2093*4882a593Smuzhiyun int err;
2094*4882a593Smuzhiyun
2095*4882a593Smuzhiyun err = rtw_halmac_rx_agg_switch(adapter_to_dvobj(adapter), enable);
2096*4882a593Smuzhiyun if (err)
2097*4882a593Smuzhiyun return _FAIL;
2098*4882a593Smuzhiyun
2099*4882a593Smuzhiyun return _SUCCESS;
2100*4882a593Smuzhiyun }
2101*4882a593Smuzhiyun
2102*4882a593Smuzhiyun
2103*4882a593Smuzhiyun #ifdef CONFIG_AP_PORT_SWAP
2104*4882a593Smuzhiyun /*
2105*4882a593Smuzhiyun * Parameters:
2106*4882a593Smuzhiyun * if_ap ap interface
2107*4882a593Smuzhiyun * if_port0 port0 interface
2108*4882a593Smuzhiyun */
2109*4882a593Smuzhiyun
hw_port_reconfig(_adapter * if_ap,_adapter * if_port0)2110*4882a593Smuzhiyun static void hw_port_reconfig(_adapter * if_ap, _adapter *if_port0)
2111*4882a593Smuzhiyun {
2112*4882a593Smuzhiyun struct hal_spec_t *hal_spec = GET_HAL_SPEC(if_port0);
2113*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &if_port0->mlmeextpriv;
2114*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
2115*4882a593Smuzhiyun u32 bssid_offset = 0;
2116*4882a593Smuzhiyun u8 bssid[6] = {0};
2117*4882a593Smuzhiyun u8 vnet_type = 0;
2118*4882a593Smuzhiyun u8 vbcn_ctrl = 0;
2119*4882a593Smuzhiyun u8 i;
2120*4882a593Smuzhiyun u8 port = if_ap->hw_port;
2121*4882a593Smuzhiyun
2122*4882a593Smuzhiyun if (port > (hal_spec->port_num - 1)) {
2123*4882a593Smuzhiyun RTW_INFO("[WARN] "ADPT_FMT"- hw_port : %d,will switch to invalid port-%d\n",
2124*4882a593Smuzhiyun ADPT_ARG(if_port0), if_port0->hw_port, port);
2125*4882a593Smuzhiyun rtw_warn_on(1);
2126*4882a593Smuzhiyun }
2127*4882a593Smuzhiyun
2128*4882a593Smuzhiyun RTW_PRINT(ADPT_FMT" - hw_port : %d,will switch to port-%d\n",
2129*4882a593Smuzhiyun ADPT_ARG(if_port0), if_port0->hw_port, port);
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun /*backup*/
2132*4882a593Smuzhiyun GetHwReg(if_port0, HW_VAR_MEDIA_STATUS, &vnet_type);
2133*4882a593Smuzhiyun vbcn_ctrl = rtw_read8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl);
2134*4882a593Smuzhiyun
2135*4882a593Smuzhiyun if (is_client_associated_to_ap(if_port0)) {
2136*4882a593Smuzhiyun RTW_INFO("port0-iface("ADPT_FMT") is STA mode and linked\n", ADPT_ARG(if_port0));
2137*4882a593Smuzhiyun bssid_offset = port_cfg[if_port0->hw_port].bssid;
2138*4882a593Smuzhiyun for (i = 0; i < 6; i++)
2139*4882a593Smuzhiyun bssid[i] = rtw_read8(if_port0, bssid_offset + i);
2140*4882a593Smuzhiyun }
2141*4882a593Smuzhiyun
2142*4882a593Smuzhiyun /*reconfigure*/
2143*4882a593Smuzhiyun if_port0->hw_port = port;
2144*4882a593Smuzhiyun /* adapter mac addr switch to port mac addr */
2145*4882a593Smuzhiyun rtw_hal_set_hwreg(if_port0, HW_VAR_MAC_ADDR, adapter_mac_addr(if_port0));
2146*4882a593Smuzhiyun Set_MSR(if_port0, vnet_type);
2147*4882a593Smuzhiyun rtw_write8(if_port0, port_cfg[if_port0->hw_port].bcn_ctl, vbcn_ctrl);
2148*4882a593Smuzhiyun
2149*4882a593Smuzhiyun if (is_client_associated_to_ap(if_port0)) {
2150*4882a593Smuzhiyun rtw_hal_set_hwreg(if_port0, HW_VAR_BSSID, bssid);
2151*4882a593Smuzhiyun #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
2152*4882a593Smuzhiyun rtw_set_default_port_id(if_port0);
2153*4882a593Smuzhiyun #endif
2154*4882a593Smuzhiyun }
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun #if defined(CONFIG_BT_COEXIST) && defined(CONFIG_FW_MULTI_PORT_SUPPORT)
2157*4882a593Smuzhiyun if (GET_HAL_DATA(if_port0)->EEPROMBluetoothCoexist == _TRUE)
2158*4882a593Smuzhiyun rtw_hal_set_wifi_btc_port_id_cmd(if_port0);
2159*4882a593Smuzhiyun #endif
2160*4882a593Smuzhiyun
2161*4882a593Smuzhiyun if_ap->hw_port =HW_PORT0;
2162*4882a593Smuzhiyun /* port mac addr switch to adapter mac addr */
2163*4882a593Smuzhiyun rtw_hal_set_hwreg(if_ap, HW_VAR_MAC_ADDR, adapter_mac_addr(if_ap));
2164*4882a593Smuzhiyun }
2165*4882a593Smuzhiyun
hw_var_ap_port_switch(_adapter * adapter,u8 mode)2166*4882a593Smuzhiyun static void hw_var_ap_port_switch(_adapter *adapter, u8 mode)
2167*4882a593Smuzhiyun {
2168*4882a593Smuzhiyun u8 hw_port = get_hw_port(adapter);
2169*4882a593Smuzhiyun struct dvobj_priv *dvobj = adapter_to_dvobj(adapter);
2170*4882a593Smuzhiyun u8 ap_nums = 0;
2171*4882a593Smuzhiyun _adapter *if_port0 = NULL;
2172*4882a593Smuzhiyun int i;
2173*4882a593Smuzhiyun
2174*4882a593Smuzhiyun RTW_INFO(ADPT_FMT ": hw_port(%d) will set mode to %d\n", ADPT_ARG(adapter), hw_port, mode);
2175*4882a593Smuzhiyun #if 0
2176*4882a593Smuzhiyun #ifdef CONFIG_P2P
2177*4882a593Smuzhiyun if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
2178*4882a593Smuzhiyun RTW_INFO("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__,
2179*4882a593Smuzhiyun rtw_p2p_role(&adapter->wdinfo), rtw_p2p_state(&adapter->wdinfo), rtw_p2p_pre_state(&adapter->wdinfo));
2180*4882a593Smuzhiyun }
2181*4882a593Smuzhiyun #endif
2182*4882a593Smuzhiyun #endif
2183*4882a593Smuzhiyun
2184*4882a593Smuzhiyun if (mode != _HW_STATE_AP_)
2185*4882a593Smuzhiyun return;
2186*4882a593Smuzhiyun
2187*4882a593Smuzhiyun if (hw_port == HW_PORT0)
2188*4882a593Smuzhiyun return;
2189*4882a593Smuzhiyun
2190*4882a593Smuzhiyun /*check and prepare switch port to port0 for AP mode's BCN function*/
2191*4882a593Smuzhiyun ap_nums = rtw_mi_get_ap_num(adapter);
2192*4882a593Smuzhiyun if (ap_nums > 0) {
2193*4882a593Smuzhiyun RTW_ERR("SortAP mode numbers:%d, must move setting to MBSSID CAM, not support yet\n", ap_nums);
2194*4882a593Smuzhiyun rtw_warn_on(1);
2195*4882a593Smuzhiyun return;
2196*4882a593Smuzhiyun }
2197*4882a593Smuzhiyun
2198*4882a593Smuzhiyun /*Get iface of port-0*/
2199*4882a593Smuzhiyun for (i = 0; i < dvobj->iface_nums; i++) {
2200*4882a593Smuzhiyun if (get_hw_port(dvobj->padapters[i]) == HW_PORT0) {
2201*4882a593Smuzhiyun if_port0 = dvobj->padapters[i];
2202*4882a593Smuzhiyun break;
2203*4882a593Smuzhiyun }
2204*4882a593Smuzhiyun }
2205*4882a593Smuzhiyun
2206*4882a593Smuzhiyun if (if_port0 == NULL) {
2207*4882a593Smuzhiyun RTW_ERR("%s if_port0 == NULL\n", __func__);
2208*4882a593Smuzhiyun rtw_warn_on(1);
2209*4882a593Smuzhiyun return;
2210*4882a593Smuzhiyun }
2211*4882a593Smuzhiyun /* if_port0 switch to hw_port */
2212*4882a593Smuzhiyun hw_port_reconfig(adapter, if_port0);
2213*4882a593Smuzhiyun RTW_INFO(ADPT_FMT ": Cfg SoftAP mode to hw_port(%d) done\n", ADPT_ARG(adapter), adapter->hw_port);
2214*4882a593Smuzhiyun
2215*4882a593Smuzhiyun }
2216*4882a593Smuzhiyun #endif
2217*4882a593Smuzhiyun
rtl8822c_sethwreg(PADAPTER adapter,u8 variable,u8 * val)2218*4882a593Smuzhiyun u8 rtl8822c_sethwreg(PADAPTER adapter, u8 variable, u8 *val)
2219*4882a593Smuzhiyun {
2220*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
2221*4882a593Smuzhiyun u8 ret = _SUCCESS;
2222*4882a593Smuzhiyun u8 val8;
2223*4882a593Smuzhiyun u16 val16;
2224*4882a593Smuzhiyun u32 val32;
2225*4882a593Smuzhiyun
2226*4882a593Smuzhiyun
2227*4882a593Smuzhiyun switch (variable) {
2228*4882a593Smuzhiyun case HW_VAR_SET_OPMODE:
2229*4882a593Smuzhiyun hw_var_set_opmode(adapter, *val);
2230*4882a593Smuzhiyun break;
2231*4882a593Smuzhiyun /*
2232*4882a593Smuzhiyun case HW_VAR_INIT_RTS_RATE:
2233*4882a593Smuzhiyun break;
2234*4882a593Smuzhiyun */
2235*4882a593Smuzhiyun case HW_VAR_BASIC_RATE:
2236*4882a593Smuzhiyun rtw_var_set_basic_rate(adapter, val);
2237*4882a593Smuzhiyun break;
2238*4882a593Smuzhiyun
2239*4882a593Smuzhiyun case HW_VAR_TXPAUSE:
2240*4882a593Smuzhiyun rtw_write8(adapter, REG_TXPAUSE_8822C, *val);
2241*4882a593Smuzhiyun break;
2242*4882a593Smuzhiyun
2243*4882a593Smuzhiyun case HW_VAR_BCN_FUNC:
2244*4882a593Smuzhiyun hw_var_set_bcn_func(adapter, *val);
2245*4882a593Smuzhiyun break;
2246*4882a593Smuzhiyun
2247*4882a593Smuzhiyun case HW_VAR_PORT_CFG:
2248*4882a593Smuzhiyun hw_var_hw_port_cfg(adapter, *val);
2249*4882a593Smuzhiyun break;
2250*4882a593Smuzhiyun
2251*4882a593Smuzhiyun case HW_VAR_MLME_DISCONNECT:
2252*4882a593Smuzhiyun hw_var_set_mlme_disconnect(adapter);
2253*4882a593Smuzhiyun break;
2254*4882a593Smuzhiyun
2255*4882a593Smuzhiyun case HW_VAR_MLME_SITESURVEY:
2256*4882a593Smuzhiyun hw_var_set_mlme_sitesurvey(adapter, *val);
2257*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
2258*4882a593Smuzhiyun if (hal->EEPROMBluetoothCoexist)
2259*4882a593Smuzhiyun rtw_btcoex_ScanNotify(adapter, *val ? _TRUE : _FALSE);
2260*4882a593Smuzhiyun else
2261*4882a593Smuzhiyun #endif /* CONFIG_BT_COEXIST */
2262*4882a593Smuzhiyun rtw_btcoex_wifionly_scan_notify(adapter);
2263*4882a593Smuzhiyun break;
2264*4882a593Smuzhiyun
2265*4882a593Smuzhiyun case HW_VAR_MLME_JOIN:
2266*4882a593Smuzhiyun hw_var_set_mlme_join(adapter, *val);
2267*4882a593Smuzhiyun break;
2268*4882a593Smuzhiyun
2269*4882a593Smuzhiyun case HW_VAR_RCR:
2270*4882a593Smuzhiyun ret = rtl8822c_rcr_config(adapter, *((u32 *)val));
2271*4882a593Smuzhiyun break;
2272*4882a593Smuzhiyun
2273*4882a593Smuzhiyun case HW_VAR_SLOT_TIME:
2274*4882a593Smuzhiyun rtw_write8(adapter, REG_SLOT_8822C, *val);
2275*4882a593Smuzhiyun break;
2276*4882a593Smuzhiyun
2277*4882a593Smuzhiyun case HW_VAR_RESP_SIFS:
2278*4882a593Smuzhiyun /* RESP_SIFS for CCK */
2279*4882a593Smuzhiyun rtw_write8(adapter, REG_RESP_SIFS_CCK_8822C, 0x08);
2280*4882a593Smuzhiyun rtw_write8(adapter, REG_RESP_SIFS_CCK_8822C + 1, 0x08);
2281*4882a593Smuzhiyun /* RESP_SIFS for OFDM */
2282*4882a593Smuzhiyun rtw_write8(adapter, REG_RESP_SIFS_OFDM_8822C, 0x0a);
2283*4882a593Smuzhiyun rtw_write8(adapter, REG_RESP_SIFS_OFDM_8822C + 1, 0x0a);
2284*4882a593Smuzhiyun break;
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun case HW_VAR_ACK_PREAMBLE:
2287*4882a593Smuzhiyun hw_var_set_ack_preamble(adapter, *val);
2288*4882a593Smuzhiyun break;
2289*4882a593Smuzhiyun
2290*4882a593Smuzhiyun /*
2291*4882a593Smuzhiyun case HW_VAR_SEC_CFG:
2292*4882a593Smuzhiyun follow hal_com.c
2293*4882a593Smuzhiyun break;
2294*4882a593Smuzhiyun */
2295*4882a593Smuzhiyun
2296*4882a593Smuzhiyun case HW_VAR_SEC_DK_CFG:
2297*4882a593Smuzhiyun if (val)
2298*4882a593Smuzhiyun hw_var_set_sec_dk_cfg(adapter, _TRUE);
2299*4882a593Smuzhiyun else
2300*4882a593Smuzhiyun hw_var_set_sec_dk_cfg(adapter, _FALSE);
2301*4882a593Smuzhiyun break;
2302*4882a593Smuzhiyun
2303*4882a593Smuzhiyun case HW_VAR_BCN_VALID:
2304*4882a593Smuzhiyun hw_var_set_bcn_valid(adapter);
2305*4882a593Smuzhiyun break;
2306*4882a593Smuzhiyun
2307*4882a593Smuzhiyun case HW_VAR_CAM_INVALID_ALL:
2308*4882a593Smuzhiyun val32 = BIT_SECCAM_POLLING_8822C | BIT_SECCAM_CLR_8822C;
2309*4882a593Smuzhiyun rtw_write32(adapter, REG_CAMCMD_8822C, val32);
2310*4882a593Smuzhiyun break;
2311*4882a593Smuzhiyun
2312*4882a593Smuzhiyun case HW_VAR_AC_PARAM_VO:
2313*4882a593Smuzhiyun rtw_write32(adapter, REG_EDCA_VO_PARAM_8822C, *(u32 *)val);
2314*4882a593Smuzhiyun break;
2315*4882a593Smuzhiyun
2316*4882a593Smuzhiyun case HW_VAR_AC_PARAM_VI:
2317*4882a593Smuzhiyun rtw_write32(adapter, REG_EDCA_VI_PARAM_8822C, *(u32 *)val);
2318*4882a593Smuzhiyun break;
2319*4882a593Smuzhiyun
2320*4882a593Smuzhiyun case HW_VAR_AC_PARAM_BE:
2321*4882a593Smuzhiyun hal->ac_param_be = *(u32 *)val;
2322*4882a593Smuzhiyun rtw_write32(adapter, REG_EDCA_BE_PARAM_8822C, *(u32 *)val);
2323*4882a593Smuzhiyun break;
2324*4882a593Smuzhiyun
2325*4882a593Smuzhiyun case HW_VAR_AC_PARAM_BK:
2326*4882a593Smuzhiyun rtw_write32(adapter, REG_EDCA_BK_PARAM_8822C, *(u32 *)val);
2327*4882a593Smuzhiyun break;
2328*4882a593Smuzhiyun
2329*4882a593Smuzhiyun case HW_VAR_ACM_CTRL:
2330*4882a593Smuzhiyun hw_var_set_acm_ctrl(adapter, *val);
2331*4882a593Smuzhiyun break;
2332*4882a593Smuzhiyun /*
2333*4882a593Smuzhiyun case HW_VAR_AMPDU_MIN_SPACE:
2334*4882a593Smuzhiyun break;
2335*4882a593Smuzhiyun */
2336*4882a593Smuzhiyun #ifdef CONFIG_80211N_HT
2337*4882a593Smuzhiyun case HW_VAR_AMPDU_FACTOR: {
2338*4882a593Smuzhiyun u32 AMPDULen = *val; /* enum AGGRE_SIZE */
2339*4882a593Smuzhiyun
2340*4882a593Smuzhiyun AMPDULen = (0x2000 << AMPDULen) - 1;
2341*4882a593Smuzhiyun rtw_write32(adapter, REG_AMPDU_MAX_LENGTH_HT_8822C, AMPDULen);
2342*4882a593Smuzhiyun }
2343*4882a593Smuzhiyun break;
2344*4882a593Smuzhiyun #endif /* CONFIG_80211N_HT */
2345*4882a593Smuzhiyun case HW_VAR_RXDMA_AGG_PG_TH:
2346*4882a593Smuzhiyun /*
2347*4882a593Smuzhiyun * TH=1 => invalidate RX DMA aggregation
2348*4882a593Smuzhiyun * TH=0 => validate RX DMA aggregation, use init value.
2349*4882a593Smuzhiyun */
2350*4882a593Smuzhiyun if (*val == 0)
2351*4882a593Smuzhiyun /* enable RXDMA aggregation */
2352*4882a593Smuzhiyun rx_agg_switch(adapter, _TRUE);
2353*4882a593Smuzhiyun else
2354*4882a593Smuzhiyun /* disable RXDMA aggregation */
2355*4882a593Smuzhiyun rx_agg_switch(adapter, _FALSE);
2356*4882a593Smuzhiyun break;
2357*4882a593Smuzhiyun /*
2358*4882a593Smuzhiyun case HW_VAR_SET_RPWM:
2359*4882a593Smuzhiyun case HW_VAR_CPWM:
2360*4882a593Smuzhiyun break;
2361*4882a593Smuzhiyun */
2362*4882a593Smuzhiyun case HW_VAR_H2C_FW_PWRMODE:
2363*4882a593Smuzhiyun rtl8822c_set_FwPwrMode_cmd(adapter, *val);
2364*4882a593Smuzhiyun break;
2365*4882a593Smuzhiyun
2366*4882a593Smuzhiyun case HW_VAR_H2C_FW_PWRMODE_RFON_CTRL:
2367*4882a593Smuzhiyun rtl8822c_set_FwPwrMode_rfon_ctrl_cmd(adapter, *val);
2368*4882a593Smuzhiyun break;
2369*4882a593Smuzhiyun
2370*4882a593Smuzhiyun case HW_VAR_LPS_RFON_CHK:
2371*4882a593Smuzhiyun hw_var_lps_rfon_chk(adapter, *val);
2372*4882a593Smuzhiyun break;
2373*4882a593Smuzhiyun /*
2374*4882a593Smuzhiyun case HW_VAR_H2C_PS_TUNE_PARAM:
2375*4882a593Smuzhiyun break;
2376*4882a593Smuzhiyun */
2377*4882a593Smuzhiyun case HW_VAR_H2C_INACTIVE_IPS:
2378*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
2379*4882a593Smuzhiyun rtl8822c_set_fw_pwrmode_inips_cmd_wowlan(adapter, *val);
2380*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
2381*4882a593Smuzhiyun break;
2382*4882a593Smuzhiyun case HW_VAR_H2C_FW_JOINBSSRPT:
2383*4882a593Smuzhiyun hw_var_set_h2c_fw_joinbssrpt(adapter, *val);
2384*4882a593Smuzhiyun break;
2385*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
2386*4882a593Smuzhiyun case HW_VAR_VENDOR_WOW_MODE:
2387*4882a593Smuzhiyun hw_var_vendor_wow_mode(adapter, *(u8 *)val);
2388*4882a593Smuzhiyun break;
2389*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
2390*4882a593Smuzhiyun case HW_VAR_DL_RSVD_PAGE:
2391*4882a593Smuzhiyun #ifdef CONFIG_BT_COEXIST
2392*4882a593Smuzhiyun if (check_fwstate(&adapter->mlmepriv, WIFI_AP_STATE) == _TRUE)
2393*4882a593Smuzhiyun rtl8822c_download_BTCoex_AP_mode_rsvd_page(adapter);
2394*4882a593Smuzhiyun #endif
2395*4882a593Smuzhiyun break;
2396*4882a593Smuzhiyun #ifdef CONFIG_P2P_PS
2397*4882a593Smuzhiyun case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
2398*4882a593Smuzhiyun #ifdef CONFIG_FW_MULTI_PORT_SUPPORT
2399*4882a593Smuzhiyun if (*val == P2P_PS_ENABLE)
2400*4882a593Smuzhiyun rtw_set_default_port_id(adapter);
2401*4882a593Smuzhiyun #endif
2402*4882a593Smuzhiyun rtw_set_p2p_ps_offload_cmd(adapter, *val);
2403*4882a593Smuzhiyun break;
2404*4882a593Smuzhiyun #endif /* CONFIG_P2P_PS */
2405*4882a593Smuzhiyun /*
2406*4882a593Smuzhiyun case HW_VAR_TRIGGER_GPIO_0:
2407*4882a593Smuzhiyun case HW_VAR_BT_SET_COEXIST:
2408*4882a593Smuzhiyun case HW_VAR_BT_ISSUE_DELBA:
2409*4882a593Smuzhiyun case HW_VAR_SWITCH_EPHY_WoWLAN:
2410*4882a593Smuzhiyun case HW_VAR_EFUSE_USAGE:
2411*4882a593Smuzhiyun case HW_VAR_EFUSE_BYTES:
2412*4882a593Smuzhiyun case HW_VAR_EFUSE_BT_USAGE:
2413*4882a593Smuzhiyun case HW_VAR_EFUSE_BT_BYTES:
2414*4882a593Smuzhiyun break;
2415*4882a593Smuzhiyun */
2416*4882a593Smuzhiyun case HW_VAR_FIFO_CLEARN_UP: {
2417*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
2418*4882a593Smuzhiyun u8 trycnt = 100;
2419*4882a593Smuzhiyun u32 reg_hw_ssn;
2420*4882a593Smuzhiyun
2421*4882a593Smuzhiyun /* pause tx */
2422*4882a593Smuzhiyun rtw_write8(adapter, REG_TXPAUSE_8822C, 0xff);
2423*4882a593Smuzhiyun
2424*4882a593Smuzhiyun /* keep hw sn */
2425*4882a593Smuzhiyun if (adapter->xmitpriv.hw_ssn_seq_no == 1)
2426*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ1_8822C;
2427*4882a593Smuzhiyun else if (adapter->xmitpriv.hw_ssn_seq_no == 2)
2428*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ2_8822C;
2429*4882a593Smuzhiyun else if (adapter->xmitpriv.hw_ssn_seq_no == 3)
2430*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ3_8822C;
2431*4882a593Smuzhiyun else
2432*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ0_8822C;
2433*4882a593Smuzhiyun
2434*4882a593Smuzhiyun adapter->xmitpriv.nqos_ssn = rtw_read16(adapter, reg_hw_ssn);
2435*4882a593Smuzhiyun
2436*4882a593Smuzhiyun if (pwrpriv->bkeepfwalive != _TRUE) {
2437*4882a593Smuzhiyun /* RX DMA stop */
2438*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_RXPKT_NUM_8822C);
2439*4882a593Smuzhiyun val32 |= BIT_RW_RELEASE_EN;
2440*4882a593Smuzhiyun rtw_write32(adapter, REG_RXPKT_NUM_8822C, val32);
2441*4882a593Smuzhiyun do {
2442*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_RXPKT_NUM_8822C);
2443*4882a593Smuzhiyun val32 &= BIT_RXDMA_IDLE_8822C;
2444*4882a593Smuzhiyun if (val32)
2445*4882a593Smuzhiyun break;
2446*4882a593Smuzhiyun
2447*4882a593Smuzhiyun RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] val=%x times:%d\n", val32, trycnt);
2448*4882a593Smuzhiyun rtw_yield_os();
2449*4882a593Smuzhiyun } while (--trycnt);
2450*4882a593Smuzhiyun if (trycnt == 0)
2451*4882a593Smuzhiyun RTW_INFO("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed!\n");
2452*4882a593Smuzhiyun #if 0
2453*4882a593Smuzhiyun /* RQPN Load 0 */
2454*4882a593Smuzhiyun rtw_write16(adapter, REG_RQPN_NPQ, 0);
2455*4882a593Smuzhiyun rtw_write32(adapter, REG_RQPN, 0x80000000);
2456*4882a593Smuzhiyun rtw_mdelay_os(2);
2457*4882a593Smuzhiyun #endif
2458*4882a593Smuzhiyun }
2459*4882a593Smuzhiyun }
2460*4882a593Smuzhiyun break;
2461*4882a593Smuzhiyun
2462*4882a593Smuzhiyun case HW_VAR_RESTORE_HW_SEQ:
2463*4882a593Smuzhiyun {
2464*4882a593Smuzhiyun /* restore Sequence No. */
2465*4882a593Smuzhiyun u32 reg_hw_ssn;
2466*4882a593Smuzhiyun
2467*4882a593Smuzhiyun if (adapter->xmitpriv.hw_ssn_seq_no == 1)
2468*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ1_8822C;
2469*4882a593Smuzhiyun else if (adapter->xmitpriv.hw_ssn_seq_no == 2)
2470*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ2_8822C;
2471*4882a593Smuzhiyun else if (adapter->xmitpriv.hw_ssn_seq_no == 3)
2472*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ3_8822C;
2473*4882a593Smuzhiyun else
2474*4882a593Smuzhiyun reg_hw_ssn = REG_HW_SEQ0_8822C;
2475*4882a593Smuzhiyun
2476*4882a593Smuzhiyun rtw_write8(adapter, reg_hw_ssn, adapter->xmitpriv.nqos_ssn);
2477*4882a593Smuzhiyun }
2478*4882a593Smuzhiyun break;
2479*4882a593Smuzhiyun
2480*4882a593Smuzhiyun case HW_VAR_CHECK_TXBUF: {
2481*4882a593Smuzhiyun u16 rtylmtorg;
2482*4882a593Smuzhiyun u8 RetryLimit = 0x01;
2483*4882a593Smuzhiyun systime start;
2484*4882a593Smuzhiyun u32 passtime;
2485*4882a593Smuzhiyun u32 timelmt = 2000; /* ms */
2486*4882a593Smuzhiyun int err;
2487*4882a593Smuzhiyun u8 empty;
2488*4882a593Smuzhiyun
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun rtylmtorg = rtw_read16(adapter, REG_RETRY_LIMIT_8822C);
2491*4882a593Smuzhiyun
2492*4882a593Smuzhiyun val16 = BIT_LRL_8822C(RetryLimit) | BIT_SRL_8822C(RetryLimit);
2493*4882a593Smuzhiyun rtw_write16(adapter, REG_RETRY_LIMIT_8822C, val16);
2494*4882a593Smuzhiyun
2495*4882a593Smuzhiyun /* Check TX FIFO empty or not */
2496*4882a593Smuzhiyun empty = _FALSE;
2497*4882a593Smuzhiyun start = rtw_get_current_time();
2498*4882a593Smuzhiyun err = rtw_halmac_txfifo_wait_empty(adapter_to_dvobj(adapter), timelmt);
2499*4882a593Smuzhiyun if (!err)
2500*4882a593Smuzhiyun empty = _TRUE;
2501*4882a593Smuzhiyun passtime = rtw_get_passing_time_ms(start);
2502*4882a593Smuzhiyun
2503*4882a593Smuzhiyun if (_TRUE == empty)
2504*4882a593Smuzhiyun RTW_INFO("[HW_VAR_CHECK_TXBUF] Empty in %d ms\n", passtime);
2505*4882a593Smuzhiyun else if (RTW_CANNOT_RUN(adapter))
2506*4882a593Smuzhiyun RTW_WARN("[HW_VAR_CHECK_TXBUF] bDriverStopped or bSurpriseRemoved\n");
2507*4882a593Smuzhiyun else {
2508*4882a593Smuzhiyun RTW_ERR("[HW_VAR_CHECK_TXBUF] NOT empty in %d ms\n", passtime);
2509*4882a593Smuzhiyun
2510*4882a593Smuzhiyun }
2511*4882a593Smuzhiyun rtw_write16(adapter, REG_RETRY_LIMIT_8822C, rtylmtorg);
2512*4882a593Smuzhiyun }
2513*4882a593Smuzhiyun break;
2514*4882a593Smuzhiyun /*
2515*4882a593Smuzhiyun case HW_VAR_PCIE_STOP_TX_DMA:
2516*4882a593Smuzhiyun case HW_VAR_APFM_ON_MAC
2517*4882a593Smuzhiyun case HW_VAR_HCI_SUS_STATE:
2518*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2519*4882a593Smuzhiyun case HW_VAR_WOWLAN:
2520*4882a593Smuzhiyun case HW_VAR_WAKEUP_REASON:
2521*4882a593Smuzhiyun #endif
2522*4882a593Smuzhiyun case HW_VAR_RPWM_TOG:
2523*4882a593Smuzhiyun break;
2524*4882a593Smuzhiyun */
2525*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
2526*4882a593Smuzhiyun case HW_SET_GPIO_WL_CTRL: {
2527*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
2528*4882a593Smuzhiyun u8 enable = *val;
2529*4882a593Smuzhiyun u8 value = 0;
2530*4882a593Smuzhiyun u8 addr = REG_PAD_CTRL1_8822C + 3;
2531*4882a593Smuzhiyun
2532*4882a593Smuzhiyun if (pwrpriv->wowlan_gpio_index == 6) {
2533*4882a593Smuzhiyun value = rtw_read8(adapter, addr);
2534*4882a593Smuzhiyun
2535*4882a593Smuzhiyun if (enable == _TRUE && (value & BIT(1)))
2536*4882a593Smuzhiyun /* set 0x64[25] = 0 to control GPIO 6 */
2537*4882a593Smuzhiyun rtw_write8(adapter, addr, value & (~BIT(1)));
2538*4882a593Smuzhiyun else if (enable == _FALSE)
2539*4882a593Smuzhiyun rtw_write8(adapter, addr, value | BIT(1));
2540*4882a593Smuzhiyun
2541*4882a593Smuzhiyun RTW_INFO("[HW_SET_GPIO_WL_CTRL] 0x%02X=0x%02X\n",
2542*4882a593Smuzhiyun addr, rtw_read8(adapter, addr));
2543*4882a593Smuzhiyun }
2544*4882a593Smuzhiyun }
2545*4882a593Smuzhiyun break;
2546*4882a593Smuzhiyun #endif
2547*4882a593Smuzhiyun /*
2548*4882a593Smuzhiyun case HW_VAR_SYS_CLKR:
2549*4882a593Smuzhiyun break;
2550*4882a593Smuzhiyun */
2551*4882a593Smuzhiyun case HW_VAR_NAV_UPPER: {
2552*4882a593Smuzhiyun #define HAL_NAV_UPPER_UNIT 128 /* micro-second */
2553*4882a593Smuzhiyun u32 usNavUpper = *(u32 *)val;
2554*4882a593Smuzhiyun
2555*4882a593Smuzhiyun if (usNavUpper > HAL_NAV_UPPER_UNIT * 0xFF) {
2556*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": [HW_VAR_NAV_UPPER] value(0x%08X us) is larger than (%d * 0xFF)!!!\n",
2557*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), usNavUpper, HAL_NAV_UPPER_UNIT);
2558*4882a593Smuzhiyun break;
2559*4882a593Smuzhiyun }
2560*4882a593Smuzhiyun
2561*4882a593Smuzhiyun usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT - 1) / HAL_NAV_UPPER_UNIT;
2562*4882a593Smuzhiyun rtw_write8(adapter, REG_NAV_CTRL_8822C + 2, (u8)usNavUpper);
2563*4882a593Smuzhiyun }
2564*4882a593Smuzhiyun break;
2565*4882a593Smuzhiyun
2566*4882a593Smuzhiyun /*
2567*4882a593Smuzhiyun case HW_VAR_RPT_TIMER_SETTING:
2568*4882a593Smuzhiyun case HW_VAR_TX_RPT_MAX_MACID:
2569*4882a593Smuzhiyun case HW_VAR_CHK_HI_QUEUE_EMPTY:
2570*4882a593Smuzhiyun case HW_VAR_AMPDU_MAX_TIME:
2571*4882a593Smuzhiyun case HW_VAR_USB_MODE:
2572*4882a593Smuzhiyun break;
2573*4882a593Smuzhiyun */
2574*4882a593Smuzhiyun #ifdef CONFIG_AP_PORT_SWAP
2575*4882a593Smuzhiyun case HW_VAR_PORT_SWITCH:
2576*4882a593Smuzhiyun {
2577*4882a593Smuzhiyun u8 mode = *((u8 *)val);
2578*4882a593Smuzhiyun
2579*4882a593Smuzhiyun hw_var_ap_port_switch(adapter, mode);
2580*4882a593Smuzhiyun }
2581*4882a593Smuzhiyun break;
2582*4882a593Smuzhiyun #endif
2583*4882a593Smuzhiyun
2584*4882a593Smuzhiyun #ifdef CONFIG_BEAMFORMING
2585*4882a593Smuzhiyun case HW_VAR_SOUNDING_ENTER:
2586*4882a593Smuzhiyun rtl8822c_phy_bf_enter(adapter, (struct sta_info*)val);
2587*4882a593Smuzhiyun break;
2588*4882a593Smuzhiyun
2589*4882a593Smuzhiyun case HW_VAR_SOUNDING_LEAVE:
2590*4882a593Smuzhiyun rtl8822c_phy_bf_leave(adapter, val);
2591*4882a593Smuzhiyun break;
2592*4882a593Smuzhiyun /*
2593*4882a593Smuzhiyun case HW_VAR_SOUNDING_RATE:
2594*4882a593Smuzhiyun break;
2595*4882a593Smuzhiyun */
2596*4882a593Smuzhiyun case HW_VAR_SOUNDING_STATUS:
2597*4882a593Smuzhiyun rtl8822c_phy_bf_sounding_status(adapter, *val);
2598*4882a593Smuzhiyun break;
2599*4882a593Smuzhiyun /*
2600*4882a593Smuzhiyun case HW_VAR_SOUNDING_FW_NDPA:
2601*4882a593Smuzhiyun case HW_VAR_SOUNDING_CLK:
2602*4882a593Smuzhiyun break;
2603*4882a593Smuzhiyun */
2604*4882a593Smuzhiyun case HW_VAR_SOUNDING_SET_GID_TABLE:
2605*4882a593Smuzhiyun rtl8822c_phy_bf_set_gid_table(adapter, (struct beamformer_entry*)val);
2606*4882a593Smuzhiyun break;
2607*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */
2608*4882a593Smuzhiyun /*
2609*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_INIT:
2610*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_RESTART:
2611*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_START:
2612*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_STOP:
2613*4882a593Smuzhiyun break;
2614*4882a593Smuzhiyun */
2615*4882a593Smuzhiyun
2616*4882a593Smuzhiyun /*
2617*4882a593Smuzhiyun case HW_VAR_MACID_LINK:
2618*4882a593Smuzhiyun case HW_VAR_MACID_NOLINK:
2619*4882a593Smuzhiyun case HW_VAR_DUMP_MAC_QUEUE_INFO:
2620*4882a593Smuzhiyun case HW_VAR_ASIX_IOT:
2621*4882a593Smuzhiyun case HW_VAR_EN_HW_UPDATE_TSF:
2622*4882a593Smuzhiyun case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
2623*4882a593Smuzhiyun case HW_VAR_CH_SW_IQK_INFO_BACKUP:
2624*4882a593Smuzhiyun case HW_VAR_CH_SW_IQK_INFO_RESTORE:
2625*4882a593Smuzhiyun break;
2626*4882a593Smuzhiyun */
2627*4882a593Smuzhiyun
2628*4882a593Smuzhiyun case HW_VAR_FREECNT:
2629*4882a593Smuzhiyun
2630*4882a593Smuzhiyun val8 = (u8)*val;
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun if (val8==0) {
2633*4882a593Smuzhiyun /* disable free run counter set 0x577[3]=0 */
2634*4882a593Smuzhiyun rtw_write8(adapter, REG_MISC_CTRL,
2635*4882a593Smuzhiyun rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));
2636*4882a593Smuzhiyun
2637*4882a593Smuzhiyun /* reset FREE_RUN_COUNTER set 0x553[5]=1 */
2638*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_DUAL_TSF_RST);
2639*4882a593Smuzhiyun val8 |= BIT_FREECNT_RST;
2640*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST, val8);
2641*4882a593Smuzhiyun
2642*4882a593Smuzhiyun } else if (val8==1){
2643*4882a593Smuzhiyun
2644*4882a593Smuzhiyun /* enable free run counter */
2645*4882a593Smuzhiyun
2646*4882a593Smuzhiyun /* disable first set 0x577[3]=0 */
2647*4882a593Smuzhiyun rtw_write8(adapter, REG_MISC_CTRL,
2648*4882a593Smuzhiyun rtw_read8(adapter, REG_MISC_CTRL)&(~BIT_EN_FREECNT));
2649*4882a593Smuzhiyun
2650*4882a593Smuzhiyun /* reset FREE_RUN_COUNTER set 0x553[5]=1 */
2651*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_DUAL_TSF_RST);
2652*4882a593Smuzhiyun val8 |= BIT_FREECNT_RST;
2653*4882a593Smuzhiyun rtw_write8(adapter, REG_DUAL_TSF_RST, val8);
2654*4882a593Smuzhiyun
2655*4882a593Smuzhiyun /* enable free run counter 0x577[3]=1 */
2656*4882a593Smuzhiyun rtw_write8(adapter, REG_MISC_CTRL,
2657*4882a593Smuzhiyun rtw_read8(adapter, REG_MISC_CTRL)|BIT_EN_FREECNT);
2658*4882a593Smuzhiyun }
2659*4882a593Smuzhiyun break;
2660*4882a593Smuzhiyun
2661*4882a593Smuzhiyun case HW_VAR_SET_SOML_PARAM:
2662*4882a593Smuzhiyun #ifdef CONFIG_DYNAMIC_SOML
2663*4882a593Smuzhiyun rtw_dyn_soml_para_set(adapter, 4, 20, 1, 0);
2664*4882a593Smuzhiyun #endif
2665*4882a593Smuzhiyun break;
2666*4882a593Smuzhiyun
2667*4882a593Smuzhiyun #ifdef CONFIG_WAKE_ON_BT
2668*4882a593Smuzhiyun case HW_VAR_WAKE_ON_BT_GPIO_SWITCH: {
2669*4882a593Smuzhiyun int status = 0;
2670*4882a593Smuzhiyun u8 enable = *val;
2671*4882a593Smuzhiyun
2672*4882a593Smuzhiyun if (enable) {
2673*4882a593Smuzhiyun /* Should disable wl_led control at first
2674*4882a593Smuzhiyun halmac will check if wl_led is enabled before switch BT wake GPIO */
2675*4882a593Smuzhiyun status = rtw_halmac_led_cfg(adapter_to_dvobj(adapter), _FALSE, 3);
2676*4882a593Smuzhiyun status = rtw_halmac_bt_wake_cfg(adapter_to_dvobj(adapter), *val);
2677*4882a593Smuzhiyun if (status)
2678*4882a593Smuzhiyun RTW_INFO("[WakeOnBT] Enable BT control fail, status: %d\n", status);
2679*4882a593Smuzhiyun } else {
2680*4882a593Smuzhiyun status = rtw_halmac_bt_wake_cfg(adapter_to_dvobj(adapter), *val);
2681*4882a593Smuzhiyun status = rtw_halmac_led_cfg(adapter_to_dvobj(adapter), _TRUE, 3);
2682*4882a593Smuzhiyun }
2683*4882a593Smuzhiyun }
2684*4882a593Smuzhiyun break;
2685*4882a593Smuzhiyun #endif
2686*4882a593Smuzhiyun default:
2687*4882a593Smuzhiyun ret = SetHwReg(adapter, variable, val);
2688*4882a593Smuzhiyun break;
2689*4882a593Smuzhiyun }
2690*4882a593Smuzhiyun
2691*4882a593Smuzhiyun return ret;
2692*4882a593Smuzhiyun }
2693*4882a593Smuzhiyun
2694*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG
2695*4882a593Smuzhiyun struct qinfo {
2696*4882a593Smuzhiyun u32 head:11;
2697*4882a593Smuzhiyun u32 tail:11;
2698*4882a593Smuzhiyun u32 empty:1;
2699*4882a593Smuzhiyun u32 ac:2;
2700*4882a593Smuzhiyun u32 macid:7;
2701*4882a593Smuzhiyun };
2702*4882a593Smuzhiyun
2703*4882a593Smuzhiyun struct bcn_qinfo {
2704*4882a593Smuzhiyun u16 head:12;
2705*4882a593Smuzhiyun u16 rsvd:4;
2706*4882a593Smuzhiyun };
2707*4882a593Smuzhiyun
dump_qinfo(void * sel,struct qinfo * info,u32 pkt_num,const char * tag)2708*4882a593Smuzhiyun static void dump_qinfo(void *sel, struct qinfo *info, u32 pkt_num, const char *tag)
2709*4882a593Smuzhiyun {
2710*4882a593Smuzhiyun RTW_PRINT_SEL(sel, "%shead:0x%02x, tail:0x%02x, pkt_num:%u, macid:%u, ac:%u\n",
2711*4882a593Smuzhiyun tag ? tag : "", info->head, info->tail, pkt_num, info->macid, info->ac);
2712*4882a593Smuzhiyun }
2713*4882a593Smuzhiyun
dump_bcn_qinfo(void * sel,struct bcn_qinfo * info,u32 pkt_num,const char * tag)2714*4882a593Smuzhiyun static void dump_bcn_qinfo(void *sel, struct bcn_qinfo *info, u32 pkt_num, const char *tag)
2715*4882a593Smuzhiyun {
2716*4882a593Smuzhiyun RTW_PRINT_SEL(sel, "%shead:0x%02x, pkt_num:%u\n",
2717*4882a593Smuzhiyun tag ? tag : "", info->head, pkt_num);
2718*4882a593Smuzhiyun }
2719*4882a593Smuzhiyun
dump_mac_qinfo(void * sel,_adapter * adapter)2720*4882a593Smuzhiyun static void dump_mac_qinfo(void *sel, _adapter *adapter)
2721*4882a593Smuzhiyun {
2722*4882a593Smuzhiyun u32 q0_info;
2723*4882a593Smuzhiyun u32 q1_info;
2724*4882a593Smuzhiyun u32 q2_info;
2725*4882a593Smuzhiyun u32 q3_info;
2726*4882a593Smuzhiyun u32 q4_info;
2727*4882a593Smuzhiyun u32 q5_info;
2728*4882a593Smuzhiyun u32 q6_info;
2729*4882a593Smuzhiyun u32 q7_info;
2730*4882a593Smuzhiyun u32 mg_q_info;
2731*4882a593Smuzhiyun u32 hi_q_info;
2732*4882a593Smuzhiyun u16 bcn_q_info;
2733*4882a593Smuzhiyun u32 q0_q1_info;
2734*4882a593Smuzhiyun u32 q2_q3_info;
2735*4882a593Smuzhiyun u32 q4_q5_info;
2736*4882a593Smuzhiyun u32 q6_q7_info;
2737*4882a593Smuzhiyun u32 mg_hi_q_info;
2738*4882a593Smuzhiyun u32 cmd_bcn_q_info;
2739*4882a593Smuzhiyun
2740*4882a593Smuzhiyun q0_info = rtw_read32(adapter, REG_Q0_INFO_8822C);
2741*4882a593Smuzhiyun q1_info = rtw_read32(adapter, REG_Q1_INFO_8822C);
2742*4882a593Smuzhiyun q2_info = rtw_read32(adapter, REG_Q2_INFO_8822C);
2743*4882a593Smuzhiyun q3_info = rtw_read32(adapter, REG_Q3_INFO_8822C);
2744*4882a593Smuzhiyun q4_info = rtw_read32(adapter, REG_Q4_INFO_8822C);
2745*4882a593Smuzhiyun q5_info = rtw_read32(adapter, REG_Q5_INFO_8822C);
2746*4882a593Smuzhiyun q6_info = rtw_read32(adapter, REG_Q6_INFO_8822C);
2747*4882a593Smuzhiyun q7_info = rtw_read32(adapter, REG_Q7_INFO_8822C);
2748*4882a593Smuzhiyun mg_q_info = rtw_read32(adapter, REG_MGQ_INFO_8822C);
2749*4882a593Smuzhiyun hi_q_info = rtw_read32(adapter, REG_HIQ_INFO_8822C);
2750*4882a593Smuzhiyun bcn_q_info = rtw_read16(adapter, REG_BCNQ_INFO_8822C);
2751*4882a593Smuzhiyun
2752*4882a593Smuzhiyun q0_q1_info = rtw_read32(adapter, REG_Q0_Q1_INFO_8822C);
2753*4882a593Smuzhiyun q2_q3_info = rtw_read32(adapter, REG_Q2_Q3_INFO_8822C);
2754*4882a593Smuzhiyun q4_q5_info = rtw_read32(adapter, REG_Q4_Q5_INFO_8822C);
2755*4882a593Smuzhiyun q6_q7_info = rtw_read32(adapter, REG_Q6_Q7_INFO_8822C);
2756*4882a593Smuzhiyun mg_hi_q_info = rtw_read32(adapter, REG_MGQ_HIQ_INFO_8822C);
2757*4882a593Smuzhiyun cmd_bcn_q_info = rtw_read32(adapter, REG_CMDQ_BCNQ_INFO_8822C);
2758*4882a593Smuzhiyun
2759*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q0_info, q0_q1_info&0xFFF, "Q0 ");
2760*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q1_info, (q0_q1_info>>15)&0xFFF, "Q1 ");
2761*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q2_info, q2_q3_info&0xFFF, "Q2 ");
2762*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q3_info, (q2_q3_info>>15)&0xFFF, "Q3 ");
2763*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q4_info, q4_q5_info&0xFFF, "Q4 ");
2764*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q5_info, (q4_q5_info>>15)&0xFFF, "Q5 ");
2765*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q6_info, q6_q7_info&0xFFF, "Q6 ");
2766*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&q7_info, (q6_q7_info>>15)&0xFFF, "Q7 ");
2767*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&mg_q_info, mg_hi_q_info&0xFFF, "MG ");
2768*4882a593Smuzhiyun dump_qinfo(sel, (struct qinfo *)&hi_q_info, (mg_hi_q_info>>15)&0xFFF, "HI ");
2769*4882a593Smuzhiyun dump_bcn_qinfo(sel, (struct bcn_qinfo *)&bcn_q_info, cmd_bcn_q_info&0xFFF, "BCN ");
2770*4882a593Smuzhiyun
2771*4882a593Smuzhiyun }
2772*4882a593Smuzhiyun
dump_mac_txfifo(void * sel,_adapter * adapter)2773*4882a593Smuzhiyun static void dump_mac_txfifo(void *sel, _adapter *adapter)
2774*4882a593Smuzhiyun {
2775*4882a593Smuzhiyun u32 hpq, lpq, npq, epq, pubq;
2776*4882a593Smuzhiyun
2777*4882a593Smuzhiyun hpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_1_8822C);
2778*4882a593Smuzhiyun lpq = rtw_read32(adapter, REG_FIFOPAGE_INFO_2_8822C);
2779*4882a593Smuzhiyun npq = rtw_read32(adapter, REG_FIFOPAGE_INFO_3_8822C);
2780*4882a593Smuzhiyun epq = rtw_read32(adapter, REG_FIFOPAGE_INFO_4_8822C);
2781*4882a593Smuzhiyun pubq = rtw_read32(adapter, REG_FIFOPAGE_INFO_5_8822C);
2782*4882a593Smuzhiyun
2783*4882a593Smuzhiyun hpq = (hpq & 0xFFF0000)>>16;
2784*4882a593Smuzhiyun lpq = (lpq & 0xFFF0000)>>16;
2785*4882a593Smuzhiyun npq = (npq & 0xFFF0000)>>16;
2786*4882a593Smuzhiyun epq = (epq & 0xFFF0000)>>16;
2787*4882a593Smuzhiyun pubq = (pubq & 0xFFF0000)>>16;
2788*4882a593Smuzhiyun
2789*4882a593Smuzhiyun RTW_PRINT_SEL(sel, "Tx: available page num: ");
2790*4882a593Smuzhiyun if ((hpq == 0xAEA) && (hpq == lpq) && (hpq == pubq))
2791*4882a593Smuzhiyun RTW_PRINT_SEL(sel, "N/A (reg val = 0xea)\n");
2792*4882a593Smuzhiyun else
2793*4882a593Smuzhiyun RTW_PRINT_SEL(sel, "HPQ: %d, LPQ: %d, NPQ: %d, EPQ: %d, PUBQ: %d\n"
2794*4882a593Smuzhiyun , hpq, lpq, npq, epq, pubq);
2795*4882a593Smuzhiyun }
2796*4882a593Smuzhiyun #endif
2797*4882a593Smuzhiyun
hw_var_get_bcn_valid(PADAPTER adapter)2798*4882a593Smuzhiyun static u8 hw_var_get_bcn_valid(PADAPTER adapter)
2799*4882a593Smuzhiyun {
2800*4882a593Smuzhiyun u8 val8 = 0;
2801*4882a593Smuzhiyun u8 ret = _FALSE;
2802*4882a593Smuzhiyun
2803*4882a593Smuzhiyun /* only port 0 can TX BCN */
2804*4882a593Smuzhiyun val8 = rtw_read8(adapter, REG_FIFOPAGE_CTRL_2_8822C + 1);
2805*4882a593Smuzhiyun ret = (BIT(7) & val8) ? _TRUE : _FALSE;
2806*4882a593Smuzhiyun
2807*4882a593Smuzhiyun return ret;
2808*4882a593Smuzhiyun }
2809*4882a593Smuzhiyun
rtl8822c_read_wmmedca_reg(PADAPTER adapter,u16 * vo_params,u16 * vi_params,u16 * be_params,u16 * bk_params)2810*4882a593Smuzhiyun void rtl8822c_read_wmmedca_reg(PADAPTER adapter, u16 *vo_params, u16 *vi_params, u16 *be_params, u16 *bk_params)
2811*4882a593Smuzhiyun {
2812*4882a593Smuzhiyun u8 vo_reg_params[4];
2813*4882a593Smuzhiyun u8 vi_reg_params[4];
2814*4882a593Smuzhiyun u8 be_reg_params[4];
2815*4882a593Smuzhiyun u8 bk_reg_params[4];
2816*4882a593Smuzhiyun
2817*4882a593Smuzhiyun rtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_VO, vo_reg_params);
2818*4882a593Smuzhiyun rtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_VI, vi_reg_params);
2819*4882a593Smuzhiyun rtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_BE, be_reg_params);
2820*4882a593Smuzhiyun rtl8822c_gethwreg(adapter, HW_VAR_AC_PARAM_BK, bk_reg_params);
2821*4882a593Smuzhiyun
2822*4882a593Smuzhiyun vo_params[0] = vo_reg_params[0];
2823*4882a593Smuzhiyun vo_params[1] = vo_reg_params[1] & 0x0F;
2824*4882a593Smuzhiyun vo_params[2] = (vo_reg_params[1] & 0xF0) >> 4;
2825*4882a593Smuzhiyun vo_params[3] = ((vo_reg_params[3] << 8) | (vo_reg_params[2])) * 32;
2826*4882a593Smuzhiyun
2827*4882a593Smuzhiyun vi_params[0] = vi_reg_params[0];
2828*4882a593Smuzhiyun vi_params[1] = vi_reg_params[1] & 0x0F;
2829*4882a593Smuzhiyun vi_params[2] = (vi_reg_params[1] & 0xF0) >> 4;
2830*4882a593Smuzhiyun vi_params[3] = ((vi_reg_params[3] << 8) | (vi_reg_params[2])) * 32;
2831*4882a593Smuzhiyun
2832*4882a593Smuzhiyun be_params[0] = be_reg_params[0];
2833*4882a593Smuzhiyun be_params[1] = be_reg_params[1] & 0x0F;
2834*4882a593Smuzhiyun be_params[2] = (be_reg_params[1] & 0xF0) >> 4;
2835*4882a593Smuzhiyun be_params[3] = ((be_reg_params[3] << 8) | (be_reg_params[2])) * 32;
2836*4882a593Smuzhiyun
2837*4882a593Smuzhiyun bk_params[0] = bk_reg_params[0];
2838*4882a593Smuzhiyun bk_params[1] = bk_reg_params[1] & 0x0F;
2839*4882a593Smuzhiyun bk_params[2] = (bk_reg_params[1] & 0xF0) >> 4;
2840*4882a593Smuzhiyun bk_params[3] = ((bk_reg_params[3] << 8) | (bk_reg_params[2])) * 32;
2841*4882a593Smuzhiyun
2842*4882a593Smuzhiyun vo_params[1] = (1 << vo_params[1]) - 1;
2843*4882a593Smuzhiyun vo_params[2] = (1 << vo_params[2]) - 1;
2844*4882a593Smuzhiyun vi_params[1] = (1 << vi_params[1]) - 1;
2845*4882a593Smuzhiyun vi_params[2] = (1 << vi_params[2]) - 1;
2846*4882a593Smuzhiyun be_params[1] = (1 << be_params[1]) - 1;
2847*4882a593Smuzhiyun be_params[2] = (1 << be_params[2]) - 1;
2848*4882a593Smuzhiyun bk_params[1] = (1 << bk_params[1]) - 1;
2849*4882a593Smuzhiyun bk_params[2] = (1 << bk_params[2]) - 1;
2850*4882a593Smuzhiyun }
2851*4882a593Smuzhiyun
rtl8822c_gethwreg(PADAPTER adapter,u8 variable,u8 * val)2852*4882a593Smuzhiyun void rtl8822c_gethwreg(PADAPTER adapter, u8 variable, u8 *val)
2853*4882a593Smuzhiyun {
2854*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
2855*4882a593Smuzhiyun u8 val8;
2856*4882a593Smuzhiyun u16 val16;
2857*4882a593Smuzhiyun u32 val32;
2858*4882a593Smuzhiyun u64 val64;
2859*4882a593Smuzhiyun
2860*4882a593Smuzhiyun
2861*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
2862*4882a593Smuzhiyun
2863*4882a593Smuzhiyun switch (variable) {
2864*4882a593Smuzhiyun /*
2865*4882a593Smuzhiyun case HW_VAR_INIT_RTS_RATE:
2866*4882a593Smuzhiyun case HW_VAR_BASIC_RATE:
2867*4882a593Smuzhiyun break;
2868*4882a593Smuzhiyun */
2869*4882a593Smuzhiyun case HW_VAR_TXPAUSE:
2870*4882a593Smuzhiyun *val = rtw_read8(adapter, REG_TXPAUSE_8822C);
2871*4882a593Smuzhiyun break;
2872*4882a593Smuzhiyun /*
2873*4882a593Smuzhiyun case HW_VAR_BCN_FUNC:
2874*4882a593Smuzhiyun case HW_VAR_MLME_DISCONNECT:
2875*4882a593Smuzhiyun case HW_VAR_MLME_SITESURVEY:
2876*4882a593Smuzhiyun case HW_VAR_MLME_JOIN:
2877*4882a593Smuzhiyun case HW_VAR_BEACON_INTERVAL:
2878*4882a593Smuzhiyun case HW_VAR_SLOT_TIME:
2879*4882a593Smuzhiyun case HW_VAR_RESP_SIFS:
2880*4882a593Smuzhiyun case HW_VAR_ACK_PREAMBLE:
2881*4882a593Smuzhiyun case HW_VAR_SEC_CFG:
2882*4882a593Smuzhiyun case HW_VAR_SEC_DK_CFG:
2883*4882a593Smuzhiyun break;
2884*4882a593Smuzhiyun */
2885*4882a593Smuzhiyun case HW_VAR_BCN_VALID:
2886*4882a593Smuzhiyun *val = hw_var_get_bcn_valid(adapter);
2887*4882a593Smuzhiyun break;
2888*4882a593Smuzhiyun
2889*4882a593Smuzhiyun case HW_VAR_FREECNT:
2890*4882a593Smuzhiyun /* free run counter 0x577[3]=1 means running */
2891*4882a593Smuzhiyun *val = rtw_read8(adapter, REG_MISC_CTRL)&BIT_EN_FREECNT;
2892*4882a593Smuzhiyun break;
2893*4882a593Smuzhiyun /*
2894*4882a593Smuzhiyun case HW_VAR_CAM_INVALID_ALL:
2895*4882a593Smuzhiyun */
2896*4882a593Smuzhiyun case HW_VAR_AC_PARAM_VO:
2897*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_EDCA_VO_PARAM);
2898*4882a593Smuzhiyun val[0] = val32 & 0xFF;
2899*4882a593Smuzhiyun val[1] = (val32 >> 8) & 0xFF;
2900*4882a593Smuzhiyun val[2] = (val32 >> 16) & 0xFF;
2901*4882a593Smuzhiyun val[3] = (val32 >> 24) & 0x07;
2902*4882a593Smuzhiyun break;
2903*4882a593Smuzhiyun
2904*4882a593Smuzhiyun case HW_VAR_AC_PARAM_VI:
2905*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_EDCA_VI_PARAM);
2906*4882a593Smuzhiyun val[0] = val32 & 0xFF;
2907*4882a593Smuzhiyun val[1] = (val32 >> 8) & 0xFF;
2908*4882a593Smuzhiyun val[2] = (val32 >> 16) & 0xFF;
2909*4882a593Smuzhiyun val[3] = (val32 >> 24) & 0x07;
2910*4882a593Smuzhiyun break;
2911*4882a593Smuzhiyun
2912*4882a593Smuzhiyun case HW_VAR_AC_PARAM_BE:
2913*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_EDCA_BE_PARAM);
2914*4882a593Smuzhiyun val[0] = val32 & 0xFF;
2915*4882a593Smuzhiyun val[1] = (val32 >> 8) & 0xFF;
2916*4882a593Smuzhiyun val[2] = (val32 >> 16) & 0xFF;
2917*4882a593Smuzhiyun val[3] = (val32 >> 24) & 0x07;
2918*4882a593Smuzhiyun break;
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun case HW_VAR_AC_PARAM_BK:
2921*4882a593Smuzhiyun val32 = rtw_read32(adapter, REG_EDCA_BK_PARAM);
2922*4882a593Smuzhiyun val[0] = val32 & 0xFF;
2923*4882a593Smuzhiyun val[1] = (val32 >> 8) & 0xFF;
2924*4882a593Smuzhiyun val[2] = (val32 >> 16) & 0xFF;
2925*4882a593Smuzhiyun val[3] = (val32 >> 24) & 0x07;
2926*4882a593Smuzhiyun break;
2927*4882a593Smuzhiyun /*
2928*4882a593Smuzhiyun case HW_VAR_ACM_CTRL:
2929*4882a593Smuzhiyun case HW_VAR_AMPDU_MIN_SPACE:
2930*4882a593Smuzhiyun case HW_VAR_AMPDU_FACTOR:
2931*4882a593Smuzhiyun case HW_VAR_RXDMA_AGG_PG_TH:
2932*4882a593Smuzhiyun case HW_VAR_SET_RPWM:
2933*4882a593Smuzhiyun case HW_VAR_CPWM:
2934*4882a593Smuzhiyun case HW_VAR_H2C_FW_PWRMODE:
2935*4882a593Smuzhiyun case HW_VAR_H2C_PS_TUNE_PARAM:
2936*4882a593Smuzhiyun case HW_VAR_H2C_FW_JOINBSSRPT:
2937*4882a593Smuzhiyun break;
2938*4882a593Smuzhiyun */
2939*4882a593Smuzhiyun case HW_VAR_FWLPS_RF_ON:
2940*4882a593Smuzhiyun /* When we halt NIC, we should check if FW LPS is leave. */
2941*4882a593Smuzhiyun if (rtw_is_surprise_removed(adapter) ||
2942*4882a593Smuzhiyun (adapter_to_pwrctl(adapter)->rf_pwrstate == rf_off)) {
2943*4882a593Smuzhiyun /*
2944*4882a593Smuzhiyun * If it is in HW/SW Radio OFF or IPS state,
2945*4882a593Smuzhiyun * we do not check Fw LPS Leave,
2946*4882a593Smuzhiyun * because Fw is unload.
2947*4882a593Smuzhiyun */
2948*4882a593Smuzhiyun *val = _TRUE;
2949*4882a593Smuzhiyun } else {
2950*4882a593Smuzhiyun rtw_hal_get_hwreg(adapter, HW_VAR_RCR, (u8 *)&val32);
2951*4882a593Smuzhiyun
2952*4882a593Smuzhiyun if (adapter_to_pwrctl(adapter)->wowlan_mode == _TRUE)
2953*4882a593Smuzhiyun val32 &= (BIT_UC_MD_EN_8822C | BIT_BC_MD_EN_8822C);
2954*4882a593Smuzhiyun else
2955*4882a593Smuzhiyun val32 &= (BIT_UC_MD_EN_8822C | BIT_BC_MD_EN_8822C | BIT_TIM_PARSER_EN_8822C);
2956*4882a593Smuzhiyun
2957*4882a593Smuzhiyun if (val32)
2958*4882a593Smuzhiyun *val = _FALSE;
2959*4882a593Smuzhiyun else
2960*4882a593Smuzhiyun *val = _TRUE;
2961*4882a593Smuzhiyun }
2962*4882a593Smuzhiyun break;
2963*4882a593Smuzhiyun /*
2964*4882a593Smuzhiyun case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
2965*4882a593Smuzhiyun case HW_VAR_TRIGGER_GPIO_0:
2966*4882a593Smuzhiyun case HW_VAR_BT_SET_COEXIST:
2967*4882a593Smuzhiyun case HW_VAR_BT_ISSUE_DELBA:
2968*4882a593Smuzhiyun case HW_VAR_SWITCH_EPHY_WoWLAN:
2969*4882a593Smuzhiyun case HW_VAR_EFUSE_USAGE:
2970*4882a593Smuzhiyun case HW_VAR_EFUSE_BYTES:
2971*4882a593Smuzhiyun case HW_VAR_EFUSE_BT_USAGE:
2972*4882a593Smuzhiyun case HW_VAR_EFUSE_BT_BYTES:
2973*4882a593Smuzhiyun case HW_VAR_FIFO_CLEARN_UP:
2974*4882a593Smuzhiyun case HW_VAR_RESTORE_HW_SEQ:
2975*4882a593Smuzhiyun case HW_VAR_CHECK_TXBUF:
2976*4882a593Smuzhiyun case HW_VAR_PCIE_STOP_TX_DMA:
2977*4882a593Smuzhiyun break;
2978*4882a593Smuzhiyun */
2979*4882a593Smuzhiyun
2980*4882a593Smuzhiyun /*
2981*4882a593Smuzhiyun case HW_VAR_HCI_SUS_STATE:
2982*4882a593Smuzhiyun break;
2983*4882a593Smuzhiyun */
2984*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
2985*4882a593Smuzhiyun /*
2986*4882a593Smuzhiyun case HW_VAR_WOWLAN:
2987*4882a593Smuzhiyun break;
2988*4882a593Smuzhiyun
2989*4882a593Smuzhiyun case HW_VAR_WAKEUP_REASON:
2990*4882a593Smuzhiyun rtw_halmac_get_wow_reason(adapter_to_dvobj(adapter), val);
2991*4882a593Smuzhiyun break;
2992*4882a593Smuzhiyun
2993*4882a593Smuzhiyun case HW_VAR_RPWM_TOG:
2994*4882a593Smuzhiyun break;
2995*4882a593Smuzhiyun */
2996*4882a593Smuzhiyun #endif
2997*4882a593Smuzhiyun /*
2998*4882a593Smuzhiyun #ifdef CONFIG_GPIO_WAKEUP
2999*4882a593Smuzhiyun case HW_SET_GPIO_WL_CTRL:
3000*4882a593Smuzhiyun break;
3001*4882a593Smuzhiyun #endif
3002*4882a593Smuzhiyun */
3003*4882a593Smuzhiyun case HW_VAR_SYS_CLKR:
3004*4882a593Smuzhiyun *val = rtw_read8(adapter, REG_SYS_CLK_CTRL_8822C);
3005*4882a593Smuzhiyun break;
3006*4882a593Smuzhiyun /*
3007*4882a593Smuzhiyun case HW_VAR_NAV_UPPER:
3008*4882a593Smuzhiyun case HW_VAR_RPT_TIMER_SETTING:
3009*4882a593Smuzhiyun case HW_VAR_TX_RPT_MAX_MACID:
3010*4882a593Smuzhiyun break;
3011*4882a593Smuzhiyun */
3012*4882a593Smuzhiyun case HW_VAR_CHK_HI_QUEUE_EMPTY:
3013*4882a593Smuzhiyun val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822C);
3014*4882a593Smuzhiyun *val = (val16 & BIT_HQQ_EMPTY_8822C) ? _TRUE : _FALSE;
3015*4882a593Smuzhiyun break;
3016*4882a593Smuzhiyun case HW_VAR_CHK_MGQ_CPU_EMPTY:
3017*4882a593Smuzhiyun val16 = rtw_read16(adapter, REG_TXPKT_EMPTY_8822C);
3018*4882a593Smuzhiyun *val = (val16 & BIT_MGQ_CPU_EMPTY_8822C) ? _TRUE : _FALSE;
3019*4882a593Smuzhiyun break;
3020*4882a593Smuzhiyun /*
3021*4882a593Smuzhiyun case HW_VAR_DL_BCN_SEL:
3022*4882a593Smuzhiyun case HW_VAR_AMPDU_MAX_TIME:
3023*4882a593Smuzhiyun case HW_VAR_USB_MODE:
3024*4882a593Smuzhiyun case HW_VAR_PORT_SWITCH:
3025*4882a593Smuzhiyun case HW_VAR_DO_IQK:
3026*4882a593Smuzhiyun case HW_VAR_SOUNDING_ENTER:
3027*4882a593Smuzhiyun case HW_VAR_SOUNDING_LEAVE:
3028*4882a593Smuzhiyun case HW_VAR_SOUNDING_RATE:
3029*4882a593Smuzhiyun case HW_VAR_SOUNDING_STATUS:
3030*4882a593Smuzhiyun case HW_VAR_SOUNDING_FW_NDPA:
3031*4882a593Smuzhiyun case HW_VAR_SOUNDING_CLK:
3032*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_INIT:
3033*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_RESTART:
3034*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_START:
3035*4882a593Smuzhiyun case HW_VAR_HW_REG_TIMER_STOP:
3036*4882a593Smuzhiyun case HW_VAR_MACID_LINK:
3037*4882a593Smuzhiyun case HW_VAR_MACID_NOLINK:
3038*4882a593Smuzhiyun break;
3039*4882a593Smuzhiyun */
3040*4882a593Smuzhiyun case HW_VAR_FW_PS_STATE:
3041*4882a593Smuzhiyun /* driver read REG_SYS_CFG5 - BIT_LPS_STATUS REG_1070[3] to get hw ps state */
3042*4882a593Smuzhiyun *((u16 *)val) = rtw_read8(adapter, REG_SYS_CFG5);
3043*4882a593Smuzhiyun break;
3044*4882a593Smuzhiyun #ifdef CONFIG_PROC_DEBUG
3045*4882a593Smuzhiyun case HW_VAR_DUMP_MAC_QUEUE_INFO:
3046*4882a593Smuzhiyun dump_mac_qinfo(val, adapter);
3047*4882a593Smuzhiyun break;
3048*4882a593Smuzhiyun
3049*4882a593Smuzhiyun case HW_VAR_DUMP_MAC_TXFIFO:
3050*4882a593Smuzhiyun dump_mac_txfifo(val, adapter);
3051*4882a593Smuzhiyun break;
3052*4882a593Smuzhiyun #endif
3053*4882a593Smuzhiyun /*
3054*4882a593Smuzhiyun case HW_VAR_ASIX_IOT:
3055*4882a593Smuzhiyun case HW_VAR_EN_HW_UPDATE_TSF:
3056*4882a593Smuzhiyun case HW_VAR_CH_SW_NEED_TO_TAKE_CARE_IQK_INFO:
3057*4882a593Smuzhiyun case HW_VAR_CH_SW_IQK_INFO_BACKUP:
3058*4882a593Smuzhiyun case HW_VAR_CH_SW_IQK_INFO_RESTORE:
3059*4882a593Smuzhiyun #ifdef CONFIG_TDLS
3060*4882a593Smuzhiyun #ifdef CONFIG_TDLS_CH_SW
3061*4882a593Smuzhiyun case HW_VAR_BCN_EARLY_C2H_RPT:
3062*4882a593Smuzhiyun #endif
3063*4882a593Smuzhiyun #endif
3064*4882a593Smuzhiyun break;
3065*4882a593Smuzhiyun */
3066*4882a593Smuzhiyun
3067*4882a593Smuzhiyun case HW_VAR_BCN_CTRL_ADDR:
3068*4882a593Smuzhiyun *((u32 *)val) = hw_bcn_ctrl_addr(adapter, adapter->hw_port);
3069*4882a593Smuzhiyun break;
3070*4882a593Smuzhiyun
3071*4882a593Smuzhiyun default:
3072*4882a593Smuzhiyun GetHwReg(adapter, variable, val);
3073*4882a593Smuzhiyun break;
3074*4882a593Smuzhiyun }
3075*4882a593Smuzhiyun }
3076*4882a593Smuzhiyun
3077*4882a593Smuzhiyun /*
3078*4882a593Smuzhiyun * Description:
3079*4882a593Smuzhiyun * Change default setting of specified variable.
3080*4882a593Smuzhiyun */
rtl8822c_sethaldefvar(PADAPTER adapter,HAL_DEF_VARIABLE variable,void * pval)3081*4882a593Smuzhiyun u8 rtl8822c_sethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
3082*4882a593Smuzhiyun {
3083*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
3084*4882a593Smuzhiyun u8 bResult;
3085*4882a593Smuzhiyun
3086*4882a593Smuzhiyun
3087*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
3088*4882a593Smuzhiyun bResult = _SUCCESS;
3089*4882a593Smuzhiyun
3090*4882a593Smuzhiyun switch (variable) {
3091*4882a593Smuzhiyun /*
3092*4882a593Smuzhiyun case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3093*4882a593Smuzhiyun case HAL_DEF_IS_SUPPORT_ANT_DIV:
3094*4882a593Smuzhiyun case HAL_DEF_DRVINFO_SZ:
3095*4882a593Smuzhiyun case HAL_DEF_MAX_RECVBUF_SZ:
3096*4882a593Smuzhiyun case HAL_DEF_RX_PACKET_OFFSET:
3097*4882a593Smuzhiyun case HAL_DEF_RX_DMA_SZ_WOW:
3098*4882a593Smuzhiyun case HAL_DEF_RX_DMA_SZ:
3099*4882a593Smuzhiyun case HAL_DEF_RX_PAGE_SIZE:
3100*4882a593Smuzhiyun case HAL_DEF_DBG_DUMP_RXPKT:
3101*4882a593Smuzhiyun case HAL_DEF_RA_DECISION_RATE:
3102*4882a593Smuzhiyun case HAL_DEF_RA_SGI:
3103*4882a593Smuzhiyun case HAL_DEF_PT_PWR_STATUS:
3104*4882a593Smuzhiyun case HAL_DEF_TX_LDPC:
3105*4882a593Smuzhiyun case HAL_DEF_RX_LDPC:
3106*4882a593Smuzhiyun case HAL_DEF_TX_STBC:
3107*4882a593Smuzhiyun case HAL_DEF_RX_STBC:
3108*4882a593Smuzhiyun case HAL_DEF_EXPLICIT_BEAMFORMER:
3109*4882a593Smuzhiyun case HAL_DEF_EXPLICIT_BEAMFORMEE:
3110*4882a593Smuzhiyun case HAL_DEF_VHT_MU_BEAMFORMER:
3111*4882a593Smuzhiyun case HAL_DEF_VHT_MU_BEAMFORMEE:
3112*4882a593Smuzhiyun case HAL_DEF_BEAMFORMER_CAP:
3113*4882a593Smuzhiyun case HAL_DEF_BEAMFORMEE_CAP:
3114*4882a593Smuzhiyun case HW_VAR_MAX_RX_AMPDU_FACTOR:
3115*4882a593Smuzhiyun case HAL_DEF_DBG_DUMP_TXPKT:
3116*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_SIZE:
3117*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_BOUNDARY:
3118*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
3119*4882a593Smuzhiyun case HAL_DEF_ANT_DETECT:
3120*4882a593Smuzhiyun case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
3121*4882a593Smuzhiyun case HAL_DEF_PCI_AMD_L1_SUPPORT:
3122*4882a593Smuzhiyun case HAL_DEF_PCI_ASPM_OSC:
3123*4882a593Smuzhiyun case HAL_DEF_EFUSE_USAGE:
3124*4882a593Smuzhiyun case HAL_DEF_EFUSE_BYTES:
3125*4882a593Smuzhiyun case HW_VAR_BEST_AMPDU_DENSITY:
3126*4882a593Smuzhiyun break;
3127*4882a593Smuzhiyun */
3128*4882a593Smuzhiyun default:
3129*4882a593Smuzhiyun bResult = SetHalDefVar(adapter, variable, pval);
3130*4882a593Smuzhiyun break;
3131*4882a593Smuzhiyun }
3132*4882a593Smuzhiyun
3133*4882a593Smuzhiyun return bResult;
3134*4882a593Smuzhiyun }
rtl8822c_ra_info_dump(_adapter * padapter,void * sel)3135*4882a593Smuzhiyun void rtl8822c_ra_info_dump(_adapter *padapter, void *sel)
3136*4882a593Smuzhiyun {
3137*4882a593Smuzhiyun u8 mac_id;
3138*4882a593Smuzhiyun struct sta_info *psta;
3139*4882a593Smuzhiyun u32 rate_mask1, rate_mask2;
3140*4882a593Smuzhiyun struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
3141*4882a593Smuzhiyun struct macid_ctl_t *macid_ctl = dvobj_to_macidctl(dvobj);
3142*4882a593Smuzhiyun
3143*4882a593Smuzhiyun for (mac_id = 0; mac_id < macid_ctl->num; mac_id++) {
3144*4882a593Smuzhiyun if (rtw_macid_is_used(macid_ctl, mac_id) && !rtw_macid_is_bmc(macid_ctl, mac_id)) {
3145*4882a593Smuzhiyun psta = macid_ctl->sta[mac_id];
3146*4882a593Smuzhiyun if (!psta)
3147*4882a593Smuzhiyun continue;
3148*4882a593Smuzhiyun
3149*4882a593Smuzhiyun dump_sta_info(sel, psta);
3150*4882a593Smuzhiyun rate_mask1 = macid_ctl->rate_bmp0[mac_id];
3151*4882a593Smuzhiyun rate_mask2 = macid_ctl->rate_bmp1[mac_id];
3152*4882a593Smuzhiyun _RTW_PRINT_SEL(sel, "rate_mask2:0x%08x, rate_mask1:0x%08x\n", rate_mask2, rate_mask1);
3153*4882a593Smuzhiyun }
3154*4882a593Smuzhiyun }
3155*4882a593Smuzhiyun }
3156*4882a593Smuzhiyun /*
3157*4882a593Smuzhiyun * Description:
3158*4882a593Smuzhiyun * Query setting of specified variable.
3159*4882a593Smuzhiyun */
rtl8822c_gethaldefvar(PADAPTER adapter,HAL_DEF_VARIABLE variable,void * pval)3160*4882a593Smuzhiyun u8 rtl8822c_gethaldefvar(PADAPTER adapter, HAL_DEF_VARIABLE variable, void *pval)
3161*4882a593Smuzhiyun {
3162*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
3163*4882a593Smuzhiyun struct dvobj_priv *d;
3164*4882a593Smuzhiyun u8 bResult;
3165*4882a593Smuzhiyun u8 val8 = 0;
3166*4882a593Smuzhiyun u32 val32 = 0;
3167*4882a593Smuzhiyun
3168*4882a593Smuzhiyun
3169*4882a593Smuzhiyun d = adapter_to_dvobj(adapter);
3170*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
3171*4882a593Smuzhiyun bResult = _SUCCESS;
3172*4882a593Smuzhiyun
3173*4882a593Smuzhiyun switch (variable) {
3174*4882a593Smuzhiyun /*
3175*4882a593Smuzhiyun case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
3176*4882a593Smuzhiyun break;
3177*4882a593Smuzhiyun */
3178*4882a593Smuzhiyun case HAL_DEF_IS_SUPPORT_ANT_DIV:
3179*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
3180*4882a593Smuzhiyun *(u8 *)pval = _TRUE;
3181*4882a593Smuzhiyun #else
3182*4882a593Smuzhiyun *(u8 *)pval = _FALSE;
3183*4882a593Smuzhiyun #endif
3184*4882a593Smuzhiyun break;
3185*4882a593Smuzhiyun
3186*4882a593Smuzhiyun /*
3187*4882a593Smuzhiyun case HAL_DEF_DRVINFO_SZ:
3188*4882a593Smuzhiyun break;
3189*4882a593Smuzhiyun */
3190*4882a593Smuzhiyun case HAL_DEF_MAX_RECVBUF_SZ:
3191*4882a593Smuzhiyun *((u32 *)pval) = MAX_RECVBUF_SZ;
3192*4882a593Smuzhiyun break;
3193*4882a593Smuzhiyun
3194*4882a593Smuzhiyun case HAL_DEF_RX_PACKET_OFFSET:
3195*4882a593Smuzhiyun val32 = rtl8822c_get_rx_desc_size(adapter);
3196*4882a593Smuzhiyun val8 = rtl8822c_get_rx_drv_info_size(adapter);
3197*4882a593Smuzhiyun *((u32 *)pval) = val32 + val8;
3198*4882a593Smuzhiyun break;
3199*4882a593Smuzhiyun /*
3200*4882a593Smuzhiyun case HAL_DEF_RX_DMA_SZ_WOW:
3201*4882a593Smuzhiyun case HAL_DEF_RX_DMA_SZ:
3202*4882a593Smuzhiyun case HAL_DEF_RX_PAGE_SIZE:
3203*4882a593Smuzhiyun case HAL_DEF_DBG_DUMP_RXPKT:
3204*4882a593Smuzhiyun case HAL_DEF_RA_DECISION_RATE:
3205*4882a593Smuzhiyun case HAL_DEF_RA_SGI:
3206*4882a593Smuzhiyun break;
3207*4882a593Smuzhiyun */
3208*4882a593Smuzhiyun /* only for 8188E */
3209*4882a593Smuzhiyun case HAL_DEF_PT_PWR_STATUS:
3210*4882a593Smuzhiyun break;
3211*4882a593Smuzhiyun
3212*4882a593Smuzhiyun case HAL_DEF_TX_LDPC:
3213*4882a593Smuzhiyun case HAL_DEF_RX_LDPC:
3214*4882a593Smuzhiyun *(u8 *)pval = _TRUE;
3215*4882a593Smuzhiyun break;
3216*4882a593Smuzhiyun
3217*4882a593Smuzhiyun /* support 1RX for STBC */
3218*4882a593Smuzhiyun case HAL_DEF_RX_STBC:
3219*4882a593Smuzhiyun *(u8 *)pval = 1;
3220*4882a593Smuzhiyun break;
3221*4882a593Smuzhiyun
3222*4882a593Smuzhiyun /* support Explicit TxBF for HT/VHT */
3223*4882a593Smuzhiyun case HAL_DEF_EXPLICIT_BEAMFORMER:
3224*4882a593Smuzhiyun case HAL_DEF_EXPLICIT_BEAMFORMEE:
3225*4882a593Smuzhiyun case HAL_DEF_VHT_MU_BEAMFORMER:
3226*4882a593Smuzhiyun case HAL_DEF_VHT_MU_BEAMFORMEE:
3227*4882a593Smuzhiyun *(u8 *)pval = _TRUE;
3228*4882a593Smuzhiyun break;
3229*4882a593Smuzhiyun
3230*4882a593Smuzhiyun case HAL_DEF_BEAMFORMER_CAP:
3231*4882a593Smuzhiyun val8 = GET_HAL_TX_NSS(adapter);
3232*4882a593Smuzhiyun *(u8 *)pval = (val8 - 1);
3233*4882a593Smuzhiyun break;
3234*4882a593Smuzhiyun
3235*4882a593Smuzhiyun case HAL_DEF_BEAMFORMEE_CAP:
3236*4882a593Smuzhiyun *(u8 *)pval = 3;
3237*4882a593Smuzhiyun break;
3238*4882a593Smuzhiyun
3239*4882a593Smuzhiyun case HW_VAR_MAX_RX_AMPDU_FACTOR:
3240*4882a593Smuzhiyun /* 8822C RX FIFO is 24KB */
3241*4882a593Smuzhiyun *(HT_CAP_AMPDU_FACTOR *)pval = MAX_AMPDU_FACTOR_16K;
3242*4882a593Smuzhiyun break;
3243*4882a593Smuzhiyun
3244*4882a593Smuzhiyun case HW_DEF_RA_INFO_DUMP:
3245*4882a593Smuzhiyun rtl8822c_ra_info_dump(adapter, pval);
3246*4882a593Smuzhiyun break;
3247*4882a593Smuzhiyun /*
3248*4882a593Smuzhiyun case HAL_DEF_DBG_DUMP_TXPKT:
3249*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_SIZE:
3250*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_BOUNDARY:
3251*4882a593Smuzhiyun case HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN:
3252*4882a593Smuzhiyun case HAL_DEF_ANT_DETECT:
3253*4882a593Smuzhiyun case HAL_DEF_PCI_SUUPORT_L1_BACKDOOR:
3254*4882a593Smuzhiyun case HAL_DEF_PCI_AMD_L1_SUPPORT:
3255*4882a593Smuzhiyun case HAL_DEF_PCI_ASPM_OSC:
3256*4882a593Smuzhiyun case HAL_DEF_EFUSE_USAGE:
3257*4882a593Smuzhiyun case HAL_DEF_EFUSE_BYTES:
3258*4882a593Smuzhiyun break;
3259*4882a593Smuzhiyun */
3260*4882a593Smuzhiyun case HW_VAR_BEST_AMPDU_DENSITY:
3261*4882a593Smuzhiyun *((u32 *)pval) = AMPDU_DENSITY_VALUE_4;
3262*4882a593Smuzhiyun break;
3263*4882a593Smuzhiyun
3264*4882a593Smuzhiyun default:
3265*4882a593Smuzhiyun bResult = GetHalDefVar(adapter, variable, pval);
3266*4882a593Smuzhiyun break;
3267*4882a593Smuzhiyun }
3268*4882a593Smuzhiyun
3269*4882a593Smuzhiyun return bResult;
3270*4882a593Smuzhiyun }
3271*4882a593Smuzhiyun
rtl8822c_fill_txdesc_sectype(struct pkt_attrib * pattrib,u8 * ptxdesc)3272*4882a593Smuzhiyun void rtl8822c_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc)
3273*4882a593Smuzhiyun {
3274*4882a593Smuzhiyun if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
3275*4882a593Smuzhiyun /* SEC_TYPE : 0:NO_ENC,1:WEP40/TKIP,2:WAPI,3:AES */
3276*4882a593Smuzhiyun switch (pattrib->encrypt) {
3277*4882a593Smuzhiyun case _WEP40_:
3278*4882a593Smuzhiyun case _WEP104_:
3279*4882a593Smuzhiyun case _TKIP_:
3280*4882a593Smuzhiyun case _TKIP_WTMIC_:
3281*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x1);
3282*4882a593Smuzhiyun break;
3283*4882a593Smuzhiyun #ifdef CONFIG_WAPI_SUPPORT
3284*4882a593Smuzhiyun case _SMS4_:
3285*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x2);
3286*4882a593Smuzhiyun break;
3287*4882a593Smuzhiyun #endif
3288*4882a593Smuzhiyun case _AES_:
3289*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x3);
3290*4882a593Smuzhiyun break;
3291*4882a593Smuzhiyun case _CCMP_256_:
3292*4882a593Smuzhiyun case _GCMP_:
3293*4882a593Smuzhiyun case _GCMP_256_:
3294*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x2);
3295*4882a593Smuzhiyun break;
3296*4882a593Smuzhiyun case _NO_PRIVACY_:
3297*4882a593Smuzhiyun default:
3298*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(ptxdesc, 0x0);
3299*4882a593Smuzhiyun break;
3300*4882a593Smuzhiyun }
3301*4882a593Smuzhiyun }
3302*4882a593Smuzhiyun }
3303*4882a593Smuzhiyun
rtl8822c_fill_txdesc_vcs(PADAPTER adapter,struct pkt_attrib * pattrib,u8 * ptxdesc)3304*4882a593Smuzhiyun void rtl8822c_fill_txdesc_vcs(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
3305*4882a593Smuzhiyun {
3306*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
3307*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
3308*4882a593Smuzhiyun
3309*4882a593Smuzhiyun
3310*4882a593Smuzhiyun if (pattrib->vcs_mode) {
3311*4882a593Smuzhiyun switch (pattrib->vcs_mode) {
3312*4882a593Smuzhiyun case RTS_CTS:
3313*4882a593Smuzhiyun SET_TX_DESC_RTSEN_8822C(ptxdesc, 1);
3314*4882a593Smuzhiyun break;
3315*4882a593Smuzhiyun case CTS_TO_SELF:
3316*4882a593Smuzhiyun SET_TX_DESC_CTS2SELF_8822C(ptxdesc, 1);
3317*4882a593Smuzhiyun break;
3318*4882a593Smuzhiyun case NONE_VCS:
3319*4882a593Smuzhiyun default:
3320*4882a593Smuzhiyun break;
3321*4882a593Smuzhiyun }
3322*4882a593Smuzhiyun
3323*4882a593Smuzhiyun if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3324*4882a593Smuzhiyun SET_TX_DESC_RTS_SHORT_8822C(ptxdesc, 1);
3325*4882a593Smuzhiyun
3326*4882a593Smuzhiyun /* RTS Rate=24M */
3327*4882a593Smuzhiyun SET_TX_DESC_RTSRATE_8822C(ptxdesc, 0x8);
3328*4882a593Smuzhiyun
3329*4882a593Smuzhiyun /* compatibility for MCC consideration, use pmlmeext->cur_channel */
3330*4882a593Smuzhiyun if (pmlmeext->cur_channel > 14)
3331*4882a593Smuzhiyun /* RTS retry to rate OFDM 6M for 5G */
3332*4882a593Smuzhiyun SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(ptxdesc, 4);
3333*4882a593Smuzhiyun else
3334*4882a593Smuzhiyun /* RTS retry to rate CCK 1M for 2.4G */
3335*4882a593Smuzhiyun SET_TX_DESC_RTS_RTY_LOWEST_RATE_8822C(ptxdesc, 0);
3336*4882a593Smuzhiyun }
3337*4882a593Smuzhiyun }
3338*4882a593Smuzhiyun
rtl8822c_bw_mapping(PADAPTER adapter,struct pkt_attrib * pattrib)3339*4882a593Smuzhiyun u8 rtl8822c_bw_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
3340*4882a593Smuzhiyun {
3341*4882a593Smuzhiyun u8 BWSettingOfDesc = 0;
3342*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
3343*4882a593Smuzhiyun
3344*4882a593Smuzhiyun
3345*4882a593Smuzhiyun if (hal->current_channel_bw == CHANNEL_WIDTH_80) {
3346*4882a593Smuzhiyun if (pattrib->bwmode == CHANNEL_WIDTH_80)
3347*4882a593Smuzhiyun BWSettingOfDesc = 2;
3348*4882a593Smuzhiyun else if (pattrib->bwmode == CHANNEL_WIDTH_40)
3349*4882a593Smuzhiyun BWSettingOfDesc = 1;
3350*4882a593Smuzhiyun else
3351*4882a593Smuzhiyun BWSettingOfDesc = 0;
3352*4882a593Smuzhiyun } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {
3353*4882a593Smuzhiyun if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80))
3354*4882a593Smuzhiyun BWSettingOfDesc = 1;
3355*4882a593Smuzhiyun else
3356*4882a593Smuzhiyun BWSettingOfDesc = 0;
3357*4882a593Smuzhiyun } else
3358*4882a593Smuzhiyun BWSettingOfDesc = 0;
3359*4882a593Smuzhiyun
3360*4882a593Smuzhiyun return BWSettingOfDesc;
3361*4882a593Smuzhiyun }
3362*4882a593Smuzhiyun
rtl8822c_sc_mapping(PADAPTER adapter,struct pkt_attrib * pattrib)3363*4882a593Smuzhiyun u8 rtl8822c_sc_mapping(PADAPTER adapter, struct pkt_attrib *pattrib)
3364*4882a593Smuzhiyun {
3365*4882a593Smuzhiyun u8 SCSettingOfDesc = 0;
3366*4882a593Smuzhiyun PHAL_DATA_TYPE hal = GET_HAL_DATA(adapter);
3367*4882a593Smuzhiyun
3368*4882a593Smuzhiyun
3369*4882a593Smuzhiyun if (hal->current_channel_bw == CHANNEL_WIDTH_80) {
3370*4882a593Smuzhiyun if (pattrib->bwmode == CHANNEL_WIDTH_80)
3371*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3372*4882a593Smuzhiyun else if (pattrib->bwmode == CHANNEL_WIDTH_40) {
3373*4882a593Smuzhiyun if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3374*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ;
3375*4882a593Smuzhiyun else if (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3376*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ;
3377*4882a593Smuzhiyun else
3378*4882a593Smuzhiyun RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
3379*4882a593Smuzhiyun } else {
3380*4882a593Smuzhiyun if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
3381*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
3382*4882a593Smuzhiyun else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER))
3383*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3384*4882a593Smuzhiyun else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
3385*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3386*4882a593Smuzhiyun else if ((hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (hal->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER))
3387*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
3388*4882a593Smuzhiyun else
3389*4882a593Smuzhiyun RTW_INFO("SCMapping: DONOT CARE Mode Setting\n");
3390*4882a593Smuzhiyun }
3391*4882a593Smuzhiyun } else if (hal->current_channel_bw == CHANNEL_WIDTH_40) {
3392*4882a593Smuzhiyun if (pattrib->bwmode == CHANNEL_WIDTH_40)
3393*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3394*4882a593Smuzhiyun else if (pattrib->bwmode == CHANNEL_WIDTH_20) {
3395*4882a593Smuzhiyun if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3396*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ;
3397*4882a593Smuzhiyun else if (hal->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3398*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ;
3399*4882a593Smuzhiyun else
3400*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3401*4882a593Smuzhiyun }
3402*4882a593Smuzhiyun } else
3403*4882a593Smuzhiyun SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE;
3404*4882a593Smuzhiyun
3405*4882a593Smuzhiyun return SCSettingOfDesc;
3406*4882a593Smuzhiyun }
3407*4882a593Smuzhiyun
rtl8822c_fill_txdesc_phy(PADAPTER adapter,struct pkt_attrib * pattrib,u8 * ptxdesc)3408*4882a593Smuzhiyun void rtl8822c_fill_txdesc_phy(PADAPTER adapter, struct pkt_attrib *pattrib, u8 *ptxdesc)
3409*4882a593Smuzhiyun {
3410*4882a593Smuzhiyun if (pattrib->ht_en) {
3411*4882a593Smuzhiyun /* Set Bandwidth and sub-channel settings. */
3412*4882a593Smuzhiyun SET_TX_DESC_DATA_BW_8822C(ptxdesc, rtl8822c_bw_mapping(adapter, pattrib));
3413*4882a593Smuzhiyun SET_TX_DESC_DATA_SC_8822C(ptxdesc, rtl8822c_sc_mapping(adapter, pattrib));
3414*4882a593Smuzhiyun }
3415*4882a593Smuzhiyun }
3416*4882a593Smuzhiyun
3417*4882a593Smuzhiyun /**
3418*4882a593Smuzhiyun * rtl8822c_fill_txdesc_tx_rate() - Set rate in tx description
3419*4882a593Smuzhiyun * @adapter struct _ADAPTER*
3420*4882a593Smuzhiyun * @attrib packet attribute
3421*4882a593Smuzhiyun * @rate DESC_RATE*
3422*4882a593Smuzhiyun * @shrt 1/0 means short/long PLCP for CCK, short/long GI for HT/VHT
3423*4882a593Smuzhiyun * @fallback enable rate fallback or not
3424*4882a593Smuzhiyun * @desc buffer of tx description
3425*4882a593Smuzhiyun *
3426*4882a593Smuzhiyun * Fill rate related fields of tx description when driver want to use specific
3427*4882a593Smuzhiyun * data rate to send this packet.
3428*4882a593Smuzhiyun */
rtl8822c_fill_txdesc_tx_rate(struct _ADAPTER * adapter,struct pkt_attrib * attrib,u8 rate,u8 shrt,u8 fallback,u8 * desc)3429*4882a593Smuzhiyun static void rtl8822c_fill_txdesc_tx_rate(struct _ADAPTER *adapter,
3430*4882a593Smuzhiyun struct pkt_attrib *attrib,
3431*4882a593Smuzhiyun u8 rate, u8 shrt, u8 fallback, u8 *desc)
3432*4882a593Smuzhiyun {
3433*4882a593Smuzhiyun u8 disfb;
3434*4882a593Smuzhiyun u8 bw;
3435*4882a593Smuzhiyun
3436*4882a593Smuzhiyun
3437*4882a593Smuzhiyun rate = rate & 0x7F;
3438*4882a593Smuzhiyun shrt = shrt ? 1 : 0;
3439*4882a593Smuzhiyun disfb = fallback ? 0 : 1;
3440*4882a593Smuzhiyun
3441*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(desc, 1);
3442*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(desc, rate);
3443*4882a593Smuzhiyun SET_TX_DESC_DATA_SHORT_8822C(desc, shrt);
3444*4882a593Smuzhiyun SET_TX_DESC_DISDATAFB_8822C(desc, disfb);
3445*4882a593Smuzhiyun
3446*4882a593Smuzhiyun /* HT MCS rate can't support bandwidth higher than 40MHz */
3447*4882a593Smuzhiyun bw = GET_TX_DESC_DATA_BW_8822C(desc);
3448*4882a593Smuzhiyun if (((rate >= DESC_RATEMCS0) && (rate <= DESC_RATEMCS31)) && (bw > 1)) {
3449*4882a593Smuzhiyun RTW_WARN(FUNC_ADPT_FMT ": Use HT rate(%s) on bandwidth "
3450*4882a593Smuzhiyun "higher than 40MHz(%u>%u) is illegal, "
3451*4882a593Smuzhiyun "switch bandwidth to 40MHz!\n",
3452*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter),
3453*4882a593Smuzhiyun HDATA_RATE(rate), attrib->bwmode,
3454*4882a593Smuzhiyun CHANNEL_WIDTH_40);
3455*4882a593Smuzhiyun
3456*4882a593Smuzhiyun if (attrib->bwmode > CHANNEL_WIDTH_40)
3457*4882a593Smuzhiyun attrib->bwmode = CHANNEL_WIDTH_40;
3458*4882a593Smuzhiyun rtl8822c_fill_txdesc_phy(adapter, attrib, desc);
3459*4882a593Smuzhiyun }
3460*4882a593Smuzhiyun }
3461*4882a593Smuzhiyun
rtl8822c_fill_txdesc_force_bmc_camid(struct pkt_attrib * pattrib,u8 * ptxdesc)3462*4882a593Smuzhiyun void rtl8822c_fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc)
3463*4882a593Smuzhiyun {
3464*4882a593Smuzhiyun if ((pattrib->encrypt > 0) && (!pattrib->bswenc)
3465*4882a593Smuzhiyun && (pattrib->bmc_camid != INVALID_SEC_MAC_CAM_ID)) {
3466*4882a593Smuzhiyun SET_TX_DESC_EN_DESC_ID_8822C(ptxdesc, 1);
3467*4882a593Smuzhiyun SET_TX_DESC_MACID_8822C(ptxdesc, pattrib->bmc_camid);
3468*4882a593Smuzhiyun }
3469*4882a593Smuzhiyun }
3470*4882a593Smuzhiyun
rtl8822c_fill_txdesc_bmc_tx_rate(struct pkt_attrib * pattrib,u8 * ptxdesc)3471*4882a593Smuzhiyun void rtl8822c_fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc)
3472*4882a593Smuzhiyun {
3473*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(ptxdesc, 1);
3474*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(ptxdesc, MRateToHwRate(pattrib->rate));
3475*4882a593Smuzhiyun SET_TX_DESC_DISDATAFB_8822C(ptxdesc, 1);
3476*4882a593Smuzhiyun }
3477*4882a593Smuzhiyun
3478*4882a593Smuzhiyun /*
3479*4882a593Smuzhiyun * Description:
3480*4882a593Smuzhiyun * Fill tx description for beamforming packets
3481*4882a593Smuzhiyun */
rtl8822c_fill_txdesc_bf(struct xmit_frame * frame,u8 * desc)3482*4882a593Smuzhiyun void rtl8822c_fill_txdesc_bf(struct xmit_frame *frame, u8 *desc)
3483*4882a593Smuzhiyun {
3484*4882a593Smuzhiyun #ifndef CONFIG_BEAMFORMING
3485*4882a593Smuzhiyun return;
3486*4882a593Smuzhiyun #else /* CONFIG_BEAMFORMING */
3487*4882a593Smuzhiyun struct pkt_attrib *attrib;
3488*4882a593Smuzhiyun struct _ADAPTER *padapter = frame->padapter;
3489*4882a593Smuzhiyun struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
3490*4882a593Smuzhiyun u8 init_rate;
3491*4882a593Smuzhiyun
3492*4882a593Smuzhiyun attrib = &frame->attrib;
3493*4882a593Smuzhiyun init_rate = pHalData->INIDATA_RATE[attrib->mac_id] & 0x7F;
3494*4882a593Smuzhiyun
3495*4882a593Smuzhiyun SET_TX_DESC_G_ID_8822C(desc, attrib->txbf_g_id);
3496*4882a593Smuzhiyun SET_TX_DESC_P_AID_8822C(desc, attrib->txbf_p_aid);
3497*4882a593Smuzhiyun
3498*4882a593Smuzhiyun SET_TX_DESC_MU_DATARATE_8822C(desc, init_rate);
3499*4882a593Smuzhiyun /*SET_TX_DESC_MU_RC_8822C(desc, 0);*/
3500*4882a593Smuzhiyun
3501*4882a593Smuzhiyun /* Force to disable STBC when txbf is enabled */
3502*4882a593Smuzhiyun if (attrib->txbf_p_aid && attrib->stbc)
3503*4882a593Smuzhiyun SET_TX_DESC_DATA_STBC_8822C(desc, 0);
3504*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */
3505*4882a593Smuzhiyun }
3506*4882a593Smuzhiyun
3507*4882a593Smuzhiyun /*
3508*4882a593Smuzhiyun * Description:
3509*4882a593Smuzhiyun * Fill tx description for beamformer,
3510*4882a593Smuzhiyun * include following management packets:
3511*4882a593Smuzhiyun * 1. VHT NDPA
3512*4882a593Smuzhiyun * 2. HT NDPA
3513*4882a593Smuzhiyun * 3. Beamforming Report Poll
3514*4882a593Smuzhiyun */
rtl8822c_fill_txdesc_mgnt_bf(struct xmit_frame * frame,u8 * desc)3515*4882a593Smuzhiyun void rtl8822c_fill_txdesc_mgnt_bf(struct xmit_frame *frame, u8 *desc)
3516*4882a593Smuzhiyun {
3517*4882a593Smuzhiyun #ifndef CONFIG_BEAMFORMING
3518*4882a593Smuzhiyun return;
3519*4882a593Smuzhiyun #else /* CONFIG_BEAMFORMING */
3520*4882a593Smuzhiyun PADAPTER adapter;
3521*4882a593Smuzhiyun struct pkt_attrib *attrib;
3522*4882a593Smuzhiyun u8 ndpa = 0;
3523*4882a593Smuzhiyun u8 ht_ndpa = 0;
3524*4882a593Smuzhiyun u8 report_poll = 0;
3525*4882a593Smuzhiyun
3526*4882a593Smuzhiyun
3527*4882a593Smuzhiyun adapter = frame->padapter;
3528*4882a593Smuzhiyun attrib = &frame->attrib;
3529*4882a593Smuzhiyun
3530*4882a593Smuzhiyun if (attrib->subtype == WIFI_NDPA)
3531*4882a593Smuzhiyun ndpa = 1;
3532*4882a593Smuzhiyun if ((attrib->subtype == WIFI_ACTION_NOACK) && (attrib->order == 1))
3533*4882a593Smuzhiyun ht_ndpa = 1;
3534*4882a593Smuzhiyun if (attrib->subtype == WIFI_BF_REPORT_POLL)
3535*4882a593Smuzhiyun report_poll = 1;
3536*4882a593Smuzhiyun
3537*4882a593Smuzhiyun if ((!ndpa) && (!ht_ndpa) && (!report_poll))
3538*4882a593Smuzhiyun return;
3539*4882a593Smuzhiyun
3540*4882a593Smuzhiyun /*SET_TX_DESC_TXPKTSIZE_8822C(desc, pattrib->last_txcmdsz);*/
3541*4882a593Smuzhiyun /*SET_TX_DESC_OFFSET_8822C(desc, HALMAC_TX_DESC_SIZE_8822C);*/
3542*4882a593Smuzhiyun SET_TX_DESC_DISRTSFB_8822C(desc, 1);
3543*4882a593Smuzhiyun SET_TX_DESC_DISDATAFB(desc, 1);
3544*4882a593Smuzhiyun /*SET_TX_DESC_SW_SEQ_8822C(desc, pattrib->seqnum);*/
3545*4882a593Smuzhiyun SET_TX_DESC_DATA_BW_8822C(desc, rtl8822c_bw_mapping(adapter, attrib));
3546*4882a593Smuzhiyun SET_TX_DESC_SIGNALING_TA_PKT_SC_8822C(desc,
3547*4882a593Smuzhiyun rtl8822c_sc_mapping(adapter, attrib));
3548*4882a593Smuzhiyun /*SET_TX_DESC_RTY_LMT_EN_8822C(ptxdesc, 1);*/
3549*4882a593Smuzhiyun SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(desc, 5);
3550*4882a593Smuzhiyun SET_TX_DESC_NDPA_8822C(desc, 1);
3551*4882a593Smuzhiyun SET_TX_DESC_NAVUSEHDR_8822C(desc, 1);
3552*4882a593Smuzhiyun /*SET_TX_DESC_QSEL_8822C(desc, QSLT_MGNT);*/
3553*4882a593Smuzhiyun /*
3554*4882a593Smuzhiyun * NSS2MCS0 for VHT
3555*4882a593Smuzhiyun * MCS8 for HT
3556*4882a593Smuzhiyun */
3557*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(desc, MRateToHwRate(attrib->rate));
3558*4882a593Smuzhiyun /*SET_TX_DESC_USE_RATE_8822C(desc, 1);*/
3559*4882a593Smuzhiyun /*SET_TX_DESC_MACID_8822C(desc, pattrib->mac_id);*/ /* ad-hoc mode */
3560*4882a593Smuzhiyun /*SET_TX_DESC_G_ID_8822C(desc, 63);*/
3561*4882a593Smuzhiyun /*
3562*4882a593Smuzhiyun * partial AID of 1st STA, at infrastructure mode, either SU or MU;
3563*4882a593Smuzhiyun * MACID, at ad-hoc mode
3564*4882a593Smuzhiyun *
3565*4882a593Smuzhiyun * For WMAC to restore the received CSI report of STA1.
3566*4882a593Smuzhiyun * WMAC would set p_aid field to 0 in PLCP header for MU.
3567*4882a593Smuzhiyun */
3568*4882a593Smuzhiyun /*SET_TX_DESC_P_AID_8822C(desc, pattrib->txbf_p_aid);*/
3569*4882a593Smuzhiyun SET_TX_DESC_SND_PKT_SEL_8822C(desc, attrib->bf_pkt_type);
3570*4882a593Smuzhiyun #endif /* CONFIG_BEAMFORMING */
3571*4882a593Smuzhiyun }
3572*4882a593Smuzhiyun
rtl8822c_cal_txdesc_chksum(PADAPTER adapter,u8 * ptxdesc)3573*4882a593Smuzhiyun void rtl8822c_cal_txdesc_chksum(PADAPTER adapter, u8 *ptxdesc)
3574*4882a593Smuzhiyun {
3575*4882a593Smuzhiyun struct halmac_adapter *halmac;
3576*4882a593Smuzhiyun struct halmac_api *api;
3577*4882a593Smuzhiyun
3578*4882a593Smuzhiyun
3579*4882a593Smuzhiyun halmac = adapter_to_halmac(adapter);
3580*4882a593Smuzhiyun api = HALMAC_GET_API(halmac);
3581*4882a593Smuzhiyun
3582*4882a593Smuzhiyun api->halmac_fill_txdesc_checksum(halmac, ptxdesc);
3583*4882a593Smuzhiyun }
3584*4882a593Smuzhiyun
3585*4882a593Smuzhiyun
3586*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED
rtl8822c_prepare_mp_txdesc(PADAPTER adapter,struct mp_priv * pmp_priv)3587*4882a593Smuzhiyun void rtl8822c_prepare_mp_txdesc(PADAPTER adapter, struct mp_priv *pmp_priv)
3588*4882a593Smuzhiyun {
3589*4882a593Smuzhiyun u8 *desc;
3590*4882a593Smuzhiyun struct pkt_attrib *attrib;
3591*4882a593Smuzhiyun u32 pkt_size;
3592*4882a593Smuzhiyun s32 bmcast;
3593*4882a593Smuzhiyun u32 desc_size;
3594*4882a593Smuzhiyun u8 data_rate, pwr_status, offset;
3595*4882a593Smuzhiyun
3596*4882a593Smuzhiyun
3597*4882a593Smuzhiyun desc = pmp_priv->tx.desc;
3598*4882a593Smuzhiyun attrib = &pmp_priv->tx.attrib;
3599*4882a593Smuzhiyun pkt_size = attrib->last_txcmdsz;
3600*4882a593Smuzhiyun bmcast = IS_MCAST(attrib->ra);
3601*4882a593Smuzhiyun desc_size = rtl8822c_get_tx_desc_size(adapter);
3602*4882a593Smuzhiyun
3603*4882a593Smuzhiyun SET_TX_DESC_LS_8822C(desc, 1);
3604*4882a593Smuzhiyun SET_TX_DESC_TXPKTSIZE_8822C(desc, pkt_size);
3605*4882a593Smuzhiyun
3606*4882a593Smuzhiyun offset = desc_size;
3607*4882a593Smuzhiyun SET_TX_DESC_OFFSET_8822C(desc, offset);
3608*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
3609*4882a593Smuzhiyun SET_TX_DESC_PKT_OFFSET_8822C(desc, 0); /* 8822CE pkt_offset is 0 */
3610*4882a593Smuzhiyun #else
3611*4882a593Smuzhiyun SET_TX_DESC_PKT_OFFSET_8822C(desc, 1);
3612*4882a593Smuzhiyun #endif
3613*4882a593Smuzhiyun
3614*4882a593Smuzhiyun if (bmcast)
3615*4882a593Smuzhiyun SET_TX_DESC_BMC_8822C(desc, 1);
3616*4882a593Smuzhiyun
3617*4882a593Smuzhiyun SET_TX_DESC_MACID_8822C(desc, attrib->mac_id);
3618*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(desc, attrib->raid);
3619*4882a593Smuzhiyun SET_TX_DESC_QSEL_8822C(desc, attrib->qsel);
3620*4882a593Smuzhiyun
3621*4882a593Smuzhiyun if (pmp_priv->preamble)
3622*4882a593Smuzhiyun SET_TX_DESC_DATA_SHORT_8822C(desc, 1);
3623*4882a593Smuzhiyun
3624*4882a593Smuzhiyun if (!attrib->qos_en)
3625*4882a593Smuzhiyun SET_TX_DESC_EN_HWSEQ_8822C(desc, 1);
3626*4882a593Smuzhiyun else
3627*4882a593Smuzhiyun SET_TX_DESC_SW_SEQ_8822C(desc, attrib->seqnum);
3628*4882a593Smuzhiyun
3629*4882a593Smuzhiyun if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
3630*4882a593Smuzhiyun SET_TX_DESC_DATA_BW_8822C(desc, pmp_priv->bandwidth);
3631*4882a593Smuzhiyun else {
3632*4882a593Smuzhiyun RTW_ERR("%s: unknown bandwidth %d, use 20M\n",
3633*4882a593Smuzhiyun __FUNCTION__, pmp_priv->bandwidth);
3634*4882a593Smuzhiyun SET_TX_DESC_DATA_BW_8822C(desc, CHANNEL_WIDTH_20);
3635*4882a593Smuzhiyun }
3636*4882a593Smuzhiyun
3637*4882a593Smuzhiyun SET_TX_DESC_DISDATAFB_8822C(desc, 1);
3638*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(desc, 1);
3639*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(desc, pmp_priv->rateidx);
3640*4882a593Smuzhiyun }
3641*4882a593Smuzhiyun #endif /* CONFIG_MP_INCLUDED */
3642*4882a593Smuzhiyun
fill_default_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)3643*4882a593Smuzhiyun static void fill_default_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
3644*4882a593Smuzhiyun {
3645*4882a593Smuzhiyun PADAPTER adapter;
3646*4882a593Smuzhiyun PHAL_DATA_TYPE hal;
3647*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext;
3648*4882a593Smuzhiyun struct mlme_ext_info *pmlmeinfo;
3649*4882a593Smuzhiyun struct pkt_attrib *pattrib;
3650*4882a593Smuzhiyun s32 bmcst;
3651*4882a593Smuzhiyun u32 desc_size;
3652*4882a593Smuzhiyun u8 hw_port;
3653*4882a593Smuzhiyun
3654*4882a593Smuzhiyun adapter = pxmitframe->padapter;
3655*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
3656*4882a593Smuzhiyun pmlmeext = &adapter->mlmeextpriv;
3657*4882a593Smuzhiyun pmlmeinfo = &(pmlmeext->mlmext_info);
3658*4882a593Smuzhiyun
3659*4882a593Smuzhiyun pattrib = &pxmitframe->attrib;
3660*4882a593Smuzhiyun bmcst = IS_MCAST(pattrib->ra);
3661*4882a593Smuzhiyun hw_port = rtw_hal_get_port(adapter);
3662*4882a593Smuzhiyun
3663*4882a593Smuzhiyun desc_size = rtl8822c_get_tx_desc_size(adapter);
3664*4882a593Smuzhiyun _rtw_memset(pbuf, 0, desc_size);
3665*4882a593Smuzhiyun
3666*4882a593Smuzhiyun if (pxmitframe->frame_tag == DATA_FRAMETAG) {
3667*4882a593Smuzhiyun u8 drv_userate = 0;
3668*4882a593Smuzhiyun
3669*4882a593Smuzhiyun SET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);
3670*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);
3671*4882a593Smuzhiyun SET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);
3672*4882a593Smuzhiyun SET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);
3673*4882a593Smuzhiyun
3674*4882a593Smuzhiyun rtl8822c_fill_txdesc_sectype(pattrib, pbuf);
3675*4882a593Smuzhiyun rtl8822c_fill_txdesc_vcs(adapter, pattrib, pbuf);
3676*4882a593Smuzhiyun
3677*4882a593Smuzhiyun if (bmcst)
3678*4882a593Smuzhiyun rtl8822c_fill_txdesc_force_bmc_camid(pattrib, pbuf);
3679*4882a593Smuzhiyun
3680*4882a593Smuzhiyun #ifdef CONFIG_P2P
3681*4882a593Smuzhiyun if (!rtw_p2p_chk_state(&adapter->wdinfo, P2P_STATE_NONE)) {
3682*4882a593Smuzhiyun if (pattrib->icmp_pkt == 1 && adapter->registrypriv.wifi_spec == 1)
3683*4882a593Smuzhiyun drv_userate = 1;
3684*4882a593Smuzhiyun }
3685*4882a593Smuzhiyun #endif
3686*4882a593Smuzhiyun
3687*4882a593Smuzhiyun if ((pattrib->ether_type != 0x888e) &&
3688*4882a593Smuzhiyun (pattrib->ether_type != 0x0806) &&
3689*4882a593Smuzhiyun (pattrib->ether_type != 0x88B4) &&
3690*4882a593Smuzhiyun (pattrib->dhcp_pkt != 1) &&
3691*4882a593Smuzhiyun (drv_userate != 1)
3692*4882a593Smuzhiyun #ifdef CONFIG_AUTO_AP_MODE
3693*4882a593Smuzhiyun && (pattrib->pctrl != _TRUE)
3694*4882a593Smuzhiyun #endif
3695*4882a593Smuzhiyun ) {
3696*4882a593Smuzhiyun /* Non EAP & ARP & DHCP type data packet */
3697*4882a593Smuzhiyun
3698*4882a593Smuzhiyun if (pattrib->ampdu_en == _TRUE) {
3699*4882a593Smuzhiyun SET_TX_DESC_AGG_EN_8822C(pbuf, 1);
3700*4882a593Smuzhiyun SET_TX_DESC_MAX_AGG_NUM_8822C(pbuf, 0x1F);
3701*4882a593Smuzhiyun SET_TX_DESC_AMPDU_DENSITY_8822C(pbuf, pattrib->ampdu_spacing);
3702*4882a593Smuzhiyun } else
3703*4882a593Smuzhiyun SET_TX_DESC_BK_8822C(pbuf, 1);
3704*4882a593Smuzhiyun
3705*4882a593Smuzhiyun rtl8822c_fill_txdesc_phy(adapter, pattrib, pbuf);
3706*4882a593Smuzhiyun
3707*4882a593Smuzhiyun /* compatibility for MCC consideration, use pmlmeext->cur_channel */
3708*4882a593Smuzhiyun if (!bmcst) {
3709*4882a593Smuzhiyun if (pmlmeext->cur_channel > 14)
3710*4882a593Smuzhiyun /* for 5G, OFDM 6M */
3711*4882a593Smuzhiyun SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(pbuf, 4);
3712*4882a593Smuzhiyun else
3713*4882a593Smuzhiyun /* for 2.4G, CCK 1M */
3714*4882a593Smuzhiyun SET_TX_DESC_DATA_RTY_LOWEST_RATE_8822C(pbuf, 0);
3715*4882a593Smuzhiyun }
3716*4882a593Smuzhiyun
3717*4882a593Smuzhiyun if (hal->fw_ractrl == _FALSE)
3718*4882a593Smuzhiyun rtl8822c_fill_txdesc_tx_rate(adapter, pattrib,
3719*4882a593Smuzhiyun hal->INIDATA_RATE[pattrib->mac_id] & 0x7F,
3720*4882a593Smuzhiyun hal->INIDATA_RATE[pattrib->mac_id] & BIT(7) ? 1 : 0,
3721*4882a593Smuzhiyun 1, pbuf);
3722*4882a593Smuzhiyun
3723*4882a593Smuzhiyun if (bmcst) {
3724*4882a593Smuzhiyun SET_TX_DESC_SW_DEFINE_8822C(pbuf, 0x01);
3725*4882a593Smuzhiyun rtl8822c_fill_txdesc_bmc_tx_rate(pattrib, pbuf);
3726*4882a593Smuzhiyun }
3727*4882a593Smuzhiyun
3728*4882a593Smuzhiyun /* modify data rate by iwpriv */
3729*4882a593Smuzhiyun if (adapter->fix_rate != 0xFF)
3730*4882a593Smuzhiyun rtl8822c_fill_txdesc_tx_rate(adapter, pattrib,
3731*4882a593Smuzhiyun adapter->fix_rate & 0x7F,
3732*4882a593Smuzhiyun adapter->fix_rate & BIT(7) ? 1 : 0,
3733*4882a593Smuzhiyun adapter->data_fb, pbuf);
3734*4882a593Smuzhiyun
3735*4882a593Smuzhiyun if (pattrib->ldpc)
3736*4882a593Smuzhiyun SET_TX_DESC_DATA_LDPC_8822C(pbuf, 1);
3737*4882a593Smuzhiyun if (pattrib->stbc)
3738*4882a593Smuzhiyun SET_TX_DESC_DATA_STBC_8822C(pbuf, 1);
3739*4882a593Smuzhiyun
3740*4882a593Smuzhiyun #ifdef CONFIG_CMCC_TEST
3741*4882a593Smuzhiyun SET_TX_DESC_DATA_SHORT_8822C(pbuf, 1); /* use cck short premble */
3742*4882a593Smuzhiyun #endif
3743*4882a593Smuzhiyun
3744*4882a593Smuzhiyun #ifdef CONFIG_WMMPS_STA
3745*4882a593Smuzhiyun if (pattrib->trigger_frame)
3746*4882a593Smuzhiyun SET_TX_DESC_TRI_FRAME_8822C (pbuf, 1);
3747*4882a593Smuzhiyun #endif /* CONFIG_WMMPS_STA */
3748*4882a593Smuzhiyun
3749*4882a593Smuzhiyun } else {
3750*4882a593Smuzhiyun /*
3751*4882a593Smuzhiyun * EAP data packet and ARP packet.
3752*4882a593Smuzhiyun * Use the 1M data rate to send the EAP/ARP packet.
3753*4882a593Smuzhiyun * This will maybe make the handshake smooth.
3754*4882a593Smuzhiyun */
3755*4882a593Smuzhiyun
3756*4882a593Smuzhiyun SET_TX_DESC_BK_8822C(pbuf, 1);
3757*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(pbuf, 1);
3758*4882a593Smuzhiyun if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
3759*4882a593Smuzhiyun SET_TX_DESC_DATA_SHORT_8822C(pbuf, 1);
3760*4882a593Smuzhiyun #ifdef CONFIG_IP_R_MONITOR
3761*4882a593Smuzhiyun if((pattrib->ether_type == ETH_P_ARP) &&
3762*4882a593Smuzhiyun (IsSupportedTxOFDM(adapter->registrypriv.wireless_mode)))
3763*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(IEEE80211_OFDM_RATE_6MB));
3764*4882a593Smuzhiyun else
3765*4882a593Smuzhiyun #endif/*CONFIG_IP_R_MONITOR*/
3766*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pmlmeext->tx_rate));
3767*4882a593Smuzhiyun
3768*4882a593Smuzhiyun RTW_INFO(FUNC_ADPT_FMT ": SP Packet(0x%04X) rate=0x%x SeqNum = %d\n",
3769*4882a593Smuzhiyun FUNC_ADPT_ARG(adapter), pattrib->ether_type, MRateToHwRate(pmlmeext->tx_rate), pattrib->seqnum);
3770*4882a593Smuzhiyun }
3771*4882a593Smuzhiyun
3772*4882a593Smuzhiyun #if defined(CONFIG_USB_TX_AGGREGATION) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
3773*4882a593Smuzhiyun SET_TX_DESC_DMA_TXAGG_NUM_8822C(pbuf, pxmitframe->agg_num);
3774*4882a593Smuzhiyun #endif
3775*4882a593Smuzhiyun
3776*4882a593Smuzhiyun #ifdef CONFIG_TDLS
3777*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK
3778*4882a593Smuzhiyun /* CCX-TXRPT ack for xmit mgmt frames. */
3779*4882a593Smuzhiyun if (pxmitframe->ack_report) {
3780*4882a593Smuzhiyun #ifdef DBG_CCX
3781*4882a593Smuzhiyun RTW_INFO("%s set spe_rpt\n", __func__);
3782*4882a593Smuzhiyun #endif
3783*4882a593Smuzhiyun SET_TX_DESC_SPE_RPT_8822C(pbuf, 1);
3784*4882a593Smuzhiyun SET_TX_DESC_SW_DEFINE_8822C(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));
3785*4882a593Smuzhiyun }
3786*4882a593Smuzhiyun #endif /* CONFIG_XMIT_ACK */
3787*4882a593Smuzhiyun #endif
3788*4882a593Smuzhiyun } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
3789*4882a593Smuzhiyun SET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);
3790*4882a593Smuzhiyun SET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);
3791*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);
3792*4882a593Smuzhiyun SET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);
3793*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(pbuf, 1);
3794*4882a593Smuzhiyun
3795*4882a593Smuzhiyun SET_TX_DESC_MBSSID_8822C(pbuf, pattrib->mbssid & 0xF);
3796*4882a593Smuzhiyun
3797*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pattrib->rate));
3798*4882a593Smuzhiyun
3799*4882a593Smuzhiyun SET_TX_DESC_RTY_LMT_EN_8822C(pbuf, 1);
3800*4882a593Smuzhiyun if (pattrib->retry_ctrl == _TRUE)
3801*4882a593Smuzhiyun SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pbuf, 6);
3802*4882a593Smuzhiyun else
3803*4882a593Smuzhiyun SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pbuf, 12);
3804*4882a593Smuzhiyun
3805*4882a593Smuzhiyun rtl8822c_fill_txdesc_mgnt_bf(pxmitframe, pbuf);
3806*4882a593Smuzhiyun
3807*4882a593Smuzhiyun #ifdef CONFIG_XMIT_ACK
3808*4882a593Smuzhiyun /* CCX-TXRPT ack for xmit mgmt frames. */
3809*4882a593Smuzhiyun if (pxmitframe->ack_report) {
3810*4882a593Smuzhiyun #ifdef DBG_CCX
3811*4882a593Smuzhiyun RTW_INFO("%s set spe_rpt\n", __FUNCTION__);
3812*4882a593Smuzhiyun #endif
3813*4882a593Smuzhiyun SET_TX_DESC_SPE_RPT_8822C(pbuf, 1);
3814*4882a593Smuzhiyun SET_TX_DESC_SW_DEFINE_8822C(pbuf, (u8)(GET_PRIMARY_ADAPTER(adapter)->xmitpriv.seq_no));
3815*4882a593Smuzhiyun }
3816*4882a593Smuzhiyun #endif /* CONFIG_XMIT_ACK */
3817*4882a593Smuzhiyun } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG)
3818*4882a593Smuzhiyun RTW_INFO("%s: TXAGG_FRAMETAG\n", __FUNCTION__);
3819*4882a593Smuzhiyun #ifdef CONFIG_MP_INCLUDED
3820*4882a593Smuzhiyun else if (pxmitframe->frame_tag == MP_FRAMETAG) {
3821*4882a593Smuzhiyun RTW_DBG("%s: MP_FRAMETAG\n", __FUNCTION__);
3822*4882a593Smuzhiyun fill_txdesc_for_mp(adapter, pbuf);
3823*4882a593Smuzhiyun }
3824*4882a593Smuzhiyun #endif
3825*4882a593Smuzhiyun else {
3826*4882a593Smuzhiyun RTW_INFO("%s: frame_tag=0x%x\n", __FUNCTION__, pxmitframe->frame_tag);
3827*4882a593Smuzhiyun
3828*4882a593Smuzhiyun SET_TX_DESC_MACID_8822C(pbuf, pattrib->mac_id);
3829*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(pbuf, pattrib->raid);
3830*4882a593Smuzhiyun SET_TX_DESC_QSEL_8822C(pbuf, pattrib->qsel);
3831*4882a593Smuzhiyun SET_TX_DESC_SW_SEQ_8822C(pbuf, pattrib->seqnum);
3832*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(pbuf, 1);
3833*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(pbuf, MRateToHwRate(pmlmeext->tx_rate));
3834*4882a593Smuzhiyun }
3835*4882a593Smuzhiyun
3836*4882a593Smuzhiyun SET_TX_DESC_TXPKTSIZE_8822C(pbuf, pattrib->last_txcmdsz);
3837*4882a593Smuzhiyun
3838*4882a593Smuzhiyun {
3839*4882a593Smuzhiyun u8 pkt_offset, offset;
3840*4882a593Smuzhiyun
3841*4882a593Smuzhiyun pkt_offset = 0;
3842*4882a593Smuzhiyun offset = desc_size;
3843*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
3844*4882a593Smuzhiyun pkt_offset = pxmitframe->pkt_offset;
3845*4882a593Smuzhiyun offset += (pxmitframe->pkt_offset >> 3);
3846*4882a593Smuzhiyun #endif /* CONFIG_USB_HCI */
3847*4882a593Smuzhiyun
3848*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE
3849*4882a593Smuzhiyun if (pxmitframe->frame_tag == DATA_FRAMETAG) {
3850*4882a593Smuzhiyun pkt_offset = 1;
3851*4882a593Smuzhiyun offset += EARLY_MODE_INFO_SIZE;
3852*4882a593Smuzhiyun }
3853*4882a593Smuzhiyun #endif /* CONFIG_TX_EARLY_MODE */
3854*4882a593Smuzhiyun
3855*4882a593Smuzhiyun SET_TX_DESC_PKT_OFFSET_8822C(pbuf, pkt_offset);
3856*4882a593Smuzhiyun SET_TX_DESC_OFFSET_8822C(pbuf, offset);
3857*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
3858*4882a593Smuzhiyun if (pattrib->hw_csum == 1) {
3859*4882a593Smuzhiyun int offset = 48 + pkt_offset*8 + 24;
3860*4882a593Smuzhiyun
3861*4882a593Smuzhiyun SET_TX_DESC_OFFSET_8822C(pbuf, offset);
3862*4882a593Smuzhiyun SET_TX_DESC_CHK_EN_8822C(pbuf, 1);
3863*4882a593Smuzhiyun SET_TX_DESC_WHEADER_LEN_8822C(pbuf, (pattrib->hdrlen + pattrib->iv_len + XATTRIB_GET_MCTRL_LEN(pattrib))>>1);
3864*4882a593Smuzhiyun }
3865*4882a593Smuzhiyun #endif
3866*4882a593Smuzhiyun }
3867*4882a593Smuzhiyun
3868*4882a593Smuzhiyun if (bmcst)
3869*4882a593Smuzhiyun SET_TX_DESC_BMC_8822C(pbuf, 1);
3870*4882a593Smuzhiyun
3871*4882a593Smuzhiyun /*
3872*4882a593Smuzhiyun * 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS.
3873*4882a593Smuzhiyun * (1) The sequence number of each non-Qos frame / broadcast / multicast /
3874*4882a593Smuzhiyun * mgnt frame should be controlled by Hw because Fw will also send null data
3875*4882a593Smuzhiyun * which we cannot control when Fw LPS enable.
3876*4882a593Smuzhiyun * --> default enable non-Qos data sequense number. 2010.06.23. by tynli.
3877*4882a593Smuzhiyun * (2) Enable HW SEQ control for beacon packet, because we use Hw beacon.
3878*4882a593Smuzhiyun * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets.
3879*4882a593Smuzhiyun * 2010.06.23. Added by tynli.
3880*4882a593Smuzhiyun */
3881*4882a593Smuzhiyun if (!pattrib->qos_en) {
3882*4882a593Smuzhiyun SET_TX_DESC_DISQSELSEQ_8822C(pbuf, 1);
3883*4882a593Smuzhiyun SET_TX_DESC_EN_HWSEQ_8822C(pbuf, 1);
3884*4882a593Smuzhiyun SET_TX_DESC_HW_SSN_SEL_8822C(pbuf, pattrib->hw_ssn_sel);
3885*4882a593Smuzhiyun }
3886*4882a593Smuzhiyun
3887*4882a593Smuzhiyun SET_TX_DESC_PORT_ID_8822C(pbuf, hw_port);
3888*4882a593Smuzhiyun SET_TX_DESC_MULTIPLE_PORT_8822C(pbuf, hw_port);
3889*4882a593Smuzhiyun
3890*4882a593Smuzhiyun #ifdef CONFIG_ANTENNA_DIVERSITY
3891*4882a593Smuzhiyun if (!bmcst && pattrib->psta)
3892*4882a593Smuzhiyun odm_set_tx_ant_by_tx_info(adapter_to_phydm(adapter), pbuf, pattrib->psta->cmn.mac_id);
3893*4882a593Smuzhiyun #endif
3894*4882a593Smuzhiyun
3895*4882a593Smuzhiyun rtl8822c_fill_txdesc_bf(pxmitframe, pbuf);
3896*4882a593Smuzhiyun }
3897*4882a593Smuzhiyun
3898*4882a593Smuzhiyun /*
3899*4882a593Smuzhiyun * Description:
3900*4882a593Smuzhiyun *
3901*4882a593Smuzhiyun * Parameters:
3902*4882a593Smuzhiyun * pxmitframe xmitframe
3903*4882a593Smuzhiyun * pbuf where to fill tx desc
3904*4882a593Smuzhiyun */
rtl8822c_update_txdesc(struct xmit_frame * pxmitframe,u8 * pbuf)3905*4882a593Smuzhiyun void rtl8822c_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
3906*4882a593Smuzhiyun {
3907*4882a593Smuzhiyun fill_default_txdesc(pxmitframe, pbuf);
3908*4882a593Smuzhiyun rtl8822c_cal_txdesc_chksum(pxmitframe->padapter, pbuf);
3909*4882a593Smuzhiyun }
3910*4882a593Smuzhiyun
3911*4882a593Smuzhiyun /*
3912*4882a593Smuzhiyun * Description:
3913*4882a593Smuzhiyun * In normal chip, we should send some packet to HW which will be used by FW
3914*4882a593Smuzhiyun * in FW LPS mode.
3915*4882a593Smuzhiyun * The function is to fill the Tx descriptor of this packets,
3916*4882a593Smuzhiyun * then FW can tell HW to send these packet directly.
3917*4882a593Smuzhiyun */
fill_fake_txdesc(PADAPTER adapter,u8 * pDesc,u32 BufferLen,u8 IsPsPoll,u8 IsBTQosNull,u8 bDataFrame)3918*4882a593Smuzhiyun static void fill_fake_txdesc(PADAPTER adapter, u8 *pDesc, u32 BufferLen,
3919*4882a593Smuzhiyun u8 IsPsPoll, u8 IsBTQosNull, u8 bDataFrame)
3920*4882a593Smuzhiyun {
3921*4882a593Smuzhiyun /* Clear all status */
3922*4882a593Smuzhiyun struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv;
3923*4882a593Smuzhiyun struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
3924*4882a593Smuzhiyun u32 desc_size;
3925*4882a593Smuzhiyun u8 hw_port = rtw_hal_get_port(adapter);
3926*4882a593Smuzhiyun
3927*4882a593Smuzhiyun
3928*4882a593Smuzhiyun desc_size = rtl8822c_get_tx_desc_size(adapter);
3929*4882a593Smuzhiyun _rtw_memset(pDesc, 0, desc_size);
3930*4882a593Smuzhiyun
3931*4882a593Smuzhiyun SET_TX_DESC_LS_8822C(pDesc, 1);
3932*4882a593Smuzhiyun
3933*4882a593Smuzhiyun SET_TX_DESC_OFFSET_8822C(pDesc, desc_size);
3934*4882a593Smuzhiyun
3935*4882a593Smuzhiyun SET_TX_DESC_TXPKTSIZE_8822C(pDesc, BufferLen);
3936*4882a593Smuzhiyun SET_TX_DESC_QSEL_8822C(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
3937*4882a593Smuzhiyun
3938*4882a593Smuzhiyun if (pmlmeext->cur_wireless_mode & WIRELESS_11B)
3939*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(pDesc, RATEID_IDX_B);
3940*4882a593Smuzhiyun else
3941*4882a593Smuzhiyun SET_TX_DESC_RATE_ID_8822C(pDesc, RATEID_IDX_G);
3942*4882a593Smuzhiyun
3943*4882a593Smuzhiyun /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by HW */
3944*4882a593Smuzhiyun if (_TRUE == IsPsPoll)
3945*4882a593Smuzhiyun SET_TX_DESC_NAVUSEHDR_8822C(pDesc, 1);
3946*4882a593Smuzhiyun else {
3947*4882a593Smuzhiyun SET_TX_DESC_DISQSELSEQ_8822C(pDesc, 1);
3948*4882a593Smuzhiyun SET_TX_DESC_EN_HWSEQ_8822C(pDesc, 1);
3949*4882a593Smuzhiyun SET_TX_DESC_HW_SSN_SEL_8822C(pDesc, pxmitpriv->hw_ssn_seq_no);/*pattrib->hw_ssn_sel*/
3950*4882a593Smuzhiyun SET_TX_DESC_EN_HWEXSEQ_8822C(pDesc, 0);
3951*4882a593Smuzhiyun }
3952*4882a593Smuzhiyun
3953*4882a593Smuzhiyun if (_TRUE == IsBTQosNull)
3954*4882a593Smuzhiyun SET_TX_DESC_BT_NULL_8822C(pDesc, 1);
3955*4882a593Smuzhiyun
3956*4882a593Smuzhiyun SET_TX_DESC_USE_RATE_8822C(pDesc, 1);
3957*4882a593Smuzhiyun SET_TX_DESC_DATARATE_8822C(pDesc, MRateToHwRate(pmlmeext->tx_rate));
3958*4882a593Smuzhiyun
3959*4882a593Smuzhiyun #ifdef CONFIG_MCC_MODE
3960*4882a593Smuzhiyun /* config Null data retry number */
3961*4882a593Smuzhiyun if (IsPsPoll == _FALSE && IsBTQosNull == _FALSE && bDataFrame == _FALSE) {
3962*4882a593Smuzhiyun if (rtw_hal_check_mcc_status(adapter, MCC_STATUS_PROCESS_MCC_START_SETTING)) {
3963*4882a593Smuzhiyun u8 rty_num = adapter->mcc_adapterpriv.null_rty_num;
3964*4882a593Smuzhiyun if (rty_num != 0) {
3965*4882a593Smuzhiyun SET_TX_DESC_RTY_LMT_EN_8822C(pDesc, 1);
3966*4882a593Smuzhiyun SET_TX_DESC_RTS_DATA_RTY_LMT_8822C(pDesc, rty_num);
3967*4882a593Smuzhiyun }
3968*4882a593Smuzhiyun }
3969*4882a593Smuzhiyun }
3970*4882a593Smuzhiyun #endif
3971*4882a593Smuzhiyun
3972*4882a593Smuzhiyun
3973*4882a593Smuzhiyun /*
3974*4882a593Smuzhiyun * Encrypt the data frame if under security mode excepct null data.
3975*4882a593Smuzhiyun */
3976*4882a593Smuzhiyun if (_TRUE == bDataFrame) {
3977*4882a593Smuzhiyun u32 EncAlg;
3978*4882a593Smuzhiyun
3979*4882a593Smuzhiyun EncAlg = adapter->securitypriv.dot11PrivacyAlgrthm;
3980*4882a593Smuzhiyun switch (EncAlg) {
3981*4882a593Smuzhiyun case _NO_PRIVACY_:
3982*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x0);
3983*4882a593Smuzhiyun break;
3984*4882a593Smuzhiyun case _WEP40_:
3985*4882a593Smuzhiyun case _WEP104_:
3986*4882a593Smuzhiyun case _TKIP_:
3987*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x1);
3988*4882a593Smuzhiyun break;
3989*4882a593Smuzhiyun case _SMS4_:
3990*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x2);
3991*4882a593Smuzhiyun break;
3992*4882a593Smuzhiyun case _AES_:
3993*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x3);
3994*4882a593Smuzhiyun break;
3995*4882a593Smuzhiyun case _CCMP_256_:
3996*4882a593Smuzhiyun case _GCMP_:
3997*4882a593Smuzhiyun case _GCMP_256_:
3998*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x2);
3999*4882a593Smuzhiyun break;
4000*4882a593Smuzhiyun default:
4001*4882a593Smuzhiyun SET_TX_DESC_SEC_TYPE_8822C(pDesc, 0x0);
4002*4882a593Smuzhiyun break;
4003*4882a593Smuzhiyun }
4004*4882a593Smuzhiyun }
4005*4882a593Smuzhiyun
4006*4882a593Smuzhiyun SET_TX_DESC_PORT_ID_8822C(pDesc, hw_port);
4007*4882a593Smuzhiyun SET_TX_DESC_MULTIPLE_PORT_8822C(pDesc, hw_port);
4008*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
4009*4882a593Smuzhiyun /*
4010*4882a593Smuzhiyun * USB interface drop packet if the checksum of descriptor isn't correct.
4011*4882a593Smuzhiyun * Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.).
4012*4882a593Smuzhiyun */
4013*4882a593Smuzhiyun rtl8822c_cal_txdesc_chksum(adapter, pDesc);
4014*4882a593Smuzhiyun #endif
4015*4882a593Smuzhiyun }
4016*4882a593Smuzhiyun
rtl8822c_dbg_dump_tx_desc(PADAPTER adapter,int frame_tag,u8 * ptxdesc)4017*4882a593Smuzhiyun void rtl8822c_dbg_dump_tx_desc(PADAPTER adapter, int frame_tag, u8 *ptxdesc)
4018*4882a593Smuzhiyun {
4019*4882a593Smuzhiyun u8 bDumpTxPkt;
4020*4882a593Smuzhiyun u8 bDumpTxDesc = _FALSE;
4021*4882a593Smuzhiyun
4022*4882a593Smuzhiyun
4023*4882a593Smuzhiyun rtw_hal_get_def_var(adapter, HAL_DEF_DBG_DUMP_TXPKT, &bDumpTxPkt);
4024*4882a593Smuzhiyun
4025*4882a593Smuzhiyun /* 1 for data frame, 2 for mgnt frame */
4026*4882a593Smuzhiyun if (bDumpTxPkt == 1) {
4027*4882a593Smuzhiyun RTW_INFO("dump tx_desc for data frame\n");
4028*4882a593Smuzhiyun if ((frame_tag & 0x0f) == DATA_FRAMETAG)
4029*4882a593Smuzhiyun bDumpTxDesc = _TRUE;
4030*4882a593Smuzhiyun } else if (bDumpTxPkt == 2) {
4031*4882a593Smuzhiyun RTW_INFO("dump tx_desc for mgnt frame\n");
4032*4882a593Smuzhiyun if ((frame_tag & 0x0f) == MGNT_FRAMETAG)
4033*4882a593Smuzhiyun bDumpTxDesc = _TRUE;
4034*4882a593Smuzhiyun }
4035*4882a593Smuzhiyun
4036*4882a593Smuzhiyun /* 8822C TX SIZE = 48(HALMAC_TX_DESC_SIZE_8822C) */
4037*4882a593Smuzhiyun if (_TRUE == bDumpTxDesc) {
4038*4882a593Smuzhiyun RTW_INFO("=====================================\n");
4039*4882a593Smuzhiyun RTW_INFO("Offset00(0x%08x)\n", *((u32 *)(ptxdesc)));
4040*4882a593Smuzhiyun RTW_INFO("Offset04(0x%08x)\n", *((u32 *)(ptxdesc + 4)));
4041*4882a593Smuzhiyun RTW_INFO("Offset08(0x%08x)\n", *((u32 *)(ptxdesc + 8)));
4042*4882a593Smuzhiyun RTW_INFO("Offset12(0x%08x)\n", *((u32 *)(ptxdesc + 12)));
4043*4882a593Smuzhiyun RTW_INFO("Offset16(0x%08x)\n", *((u32 *)(ptxdesc + 16)));
4044*4882a593Smuzhiyun RTW_INFO("Offset20(0x%08x)\n", *((u32 *)(ptxdesc + 20)));
4045*4882a593Smuzhiyun RTW_INFO("Offset24(0x%08x)\n", *((u32 *)(ptxdesc + 24)));
4046*4882a593Smuzhiyun RTW_INFO("Offset28(0x%08x)\n", *((u32 *)(ptxdesc + 28)));
4047*4882a593Smuzhiyun RTW_INFO("Offset32(0x%08x)\n", *((u32 *)(ptxdesc + 32)));
4048*4882a593Smuzhiyun RTW_INFO("Offset36(0x%08x)\n", *((u32 *)(ptxdesc + 36)));
4049*4882a593Smuzhiyun RTW_INFO("Offset40(0x%08x)\n", *((u32 *)(ptxdesc + 40)));
4050*4882a593Smuzhiyun RTW_INFO("Offset44(0x%08x)\n", *((u32 *)(ptxdesc + 44)));
4051*4882a593Smuzhiyun RTW_INFO("=====================================\n");
4052*4882a593Smuzhiyun }
4053*4882a593Smuzhiyun }
4054*4882a593Smuzhiyun /* xmit section */
rtl8822c_init_xmit_priv(_adapter * adapter)4055*4882a593Smuzhiyun void rtl8822c_init_xmit_priv(_adapter *adapter)
4056*4882a593Smuzhiyun {
4057*4882a593Smuzhiyun struct xmit_priv *pxmitpriv = &adapter->xmitpriv;
4058*4882a593Smuzhiyun
4059*4882a593Smuzhiyun pxmitpriv->hw_ssn_seq_no = rtw_get_hwseq_no(adapter);
4060*4882a593Smuzhiyun pxmitpriv->nqos_ssn = 0;
4061*4882a593Smuzhiyun }
4062*4882a593Smuzhiyun
rtl8822c_rxdesc2attribute(struct rx_pkt_attrib * a,u8 * desc)4063*4882a593Smuzhiyun void rtl8822c_rxdesc2attribute(struct rx_pkt_attrib *a, u8 *desc)
4064*4882a593Smuzhiyun {
4065*4882a593Smuzhiyun /* initial value */
4066*4882a593Smuzhiyun _rtw_memset(a, 0, sizeof(struct rx_pkt_attrib));
4067*4882a593Smuzhiyun a->bw = CHANNEL_WIDTH_MAX;
4068*4882a593Smuzhiyun
4069*4882a593Smuzhiyun /* Get from RX DESC */
4070*4882a593Smuzhiyun a->pkt_len = (u16)GET_RX_DESC_PKT_LEN_8822C(desc);
4071*4882a593Smuzhiyun a->pkt_rpt_type = GET_RX_DESC_C2H_8822C(desc) ? C2H_PACKET : NORMAL_RX;
4072*4882a593Smuzhiyun
4073*4882a593Smuzhiyun if (a->pkt_rpt_type == NORMAL_RX) {
4074*4882a593Smuzhiyun a->crc_err = (u8)GET_RX_DESC_CRC32_8822C(desc);
4075*4882a593Smuzhiyun a->icv_err = (u8)GET_RX_DESC_ICV_ERR_8822C(desc);
4076*4882a593Smuzhiyun a->drvinfo_sz = (u8)GET_RX_DESC_DRV_INFO_SIZE_8822C(desc) << 3;
4077*4882a593Smuzhiyun a->encrypt = (u8)GET_RX_DESC_SECURITY_8822C(desc);
4078*4882a593Smuzhiyun a->qos = (u8)GET_RX_DESC_QOS_8822C(desc);
4079*4882a593Smuzhiyun a->shift_sz = (u8)GET_RX_DESC_SHIFT_8822C(desc);
4080*4882a593Smuzhiyun a->physt = (u8)GET_RX_DESC_PHYST_8822C(desc);
4081*4882a593Smuzhiyun a->bdecrypted = (u8)GET_RX_DESC_SWDEC_8822C(desc) ? 0 : 1;
4082*4882a593Smuzhiyun
4083*4882a593Smuzhiyun a->priority = (u8)GET_RX_DESC_TID_8822C(desc);
4084*4882a593Smuzhiyun a->amsdu = (u8)GET_RX_DESC_AMSDU_8822C(desc);
4085*4882a593Smuzhiyun a->mdata = (u8)GET_RX_DESC_MD_8822C(desc);
4086*4882a593Smuzhiyun a->mfrag = (u8)GET_RX_DESC_MF_8822C(desc);
4087*4882a593Smuzhiyun
4088*4882a593Smuzhiyun a->seq_num = (u16)GET_RX_DESC_SEQ_8822C(desc);
4089*4882a593Smuzhiyun a->frag_num = (u8)GET_RX_DESC_FRAG_8822C(desc);
4090*4882a593Smuzhiyun
4091*4882a593Smuzhiyun a->data_rate = (u8)GET_RX_DESC_RX_RATE_8822C(desc);
4092*4882a593Smuzhiyun a->ampdu = (u8)GET_RX_DESC_PAGGR_8822C(desc);
4093*4882a593Smuzhiyun a->ampdu_eof = (u8)GET_RX_DESC_RX_EOF_8822C(desc);
4094*4882a593Smuzhiyun a->ppdu_cnt = (u8)GET_RX_DESC_PPDU_CNT_8822C(desc);
4095*4882a593Smuzhiyun a->free_cnt = (u32)GET_RX_DESC_TSFL_8822C(desc);
4096*4882a593Smuzhiyun
4097*4882a593Smuzhiyun #ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
4098*4882a593Smuzhiyun /* RX TCP checksum offload related variables */
4099*4882a593Smuzhiyun a->csum_valid = (u8)GET_RX_DESC_CHK_VLD_8822C(desc);
4100*4882a593Smuzhiyun a->csum_err = (u8)GET_RX_DESC_CHKERR_8822C(desc);
4101*4882a593Smuzhiyun #endif /* CONFIG_TCP_CSUM_OFFLOAD_RX */
4102*4882a593Smuzhiyun }
4103*4882a593Smuzhiyun }
4104*4882a593Smuzhiyun
rtl8822c_query_rx_desc(union recv_frame * precvframe,u8 * pdesc)4105*4882a593Smuzhiyun void rtl8822c_query_rx_desc(union recv_frame *precvframe, u8 *pdesc)
4106*4882a593Smuzhiyun {
4107*4882a593Smuzhiyun rtl8822c_rxdesc2attribute(&precvframe->u.hdr.attrib, pdesc);
4108*4882a593Smuzhiyun }
4109*4882a593Smuzhiyun
rtl8822c_set_hal_ops(PADAPTER adapter)4110*4882a593Smuzhiyun void rtl8822c_set_hal_ops(PADAPTER adapter)
4111*4882a593Smuzhiyun {
4112*4882a593Smuzhiyun struct hal_com_data *hal;
4113*4882a593Smuzhiyun struct hal_ops *ops;
4114*4882a593Smuzhiyun
4115*4882a593Smuzhiyun
4116*4882a593Smuzhiyun hal = GET_HAL_DATA(adapter);
4117*4882a593Smuzhiyun ops = &adapter->hal_func;
4118*4882a593Smuzhiyun
4119*4882a593Smuzhiyun /*
4120*4882a593Smuzhiyun * Initialize hal_com_data variables
4121*4882a593Smuzhiyun */
4122*4882a593Smuzhiyun hal->efuse0x3d7 = 0xFF;
4123*4882a593Smuzhiyun hal->efuse0x3d8 = 0xFF;
4124*4882a593Smuzhiyun
4125*4882a593Smuzhiyun /*
4126*4882a593Smuzhiyun * Initialize operation callback functions
4127*4882a593Smuzhiyun */
4128*4882a593Smuzhiyun /*** initialize section ***/
4129*4882a593Smuzhiyun ops->read_chip_version = read_chip_version;
4130*4882a593Smuzhiyun /*
4131*4882a593Smuzhiyun ops->init_default_value = NULL;
4132*4882a593Smuzhiyun ops->intf_chip_configure = NULL;
4133*4882a593Smuzhiyun */
4134*4882a593Smuzhiyun ops->read_adapter_info = rtl8822c_read_efuse;
4135*4882a593Smuzhiyun ops->hal_power_on = rtl8822c_power_on;
4136*4882a593Smuzhiyun ops->hal_power_off = rtl8822c_power_off;
4137*4882a593Smuzhiyun ops->hal_init = rtl8822c_init;
4138*4882a593Smuzhiyun ops->hal_deinit = rtl8822c_deinit;
4139*4882a593Smuzhiyun ops->dm_init = rtl8822c_phy_init_dm_priv;
4140*4882a593Smuzhiyun ops->dm_deinit = rtl8822c_phy_deinit_dm_priv;
4141*4882a593Smuzhiyun
4142*4882a593Smuzhiyun /*** xmit section ***/
4143*4882a593Smuzhiyun /*
4144*4882a593Smuzhiyun ops->init_xmit_priv = NULL;
4145*4882a593Smuzhiyun ops->free_xmit_priv = NULL;
4146*4882a593Smuzhiyun ops->hal_xmit = NULL;
4147*4882a593Smuzhiyun ops->mgnt_xmit = NULL;
4148*4882a593Smuzhiyun ops->hal_xmitframe_enqueue = NULL;
4149*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE
4150*4882a593Smuzhiyun ops->xmit_thread_handler = NULL;
4151*4882a593Smuzhiyun #endif
4152*4882a593Smuzhiyun */
4153*4882a593Smuzhiyun ops->run_thread = rtl8822c_run_thread;
4154*4882a593Smuzhiyun ops->cancel_thread = rtl8822c_cancel_thread;
4155*4882a593Smuzhiyun
4156*4882a593Smuzhiyun /*** recv section ***/
4157*4882a593Smuzhiyun /*
4158*4882a593Smuzhiyun ops->init_recv_priv = NULL;
4159*4882a593Smuzhiyun ops->free_recv_priv = NULL;
4160*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) || defined(CONFIG_PCI_HCI)
4161*4882a593Smuzhiyun ops->inirp_init = NULL;
4162*4882a593Smuzhiyun ops->inirp_deinit = NULL;
4163*4882a593Smuzhiyun #endif
4164*4882a593Smuzhiyun */
4165*4882a593Smuzhiyun /*** interrupt hdl section ***/
4166*4882a593Smuzhiyun /*
4167*4882a593Smuzhiyun ops->enable_interrupt = NULL;
4168*4882a593Smuzhiyun ops->disable_interrupt = NULL;
4169*4882a593Smuzhiyun */
4170*4882a593Smuzhiyun ops->check_ips_status = check_ips_status;
4171*4882a593Smuzhiyun /*
4172*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
4173*4882a593Smuzhiyun ops->interrupt_handler = NULL;
4174*4882a593Smuzhiyun #endif
4175*4882a593Smuzhiyun #if defined(CONFIG_USB_HCI) && defined(CONFIG_SUPPORT_USB_INT)
4176*4882a593Smuzhiyun ops->interrupt_handler = NULL;
4177*4882a593Smuzhiyun #endif
4178*4882a593Smuzhiyun #if defined(CONFIG_PCI_HCI)
4179*4882a593Smuzhiyun ops->irp_reset = NULL;
4180*4882a593Smuzhiyun #endif
4181*4882a593Smuzhiyun */
4182*4882a593Smuzhiyun
4183*4882a593Smuzhiyun /*** DM section ***/
4184*4882a593Smuzhiyun ops->set_chnl_bw_handler = rtl8822c_set_channel_bw;
4185*4882a593Smuzhiyun
4186*4882a593Smuzhiyun ops->set_tx_power_level_handler = rtl8822c_set_tx_power_level;
4187*4882a593Smuzhiyun ops->set_txpwr_done = rtl8822c_set_txpwr_done;
4188*4882a593Smuzhiyun ops->set_tx_power_index_handler = rtl8822c_set_tx_power_index;
4189*4882a593Smuzhiyun ops->get_tx_power_index_handler = hal_com_get_txpwr_idx;
4190*4882a593Smuzhiyun
4191*4882a593Smuzhiyun ops->hal_dm_watchdog = rtl8822c_phy_haldm_watchdog;
4192*4882a593Smuzhiyun
4193*4882a593Smuzhiyun ops->set_hw_reg_handler = rtl8822c_sethwreg;
4194*4882a593Smuzhiyun ops->GetHwRegHandler = rtl8822c_gethwreg;
4195*4882a593Smuzhiyun ops->get_hal_def_var_handler = rtl8822c_gethaldefvar;
4196*4882a593Smuzhiyun ops->SetHalDefVarHandler = rtl8822c_sethaldefvar;
4197*4882a593Smuzhiyun
4198*4882a593Smuzhiyun ops->GetHalODMVarHandler = GetHalODMVar;
4199*4882a593Smuzhiyun ops->SetHalODMVarHandler = SetHalODMVar;
4200*4882a593Smuzhiyun
4201*4882a593Smuzhiyun ops->SetBeaconRelatedRegistersHandler = set_beacon_related_registers;
4202*4882a593Smuzhiyun
4203*4882a593Smuzhiyun /*
4204*4882a593Smuzhiyun ops->interface_ps_func = NULL;
4205*4882a593Smuzhiyun */
4206*4882a593Smuzhiyun ops->read_bbreg = rtl8822c_read_bb_reg;
4207*4882a593Smuzhiyun ops->write_bbreg = rtl8822c_write_bb_reg;
4208*4882a593Smuzhiyun ops->read_rfreg = rtl8822c_read_rf_reg;
4209*4882a593Smuzhiyun ops->write_rfreg = rtl8822c_write_rf_reg;
4210*4882a593Smuzhiyun ops->read_wmmedca_reg = rtl8822c_read_wmmedca_reg;
4211*4882a593Smuzhiyun
4212*4882a593Smuzhiyun #ifdef CONFIG_HOSTAPD_MLME
4213*4882a593Smuzhiyun /*
4214*4882a593Smuzhiyun ops->hostap_mgnt_xmit_entry = NULL;
4215*4882a593Smuzhiyun */
4216*4882a593Smuzhiyun #endif
4217*4882a593Smuzhiyun /*
4218*4882a593Smuzhiyun ops->EfusePowerSwitch = NULL;
4219*4882a593Smuzhiyun ops->BTEfusePowerSwitch = NULL;
4220*4882a593Smuzhiyun ops->ReadEFuse = NULL;
4221*4882a593Smuzhiyun ops->EFUSEGetEfuseDefinition = NULL;
4222*4882a593Smuzhiyun ops->EfuseGetCurrentSize = NULL;
4223*4882a593Smuzhiyun ops->Efuse_PgPacketRead = NULL;
4224*4882a593Smuzhiyun ops->Efuse_PgPacketWrite = NULL;
4225*4882a593Smuzhiyun ops->Efuse_WordEnableDataWrite = NULL;
4226*4882a593Smuzhiyun ops->Efuse_PgPacketWrite_BT = NULL;
4227*4882a593Smuzhiyun */
4228*4882a593Smuzhiyun #ifdef DBG_CONFIG_ERROR_DETECT
4229*4882a593Smuzhiyun ops->sreset_init_value = sreset_init_value;
4230*4882a593Smuzhiyun ops->sreset_reset_value = sreset_reset_value;
4231*4882a593Smuzhiyun ops->silentreset = sreset_reset;
4232*4882a593Smuzhiyun ops->sreset_xmit_status_check = xmit_status_check;
4233*4882a593Smuzhiyun ops->sreset_linked_status_check = linked_status_check;
4234*4882a593Smuzhiyun ops->sreset_get_wifi_status = sreset_get_wifi_status;
4235*4882a593Smuzhiyun ops->sreset_inprogress = sreset_inprogress;
4236*4882a593Smuzhiyun #endif /* DBG_CONFIG_ERROR_DETECT */
4237*4882a593Smuzhiyun
4238*4882a593Smuzhiyun #ifdef CONFIG_IOL
4239*4882a593Smuzhiyun /*
4240*4882a593Smuzhiyun ops->IOL_exec_cmds_sync = NULL;
4241*4882a593Smuzhiyun */
4242*4882a593Smuzhiyun #endif
4243*4882a593Smuzhiyun
4244*4882a593Smuzhiyun ops->hal_notch_filter = rtl8822c_notch_filter_switch;
4245*4882a593Smuzhiyun ops->hal_mac_c2h_handler = rtl8822c_c2h_handler;
4246*4882a593Smuzhiyun ops->fill_h2c_cmd = rtl8822c_fillh2ccmd;
4247*4882a593Smuzhiyun ops->fill_fake_txdesc = fill_fake_txdesc;
4248*4882a593Smuzhiyun ops->fw_dl = rtl8822c_fw_dl;
4249*4882a593Smuzhiyun
4250*4882a593Smuzhiyun #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) || defined(CONFIG_PCI_HCI)
4251*4882a593Smuzhiyun /*
4252*4882a593Smuzhiyun ops->clear_interrupt = NULL;
4253*4882a593Smuzhiyun */
4254*4882a593Smuzhiyun #endif
4255*4882a593Smuzhiyun /*
4256*4882a593Smuzhiyun ops->hal_get_tx_buff_rsvd_page_num = NULL;
4257*4882a593Smuzhiyun */
4258*4882a593Smuzhiyun #ifdef CONFIG_GPIO_API
4259*4882a593Smuzhiyun /*
4260*4882a593Smuzhiyun ops->update_hisr_hsisr_ind = NULL;
4261*4882a593Smuzhiyun */
4262*4882a593Smuzhiyun #endif
4263*4882a593Smuzhiyun
4264*4882a593Smuzhiyun /* HALMAC related functions */
4265*4882a593Smuzhiyun ops->init_mac_register = rtl8822c_phy_init_mac_register;
4266*4882a593Smuzhiyun ops->init_phy = rtl8822c_phy_init;
4267*4882a593Smuzhiyun ops->reqtxrpt = rtl8822c_req_txrpt_cmd;
4268*4882a593Smuzhiyun
4269*4882a593Smuzhiyun }
4270*4882a593Smuzhiyun
4271