1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * Copyright(c) 2015 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun * published by the Free Software Foundation.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun * more details.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun *****************************************************************************/
15*4882a593Smuzhiyun #define _RTL8822C_MAC_C_
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <drv_types.h> /* PADAPTER, basic_types.h and etc. */
18*4882a593Smuzhiyun #include <hal_data.h> /* HAL_DATA_TYPE */
19*4882a593Smuzhiyun #include "../hal_halmac.h" /* Register Definition and etc. */
20*4882a593Smuzhiyun #include "rtl8822c.h" /* FW array */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun
rtl8822c_rcr_config(PADAPTER p,u32 rcr)23*4882a593Smuzhiyun inline u8 rtl8822c_rcr_config(PADAPTER p, u32 rcr)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun u32 v32;
26*4882a593Smuzhiyun int err;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun v32 = GET_HAL_DATA(p)->ReceiveConfig;
30*4882a593Smuzhiyun v32 ^= rcr;
31*4882a593Smuzhiyun v32 &= BIT_APP_PHYSTS_8822C;
32*4882a593Smuzhiyun if (v32) {
33*4882a593Smuzhiyun v32 = rcr & BIT_APP_PHYSTS_8822C;
34*4882a593Smuzhiyun RTW_INFO("%s: runtime %s rx phy status!\n",
35*4882a593Smuzhiyun __FUNCTION__, v32 ? "ENABLE" : "DISABLE");
36*4882a593Smuzhiyun if (v32) {
37*4882a593Smuzhiyun err = rtw_halmac_config_rx_info(adapter_to_dvobj(p), HALMAC_DRV_INFO_PHY_STATUS);
38*4882a593Smuzhiyun if (err) {
39*4882a593Smuzhiyun RTW_INFO("%s: Enable rx phy status FAIL!!", __FUNCTION__);
40*4882a593Smuzhiyun rcr &= ~BIT_APP_PHYSTS_8822C;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun } else {
43*4882a593Smuzhiyun err = rtw_halmac_config_rx_info(adapter_to_dvobj(p), HALMAC_DRV_INFO_NONE);
44*4882a593Smuzhiyun if (err) {
45*4882a593Smuzhiyun RTW_INFO("%s: Disable rx phy status FAIL!!", __FUNCTION__);
46*4882a593Smuzhiyun rcr |= BIT_APP_PHYSTS_8822C;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun err = rtw_write32(p, REG_RCR_8822C, rcr);
52*4882a593Smuzhiyun if (_FAIL == err)
53*4882a593Smuzhiyun return _FALSE;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun GET_HAL_DATA(p)->ReceiveConfig = rcr;
56*4882a593Smuzhiyun return _TRUE;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
rtl8822c_rx_ba_ssn_appended(PADAPTER p)59*4882a593Smuzhiyun inline u8 rtl8822c_rx_ba_ssn_appended(PADAPTER p)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun return rtw_hal_rcr_check(p, BIT_APP_BASSN_8822C);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
rtl8822c_rx_fcs_append_switch(PADAPTER p,u8 enable)64*4882a593Smuzhiyun inline u8 rtl8822c_rx_fcs_append_switch(PADAPTER p, u8 enable)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun u32 rcr_bit;
67*4882a593Smuzhiyun u8 ret = _TRUE;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun rcr_bit = BIT_APP_FCS_8822C;
70*4882a593Smuzhiyun if (_TRUE == enable)
71*4882a593Smuzhiyun ret = rtw_hal_rcr_add(p, rcr_bit);
72*4882a593Smuzhiyun else
73*4882a593Smuzhiyun ret = rtw_hal_rcr_clear(p, rcr_bit);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun return ret;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
rtl8822c_rx_fcs_appended(PADAPTER p)78*4882a593Smuzhiyun inline u8 rtl8822c_rx_fcs_appended(PADAPTER p)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun return rtw_hal_rcr_check(p, BIT_APP_FCS_8822C);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
rtl8822c_rx_tsf_addr_filter_config(PADAPTER p,u8 config)83*4882a593Smuzhiyun inline u8 rtl8822c_rx_tsf_addr_filter_config(PADAPTER p, u8 config)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun u8 v8;
86*4882a593Smuzhiyun int err;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun v8 = GET_HAL_DATA(p)->rx_tsf_addr_filter_config;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (v8 != config) {
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun err = rtw_write8(p, REG_NAN_RX_TSF_FILTER_8822C, config);
93*4882a593Smuzhiyun if (_FAIL == err)
94*4882a593Smuzhiyun return _FALSE;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun GET_HAL_DATA(p)->rx_tsf_addr_filter_config = config;
98*4882a593Smuzhiyun return _TRUE;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun /*
102*4882a593Smuzhiyun * Return:
103*4882a593Smuzhiyun * _SUCCESS Download Firmware OK.
104*4882a593Smuzhiyun * _FAIL Download Firmware FAIL!
105*4882a593Smuzhiyun */
rtl8822c_fw_dl(PADAPTER adapter,u8 wowlan)106*4882a593Smuzhiyun s32 rtl8822c_fw_dl(PADAPTER adapter, u8 wowlan)
107*4882a593Smuzhiyun {
108*4882a593Smuzhiyun struct dvobj_priv *d = adapter_to_dvobj(adapter);
109*4882a593Smuzhiyun HAL_DATA_TYPE *hal = GET_HAL_DATA(adapter);
110*4882a593Smuzhiyun struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(adapter);
111*4882a593Smuzhiyun int err;
112*4882a593Smuzhiyun u8 fw_bin = _TRUE;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #ifdef CONFIG_FILE_FWIMG
115*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
116*4882a593Smuzhiyun if (wowlan)
117*4882a593Smuzhiyun rtw_get_phy_file_path(adapter, MAC_FILE_FW_WW_IMG);
118*4882a593Smuzhiyun else
119*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
120*4882a593Smuzhiyun rtw_get_phy_file_path(adapter, MAC_FILE_FW_NIC);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun if (rtw_is_file_readable(rtw_phy_para_file_path) == _TRUE) {
123*4882a593Smuzhiyun RTW_INFO("%s acquire FW from file:%s\n", __FUNCTION__, rtw_phy_para_file_path);
124*4882a593Smuzhiyun fw_bin = _TRUE;
125*4882a593Smuzhiyun } else
126*4882a593Smuzhiyun #endif /* CONFIG_FILE_FWIMG */
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun RTW_INFO("%s fw source from array\n", __FUNCTION__);
129*4882a593Smuzhiyun fw_bin = _FALSE;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #ifdef CONFIG_FILE_FWIMG
133*4882a593Smuzhiyun if (_TRUE == fw_bin) {
134*4882a593Smuzhiyun err = rtw_halmac_dlfw_from_file(d, rtw_phy_para_file_path);
135*4882a593Smuzhiyun } else
136*4882a593Smuzhiyun #endif /* CONFIG_FILE_FWIMG */
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun #ifdef CONFIG_WOWLAN
139*4882a593Smuzhiyun if (_TRUE == wowlan)
140*4882a593Smuzhiyun err = rtw_halmac_dlfw(d, array_mp_8822c_fw_wowlan, array_length_mp_8822c_fw_wowlan);
141*4882a593Smuzhiyun else
142*4882a593Smuzhiyun #endif /* CONFIG_WOWLAN */
143*4882a593Smuzhiyun err = rtw_halmac_dlfw(d, array_mp_8822c_fw_nic, array_length_mp_8822c_fw_nic);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (!err) {
147*4882a593Smuzhiyun hal->bFWReady = _TRUE;
148*4882a593Smuzhiyun hal->fw_ractrl = _TRUE;
149*4882a593Smuzhiyun RTW_INFO("%s Download Firmware from %s success\n", __FUNCTION__, (fw_bin) ? "file" : "array");
150*4882a593Smuzhiyun RTW_INFO("%s FW Version:%d SubVersion:%d FW size:%d\n", (wowlan) ? "WOW" : "NIC",
151*4882a593Smuzhiyun hal->firmware_version, hal->firmware_sub_version, hal->firmware_size);
152*4882a593Smuzhiyun return _SUCCESS;
153*4882a593Smuzhiyun } else {
154*4882a593Smuzhiyun hal->bFWReady = _FALSE;
155*4882a593Smuzhiyun hal->fw_ractrl = _FALSE;
156*4882a593Smuzhiyun RTW_ERR("%s Download Firmware from %s failed\n", __FUNCTION__, (fw_bin) ? "file" : "array");
157*4882a593Smuzhiyun return _FAIL;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
rtl8822c_get_rx_drv_info_size(struct _ADAPTER * a)161*4882a593Smuzhiyun u8 rtl8822c_get_rx_drv_info_size(struct _ADAPTER *a)
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun struct dvobj_priv *d;
164*4882a593Smuzhiyun u8 size = 80; /* HALMAC_RX_DESC_DUMMY_SIZE_MAX_88XX */
165*4882a593Smuzhiyun int err = 0;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun d = adapter_to_dvobj(a);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun err = rtw_halmac_get_rx_drv_info_sz(d, &size);
171*4882a593Smuzhiyun if (err) {
172*4882a593Smuzhiyun RTW_WARN(FUNC_ADPT_FMT ": Fail to get DRV INFO size!!(err=%d)\n",
173*4882a593Smuzhiyun FUNC_ADPT_ARG(a), err);
174*4882a593Smuzhiyun size = 80;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun return size;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
rtl8822c_get_tx_desc_size(struct _ADAPTER * a)180*4882a593Smuzhiyun u32 rtl8822c_get_tx_desc_size(struct _ADAPTER *a)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun struct dvobj_priv *d;
183*4882a593Smuzhiyun u32 size = 48; /* HALMAC_TX_DESC_SIZE_8822C */
184*4882a593Smuzhiyun int err = 0;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun d = adapter_to_dvobj(a);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun err = rtw_halmac_get_tx_desc_size(d, &size);
190*4882a593Smuzhiyun if (err) {
191*4882a593Smuzhiyun RTW_WARN(FUNC_ADPT_FMT ": Fail to get TX Descriptor size!!(err=%d)\n",
192*4882a593Smuzhiyun FUNC_ADPT_ARG(a), err);
193*4882a593Smuzhiyun size = 48;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun return size;
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
rtl8822c_get_rx_desc_size(struct _ADAPTER * a)199*4882a593Smuzhiyun u32 rtl8822c_get_rx_desc_size(struct _ADAPTER *a)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun struct dvobj_priv *d;
202*4882a593Smuzhiyun u32 size = 24; /* HALMAC_RX_DESC_SIZE_8822C */
203*4882a593Smuzhiyun int err = 0;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun d = adapter_to_dvobj(a);
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun err = rtw_halmac_get_rx_desc_size(d, &size);
209*4882a593Smuzhiyun if (err) {
210*4882a593Smuzhiyun RTW_WARN(FUNC_ADPT_FMT ": Fail to get RX Descriptor size!!(err=%d)\n",
211*4882a593Smuzhiyun FUNC_ADPT_ARG(a), err);
212*4882a593Smuzhiyun size = 24;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun return size;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218