1*4882a593Smuzhiyun /****************************************************************************** 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright(c) 2007 - 2017 Realtek Corporation. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 6*4882a593Smuzhiyun * under the terms of version 2 of the GNU General Public License as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but WITHOUT 10*4882a593Smuzhiyun * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12*4882a593Smuzhiyun * more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The full GNU General Public License is included in this distribution in the 15*4882a593Smuzhiyun * file called LICENSE. 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * Contact Information: 18*4882a593Smuzhiyun * wlanfae <wlanfae@realtek.com> 19*4882a593Smuzhiyun * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20*4882a593Smuzhiyun * Hsinchu 300, Taiwan. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Larry Finger <Larry.Finger@lwfinger.net> 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun *****************************************************************************/ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #ifndef __PHYDMCCX_H__ 27*4882a593Smuzhiyun #define __PHYDMCCX_H__ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 2021.03.10 Add 8814C flag*/ 30*4882a593Smuzhiyun #define CCX_VERSION "4.9" 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* @1 ============================================================ 33*4882a593Smuzhiyun * 1 Definition 34*4882a593Smuzhiyun * 1 ============================================================ 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define CCX_EN 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define MAX_ENV_MNTR_TIME 8 /*second*/ 39*4882a593Smuzhiyun #define MS_TO_US 1000 40*4882a593Smuzhiyun #define MS_TO_4US_RATIO 250 41*4882a593Smuzhiyun #define CCA_CAP 14 42*4882a593Smuzhiyun /*CLM*/ 43*4882a593Smuzhiyun #define CLM_MAX_REPORT_TIME 10 44*4882a593Smuzhiyun #define CLM_PERIOD_MAX 65535 45*4882a593Smuzhiyun /*NHM*/ 46*4882a593Smuzhiyun #define NHM_PERIOD_MAX 65534 47*4882a593Smuzhiyun #define NHM_TH_NUM 11 /*threshold number of NHM*/ 48*4882a593Smuzhiyun #define NHM_RPT_NUM 12 49*4882a593Smuzhiyun #define NHM_IC_NOISE_TH 60 /*60/2 - 10 = 20 = -80 dBm*/ 50*4882a593Smuzhiyun #define NHM_RPT_MAX 255 51*4882a593Smuzhiyun #ifdef NHM_DYM_PW_TH_SUPPORT 52*4882a593Smuzhiyun #define DYM_PWTH_CCA_CAP 24 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun #define IGI_2_NHM_TH(igi) ((igi) << 1)/*NHM/FAHM threshold = IGI * 2*/ 55*4882a593Smuzhiyun #define NTH_TH_2_RSSI(th) ((th >> 1) - 10) 56*4882a593Smuzhiyun /*FAHM*/ 57*4882a593Smuzhiyun #define FAHM_INCLU_FA BIT(0) 58*4882a593Smuzhiyun #define FAHM_INCLU_CRC_OK BIT(1) 59*4882a593Smuzhiyun #define FAHM_INCLU_CRC_ERR BIT(2) 60*4882a593Smuzhiyun #define FAHM_PERIOD_MAX 65534 61*4882a593Smuzhiyun #define FAHM_TH_NUM 11 /*threshold number of FAHM*/ 62*4882a593Smuzhiyun #define FAHM_RPT_NUM 12 63*4882a593Smuzhiyun /*IFS-CLM*/ 64*4882a593Smuzhiyun #define IFS_CLM_PERIOD_MAX 65535 65*4882a593Smuzhiyun #define IFS_CLM_NUM 4 66*4882a593Smuzhiyun /*EDCCA-CLM*/ 67*4882a593Smuzhiyun #define EDCCA_CLM_PERIOD 65535 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define NHM_SUCCESS BIT(0) 70*4882a593Smuzhiyun #define CLM_SUCCESS BIT(1) 71*4882a593Smuzhiyun #define FAHM_SUCCESS BIT(2) 72*4882a593Smuzhiyun #define IFS_CLM_SUCCESS BIT(3) 73*4882a593Smuzhiyun #define EDCCA_CLM_SUCCESS BIT(4) 74*4882a593Smuzhiyun #define ENV_MNTR_FAIL 0xff 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* @1 ============================================================ 77*4882a593Smuzhiyun * 1 enumrate 78*4882a593Smuzhiyun * 1 ============================================================ 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun enum phydm_clm_level { 81*4882a593Smuzhiyun CLM_RELEASE = 0, 82*4882a593Smuzhiyun CLM_LV_1 = 1, /* @Low Priority function */ 83*4882a593Smuzhiyun CLM_LV_2 = 2, /* @Middle Priority function */ 84*4882a593Smuzhiyun CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ 85*4882a593Smuzhiyun CLM_LV_4 = 4, /* @Debug function (the highest priority) */ 86*4882a593Smuzhiyun CLM_MAX_NUM = 5 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun enum phydm_nhm_level { 90*4882a593Smuzhiyun NHM_RELEASE = 0, 91*4882a593Smuzhiyun NHM_LV_1 = 1, /* @Low Priority function */ 92*4882a593Smuzhiyun NHM_LV_2 = 2, /* @Middle Priority function */ 93*4882a593Smuzhiyun NHM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ 94*4882a593Smuzhiyun NHM_LV_4 = 4, /* @Debug function (the highest priority) */ 95*4882a593Smuzhiyun NHM_MAX_NUM = 5 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun enum phydm_fahm_level { 99*4882a593Smuzhiyun FAHM_RELEASE = 0, 100*4882a593Smuzhiyun FAHM_LV_1 = 1, /* Low Priority function */ 101*4882a593Smuzhiyun FAHM_LV_2 = 2, /* Middle Priority function */ 102*4882a593Smuzhiyun FAHM_LV_3 = 3, /* High priority function (ex: Check hang function) */ 103*4882a593Smuzhiyun FAHM_LV_4 = 4, /* Debug function (the highest priority) */ 104*4882a593Smuzhiyun FAHM_MAX_NUM = 5 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun enum phydm_ifs_clm_level { 108*4882a593Smuzhiyun IFS_CLM_RELEASE = 0, 109*4882a593Smuzhiyun IFS_CLM_LV_1 = 1, /* @Low Priority function */ 110*4882a593Smuzhiyun IFS_CLM_LV_2 = 2, /* @Middle Priority function */ 111*4882a593Smuzhiyun IFS_CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ 112*4882a593Smuzhiyun IFS_CLM_LV_4 = 4, /* @Debug function (the highest priority) */ 113*4882a593Smuzhiyun IFS_CLM_MAX_NUM = 5 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun enum phydm_edcca_clm_level { 117*4882a593Smuzhiyun EDCCA_CLM_RELEASE = 0, 118*4882a593Smuzhiyun EDCCA_CLM_LV_1 = 1, /* @Low Priority function */ 119*4882a593Smuzhiyun EDCCA_CLM_LV_2 = 2, /* @Middle Priority function */ 120*4882a593Smuzhiyun EDCCA_CLM_LV_3 = 3, /* @High priority function (ex: Check hang function) */ 121*4882a593Smuzhiyun EDCCA_CLM_LV_4 = 4, /* @Debug function (the highest priority) */ 122*4882a593Smuzhiyun EDCCA_CLM_MAX_NUM = 5 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun enum nhm_divider_opt_all { 126*4882a593Smuzhiyun NHM_CNT_ALL = 0, /*nhm SUM report <= 255*/ 127*4882a593Smuzhiyun NHM_VALID = 1, /*nhm SUM report = 255*/ 128*4882a593Smuzhiyun NHM_CNT_INIT 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun enum nhm_setting { 132*4882a593Smuzhiyun SET_NHM_SETTING, 133*4882a593Smuzhiyun STORE_NHM_SETTING, 134*4882a593Smuzhiyun RESTORE_NHM_SETTING 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun enum nhm_option_cca_all { 138*4882a593Smuzhiyun NHM_EXCLUDE_CCA = 0, 139*4882a593Smuzhiyun NHM_INCLUDE_CCA = 1, 140*4882a593Smuzhiyun NHM_CCA_INIT 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun enum nhm_option_txon_all { 144*4882a593Smuzhiyun NHM_EXCLUDE_TXON = 0, 145*4882a593Smuzhiyun NHM_INCLUDE_TXON = 1, 146*4882a593Smuzhiyun NHM_TXON_INIT 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun enum nhm_application { 150*4882a593Smuzhiyun NHM_BACKGROUND = 0,/*@default*/ 151*4882a593Smuzhiyun NHM_ACS = 1, 152*4882a593Smuzhiyun IEEE_11K_HIGH = 2, 153*4882a593Smuzhiyun IEEE_11K_LOW = 3, 154*4882a593Smuzhiyun INTEL_XBOX = 4, 155*4882a593Smuzhiyun NHM_DBG = 5, /*@manual trigger*/ 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun enum clm_application { 159*4882a593Smuzhiyun CLM_BACKGROUND = 0,/*@default*/ 160*4882a593Smuzhiyun CLM_ACS = 1, 161*4882a593Smuzhiyun }; 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun enum fahm_application { 164*4882a593Smuzhiyun FAHM_BACKGROUND = 0,/*default*/ 165*4882a593Smuzhiyun FAHM_ACS = 1, 166*4882a593Smuzhiyun FAHM_DBG = 2, /*manual trigger*/ 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun enum ifs_clm_application { 170*4882a593Smuzhiyun IFS_CLM_BACKGROUND = 0,/*default*/ 171*4882a593Smuzhiyun IFS_CLM_ACS = 1, 172*4882a593Smuzhiyun IFS_CLM_HP_TAS = 2, 173*4882a593Smuzhiyun IFS_CLM_DBG = 3, 174*4882a593Smuzhiyun }; 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun enum clm_monitor_mode { 177*4882a593Smuzhiyun CLM_DRIVER_MNTR = 1, 178*4882a593Smuzhiyun CLM_FW_MNTR = 2 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun enum phydm_ifs_clm_unit { 182*4882a593Smuzhiyun IFS_CLM_4 = 0, /*4us*/ 183*4882a593Smuzhiyun IFS_CLM_8 = 1, /*8us*/ 184*4882a593Smuzhiyun IFS_CLM_12 = 2, /*12us*/ 185*4882a593Smuzhiyun IFS_CLM_16 = 3, /*16us*/ 186*4882a593Smuzhiyun IFS_CLM_INIT 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun enum edcca_clm_application { 190*4882a593Smuzhiyun EDCCA_CLM_BACKGROUND = 0,/*@default*/ 191*4882a593Smuzhiyun EDCCA_CLM_ACS = 1, 192*4882a593Smuzhiyun EDCCA_CLM_DBG = 2, 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* @1 ============================================================ 196*4882a593Smuzhiyun * 1 structure 197*4882a593Smuzhiyun * 1 ============================================================ 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun struct env_trig_rpt { 200*4882a593Smuzhiyun u8 nhm_rpt_stamp; 201*4882a593Smuzhiyun u8 clm_rpt_stamp; 202*4882a593Smuzhiyun }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun struct env_mntr_rpt { 205*4882a593Smuzhiyun u8 nhm_ratio; 206*4882a593Smuzhiyun u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ 207*4882a593Smuzhiyun u8 nhm_result[NHM_RPT_NUM]; 208*4882a593Smuzhiyun u8 clm_ratio; 209*4882a593Smuzhiyun u8 nhm_rpt_stamp; 210*4882a593Smuzhiyun u8 clm_rpt_stamp; 211*4882a593Smuzhiyun u8 nhm_noise_pwr; /*including r[0]~r[10]*/ 212*4882a593Smuzhiyun u8 nhm_pwr; /*including r[0]~r[11]*/ 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun struct enhance_mntr_trig_rpt { 216*4882a593Smuzhiyun u8 nhm_rpt_stamp; 217*4882a593Smuzhiyun u8 clm_rpt_stamp; 218*4882a593Smuzhiyun u8 fahm_rpt_stamp; 219*4882a593Smuzhiyun u8 ifs_clm_rpt_stamp; 220*4882a593Smuzhiyun }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun struct enhance_mntr_rpt { 223*4882a593Smuzhiyun u8 nhm_ratio; 224*4882a593Smuzhiyun u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ 225*4882a593Smuzhiyun u8 nhm_result[NHM_RPT_NUM]; 226*4882a593Smuzhiyun u8 clm_ratio; 227*4882a593Smuzhiyun u8 nhm_rpt_stamp; 228*4882a593Smuzhiyun u8 clm_rpt_stamp; 229*4882a593Smuzhiyun u8 nhm_noise_pwr; /*including r[0]~r[10]*/ 230*4882a593Smuzhiyun u8 nhm_pwr; /*including r[0]~r[11]*/ 231*4882a593Smuzhiyun u16 fahm_result[NHM_RPT_NUM]; 232*4882a593Smuzhiyun u8 fahm_rpt_stamp; 233*4882a593Smuzhiyun u8 fahm_pwr; 234*4882a593Smuzhiyun u8 fahm_ratio; 235*4882a593Smuzhiyun u8 fahm_denom_ratio; 236*4882a593Smuzhiyun u8 fahm_inclu_cck; 237*4882a593Smuzhiyun u8 ifs_clm_rpt_stamp; 238*4882a593Smuzhiyun u8 ifs_clm_tx_ratio; 239*4882a593Smuzhiyun u8 ifs_clm_edcca_excl_cca_ratio; 240*4882a593Smuzhiyun u8 ifs_clm_cck_fa_ratio; 241*4882a593Smuzhiyun u8 ifs_clm_cck_cca_excl_fa_ratio; 242*4882a593Smuzhiyun u8 ifs_clm_ofdm_fa_ratio; 243*4882a593Smuzhiyun u8 ifs_clm_ofdm_cca_excl_fa_ratio; 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun struct nhm_para_info { 247*4882a593Smuzhiyun enum nhm_option_txon_all incld_txon; /*@Include TX on*/ 248*4882a593Smuzhiyun enum nhm_option_cca_all incld_cca; /*@Include CCA*/ 249*4882a593Smuzhiyun enum nhm_divider_opt_all div_opt; /*@divider option*/ 250*4882a593Smuzhiyun enum nhm_application nhm_app; 251*4882a593Smuzhiyun enum phydm_nhm_level nhm_lv; 252*4882a593Smuzhiyun u16 mntr_time; /*@0~262 unit ms*/ 253*4882a593Smuzhiyun boolean en_1db_mode; 254*4882a593Smuzhiyun u8 nhm_th0_manual; /* for 1-db mode*/ 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun struct clm_para_info { 258*4882a593Smuzhiyun enum clm_application clm_app; 259*4882a593Smuzhiyun enum phydm_clm_level clm_lv; 260*4882a593Smuzhiyun u16 mntr_time; /*@0~262 unit ms*/ 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun struct fahm_para_info { 264*4882a593Smuzhiyun enum fahm_application app; 265*4882a593Smuzhiyun enum phydm_fahm_level lv; 266*4882a593Smuzhiyun u16 mntr_time; /*0~262 unit ms*/ 267*4882a593Smuzhiyun u8 numer_opt; 268*4882a593Smuzhiyun u8 denom_opt; 269*4882a593Smuzhiyun boolean en_1db_mode; 270*4882a593Smuzhiyun u8 th0_manual;/* for 1-db mode*/ 271*4882a593Smuzhiyun }; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun struct ifs_clm_para_info { 274*4882a593Smuzhiyun enum ifs_clm_application ifs_clm_app; 275*4882a593Smuzhiyun enum phydm_ifs_clm_level ifs_clm_lv; 276*4882a593Smuzhiyun enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*unit*/ 277*4882a593Smuzhiyun u16 mntr_time; /*ms*/ 278*4882a593Smuzhiyun boolean ifs_clm_th_en[IFS_CLM_NUM]; 279*4882a593Smuzhiyun u16 ifs_clm_th_low[IFS_CLM_NUM]; 280*4882a593Smuzhiyun u16 ifs_clm_th_high[IFS_CLM_NUM]; 281*4882a593Smuzhiyun s16 th_shift; 282*4882a593Smuzhiyun }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun struct edcca_clm_para_info { 285*4882a593Smuzhiyun enum edcca_clm_application edcca_clm_app; 286*4882a593Smuzhiyun enum phydm_edcca_clm_level edcca_clm_lv; 287*4882a593Smuzhiyun }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun struct ccx_info { 290*4882a593Smuzhiyun u32 nhm_trigger_time; 291*4882a593Smuzhiyun u32 clm_trigger_time; 292*4882a593Smuzhiyun u32 fahm_trigger_time; 293*4882a593Smuzhiyun u32 ifs_clm_trigger_time; 294*4882a593Smuzhiyun u32 edcca_clm_trigger_time; 295*4882a593Smuzhiyun u64 start_time; /*@monitor for the test duration*/ 296*4882a593Smuzhiyun u8 ccx_watchdog_result; 297*4882a593Smuzhiyun #ifdef NHM_SUPPORT 298*4882a593Smuzhiyun enum nhm_application nhm_app; 299*4882a593Smuzhiyun enum nhm_option_txon_all nhm_include_txon; 300*4882a593Smuzhiyun enum nhm_option_cca_all nhm_include_cca; 301*4882a593Smuzhiyun enum nhm_divider_opt_all nhm_divider_opt; 302*4882a593Smuzhiyun /*Report*/ 303*4882a593Smuzhiyun u8 nhm_th[NHM_TH_NUM]; 304*4882a593Smuzhiyun u8 nhm_result[NHM_RPT_NUM]; 305*4882a593Smuzhiyun u8 nhm_wgt[NHM_RPT_NUM]; 306*4882a593Smuzhiyun u16 nhm_period; /* @4us per unit */ 307*4882a593Smuzhiyun u8 nhm_igi; 308*4882a593Smuzhiyun u8 nhm_manual_ctrl; 309*4882a593Smuzhiyun u8 nhm_ratio; /*@1% per nuit, it means the interference igi can't overcome.*/ 310*4882a593Smuzhiyun u8 nhm_env_ratio; /*exclude nhm_r[0] above -80dBm or first cluster under -80dBm*/ 311*4882a593Smuzhiyun u8 nhm_rpt_sum; 312*4882a593Smuzhiyun u16 nhm_duration; /*@Real time of NHM_VALID */ 313*4882a593Smuzhiyun u8 nhm_set_lv; 314*4882a593Smuzhiyun boolean nhm_ongoing; 315*4882a593Smuzhiyun u8 nhm_rpt_stamp; 316*4882a593Smuzhiyun u8 nhm_level; /*including r[0]~r[10]*/ 317*4882a593Smuzhiyun u8 nhm_level_valid; 318*4882a593Smuzhiyun u8 nhm_pwr; /*including r[0]~r[11]*/ 319*4882a593Smuzhiyun #ifdef NHM_DYM_PW_TH_SUPPORT 320*4882a593Smuzhiyun boolean nhm_dym_pw_th_en; 321*4882a593Smuzhiyun boolean dym_pwth_manual_ctrl; 322*4882a593Smuzhiyun u8 pw_th_rf20_ori; 323*4882a593Smuzhiyun u8 pw_th_rf20_cur; 324*4882a593Smuzhiyun u8 nhm_pw_th_max; 325*4882a593Smuzhiyun u8 nhm_period_decre; 326*4882a593Smuzhiyun u8 nhm_sl_pw_th; 327*4882a593Smuzhiyun #endif 328*4882a593Smuzhiyun #endif 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun #ifdef CLM_SUPPORT 331*4882a593Smuzhiyun enum clm_application clm_app; 332*4882a593Smuzhiyun u8 clm_manual_ctrl; 333*4882a593Smuzhiyun u8 clm_set_lv; 334*4882a593Smuzhiyun boolean clm_ongoing; 335*4882a593Smuzhiyun u16 clm_period; /* @4us per unit */ 336*4882a593Smuzhiyun u16 clm_result; 337*4882a593Smuzhiyun u8 clm_ratio; 338*4882a593Smuzhiyun u32 clm_fw_result_acc; 339*4882a593Smuzhiyun u8 clm_fw_result_cnt; 340*4882a593Smuzhiyun enum clm_monitor_mode clm_mntr_mode; 341*4882a593Smuzhiyun u8 clm_rpt_stamp; 342*4882a593Smuzhiyun #endif 343*4882a593Smuzhiyun #ifdef FAHM_SUPPORT 344*4882a593Smuzhiyun enum fahm_application fahm_app; 345*4882a593Smuzhiyun boolean fahm_ongoing; 346*4882a593Smuzhiyun u8 fahm_numer_opt; 347*4882a593Smuzhiyun u8 fahm_denom_opt; 348*4882a593Smuzhiyun boolean fahm_inclu_cck; 349*4882a593Smuzhiyun u8 fahm_th[NHM_TH_NUM]; 350*4882a593Smuzhiyun u16 fahm_result[NHM_RPT_NUM]; 351*4882a593Smuzhiyun u16 fahm_result_sum; 352*4882a593Smuzhiyun u16 fahm_denom_result; 353*4882a593Smuzhiyun u16 fahm_period; /*unit: 4us*/ 354*4882a593Smuzhiyun u8 fahm_igi; 355*4882a593Smuzhiyun u8 fahm_manual_ctrl; 356*4882a593Smuzhiyun u8 fahm_set_lv; 357*4882a593Smuzhiyun u8 fahm_rpt_stamp; 358*4882a593Smuzhiyun u8 fahm_pwr; /*including r[0]~r[11]*/ 359*4882a593Smuzhiyun u8 fahm_ratio; 360*4882a593Smuzhiyun u8 fahm_denom_ratio; 361*4882a593Smuzhiyun #endif 362*4882a593Smuzhiyun #ifdef IFS_CLM_SUPPORT 363*4882a593Smuzhiyun enum ifs_clm_application ifs_clm_app; 364*4882a593Smuzhiyun /*Control*/ 365*4882a593Smuzhiyun enum phydm_ifs_clm_unit ifs_clm_ctrl_unit; /*4,8,12,16us per unit*/ 366*4882a593Smuzhiyun u16 ifs_clm_period; 367*4882a593Smuzhiyun boolean ifs_clm_th_en[IFS_CLM_NUM]; 368*4882a593Smuzhiyun u16 ifs_clm_th_low[IFS_CLM_NUM]; 369*4882a593Smuzhiyun u16 ifs_clm_th_high[IFS_CLM_NUM]; 370*4882a593Smuzhiyun /*Flow control*/ 371*4882a593Smuzhiyun u8 ifs_clm_set_lv; 372*4882a593Smuzhiyun u8 ifs_clm_manual_ctrl; 373*4882a593Smuzhiyun boolean ifs_clm_ongoing; 374*4882a593Smuzhiyun /*Report*/ 375*4882a593Smuzhiyun u8 ifs_clm_rpt_stamp; 376*4882a593Smuzhiyun u16 ifs_clm_tx; 377*4882a593Smuzhiyun u16 ifs_clm_edcca_excl_cca; 378*4882a593Smuzhiyun u16 ifs_clm_ofdmfa; 379*4882a593Smuzhiyun u16 ifs_clm_ofdmcca_excl_fa; 380*4882a593Smuzhiyun u16 ifs_clm_cckfa; 381*4882a593Smuzhiyun u16 ifs_clm_cckcca_excl_fa; 382*4882a593Smuzhiyun u8 ifs_clm_his[IFS_CLM_NUM]; /*trx_neg_edge to CCA/FA posedge per times*/ 383*4882a593Smuzhiyun u16 ifs_clm_total_cca; 384*4882a593Smuzhiyun u16 ifs_clm_avg[IFS_CLM_NUM]; /*4,8,12,16us per unit*/ 385*4882a593Smuzhiyun u16 ifs_clm_avg_cca[IFS_CLM_NUM]; /*4,8,12,16us per unit*/ 386*4882a593Smuzhiyun u8 ifs_clm_tx_ratio; 387*4882a593Smuzhiyun u8 ifs_clm_edcca_excl_cca_ratio; 388*4882a593Smuzhiyun u8 ifs_clm_cck_fa_ratio; 389*4882a593Smuzhiyun u8 ifs_clm_cck_cca_excl_fa_ratio; 390*4882a593Smuzhiyun u8 ifs_clm_ofdm_fa_ratio; 391*4882a593Smuzhiyun u8 ifs_clm_ofdm_cca_excl_fa_ratio; 392*4882a593Smuzhiyun #endif 393*4882a593Smuzhiyun #ifdef EDCCA_CLM_SUPPORT 394*4882a593Smuzhiyun enum edcca_clm_application edcca_clm_app; 395*4882a593Smuzhiyun u8 edcca_clm_manual_ctrl; 396*4882a593Smuzhiyun u8 edcca_clm_set_lv; 397*4882a593Smuzhiyun boolean edcca_clm_ongoing; 398*4882a593Smuzhiyun u16 edcca_clm_result; 399*4882a593Smuzhiyun u8 edcca_clm_ratio; 400*4882a593Smuzhiyun u8 edcca_clm_rpt_stamp; 401*4882a593Smuzhiyun #endif 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun /* @1 ============================================================ 405*4882a593Smuzhiyun * 1 Function Prototype 406*4882a593Smuzhiyun * 1 ============================================================ 407*4882a593Smuzhiyun */ 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun #ifdef FAHM_SUPPORT 410*4882a593Smuzhiyun void phydm_fahm_init(void *dm_void); 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun void phydm_fahm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, 413*4882a593Smuzhiyun u32 *_out_len); 414*4882a593Smuzhiyun #endif 415*4882a593Smuzhiyun 416*4882a593Smuzhiyun #ifdef NHM_SUPPORT 417*4882a593Smuzhiyun void phydm_nhm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, 418*4882a593Smuzhiyun u32 *_out_len); 419*4882a593Smuzhiyun u8 phydm_get_igi(void *dm_void, enum bb_path path); 420*4882a593Smuzhiyun #endif 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun #ifdef CLM_SUPPORT 423*4882a593Smuzhiyun void phydm_clm_c2h_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len); 424*4882a593Smuzhiyun 425*4882a593Smuzhiyun void phydm_clm_dbg(void *dm_void, char input[][16], u32 *_used, char *output, 426*4882a593Smuzhiyun u32 *_out_len); 427*4882a593Smuzhiyun #endif 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun u8 phydm_env_mntr_trigger(void *dm_void, struct nhm_para_info *nhm_para, 430*4882a593Smuzhiyun struct clm_para_info *clm_para, 431*4882a593Smuzhiyun struct env_trig_rpt *rpt); 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun u8 phydm_env_mntr_result(void *dm_void, struct env_mntr_rpt *rpt); 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun void phydm_env_mntr_dbg(void *dm_void, char input[][16], u32 *_used, 436*4882a593Smuzhiyun char *output, u32 *_out_len); 437*4882a593Smuzhiyun 438*4882a593Smuzhiyun #ifdef IFS_CLM_SUPPORT 439*4882a593Smuzhiyun void phydm_ifs_clm_dbg(void *dm_void, char input[][16], u32 *_used, 440*4882a593Smuzhiyun char *output, u32 *_out_len); 441*4882a593Smuzhiyun #endif 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun u8 phydm_enhance_mntr_trigger(void *dm_void, 444*4882a593Smuzhiyun struct nhm_para_info *nhm_para, 445*4882a593Smuzhiyun struct clm_para_info *clm_para, 446*4882a593Smuzhiyun struct fahm_para_info *fahm_para, 447*4882a593Smuzhiyun struct ifs_clm_para_info *ifs_clm_para, 448*4882a593Smuzhiyun struct enhance_mntr_trig_rpt *trig_rpt); 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun u8 phydm_enhance_mntr_result(void *dm_void, struct enhance_mntr_rpt *rpt); 451*4882a593Smuzhiyun 452*4882a593Smuzhiyun void phydm_enhance_mntr_dbg(void *dm_void, char input[][16], u32 *_used, 453*4882a593Smuzhiyun char *output, u32 *_out_len); 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun #ifdef EDCCA_CLM_SUPPORT 456*4882a593Smuzhiyun void phydm_edcca_clm_dbg(void *dm_void, char input[][16], u32 *_used, 457*4882a593Smuzhiyun char *output, u32 *_out_len); 458*4882a593Smuzhiyun #endif 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun void phydm_env_mntr_result_watchdog(void *dm_void); 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun void phydm_env_mntr_set_watchdog(void *dm_void); 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun u8 phydm_env_mntr_get_802_11_k_rsni(void *dm_void, s8 rcpi, s8 anpi); 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun void phydm_env_monitor_init(void *dm_void); 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun #endif 469