1 /****************************************************************************** 2 * 3 * Copyright(c) 2016 - 2019 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 #ifndef __INC_HALMAC_REG_8197F_H 17 #define __INC_HALMAC_REG_8197F_H 18 19 #define REG_SYS_ISO_CTRL_8197F 0x0000 20 #define REG_SYS_FUNC_EN_8197F 0x0002 21 #define REG_SYS_PW_CTRL_8197F 0x0004 22 #define REG_SYS_CLK_CTRL_8197F 0x0008 23 #define REG_SYS_EEPROM_CTRL_8197F 0x000A 24 #define REG_EE_VPD_8197F 0x000C 25 #define REG_SYS_SWR_CTRL1_8197F 0x0010 26 #define REG_SYS_SWR_CTRL2_8197F 0x0014 27 #define REG_SYS_SWR_CTRL3_8197F 0x0018 28 #define REG_RSV_CTRL_8197F 0x001C 29 #define REG_RF0_CTRL_8197F 0x001F 30 #define REG_AFE_LDO_CTRL_8197F 0x0020 31 #define REG_AFE_CTRL1_8197F 0x0024 32 #define REG_AFE_CTRL2_8197F 0x0028 33 #define REG_AFE_CTRL3_8197F 0x002C 34 #define REG_EFUSE_CTRL_8197F 0x0030 35 #define REG_LDO_EFUSE_CTRL_8197F 0x0034 36 #define REG_PWR_OPTION_CTRL_8197F 0x0038 37 #define REG_CAL_TIMER_8197F 0x003C 38 #define REG_ACLK_MON_8197F 0x003E 39 #define REG_GPIO_MUXCFG_8197F 0x0040 40 #define REG_GPIO_PIN_CTRL_8197F 0x0044 41 #define REG_GPIO_INTM_8197F 0x0048 42 #define REG_LED_CFG_8197F 0x004C 43 #define REG_FSIMR_8197F 0x0050 44 #define REG_FSISR_8197F 0x0054 45 #define REG_HSIMR_8197F 0x0058 46 #define REG_HSISR_8197F 0x005C 47 #define REG_GPIO_EXT_CTRL_8197F 0x0060 48 #define REG_PAD_CTRL1_8197F 0x0064 49 #define REG_WL_BT_PWR_CTRL_8197F 0x0068 50 #define REG_SDM_DEBUG_8197F 0x006C 51 #define REG_SYS_SDIO_CTRL_8197F 0x0070 52 #define REG_HCI_OPT_CTRL_8197F 0x0074 53 #define REG_AFE_CTRL4_8197F 0x0078 54 #define REG_LDO_SWR_CTRL_8197F 0x007C 55 #define REG_MCUFW_CTRL_8197F 0x0080 56 #define REG_MCU_TST_CFG_8197F 0x0084 57 #define REG_HMEBOX_E0_E1_8197F 0x0088 58 #define REG_HMEBOX_E2_E3_8197F 0x008C 59 #define REG_WLLPS_CTRL_8197F 0x0090 60 #define REG_AFE_CTRL5_8197F 0x0094 61 #define REG_GPIO_DEBOUNCE_CTRL_8197F 0x0098 62 #define REG_RPWM2_8197F 0x009C 63 #define REG_SYSON_FSM_MON_8197F 0x00A0 64 #define REG_AFE_CTRL6_8197F 0x00A4 65 #define REG_PMC_DBG_CTRL1_8197F 0x00A8 66 #define REG_AFE_CTRL7_8197F 0x00AC 67 #define REG_HIMR0_8197F 0x00B0 68 #define REG_HISR0_8197F 0x00B4 69 #define REG_HIMR1_8197F 0x00B8 70 #define REG_HISR1_8197F 0x00BC 71 #define REG_DBG_PORT_SEL_8197F 0x00C0 72 #define REG_PAD_CTRL2_8197F 0x00C4 73 #define REG_PMC_DBG_CTRL2_8197F 0x00CC 74 #define REG_BIST_CTRL_8197F 0x00D0 75 #define REG_BIST_RPT_8197F 0x00D4 76 #define REG_MEM_CTRL_8197F 0x00D8 77 #define REG_AFE_CTRL8_8197F 0x00DC 78 #define REG_USB_SIE_INTF_8197F 0x00E0 79 #define REG_PCIE_MIO_INTF_8197F 0x00E4 80 #define REG_PCIE_MIO_INTD_8197F 0x00E8 81 #define REG_WLRF1_8197F 0x00EC 82 #define REG_SYS_CFG1_8197F 0x00F0 83 #define REG_SYS_STATUS1_8197F 0x00F4 84 #define REG_SYS_STATUS2_8197F 0x00F8 85 #define REG_SYS_CFG2_8197F 0x00FC 86 #define REG_SYS_CFG3_8197F 0x1000 87 #define REG_SYS_CFG4_8197F 0x1034 88 #define REG_CPU_DMEM_CON_8197F 0x1080 89 #define REG_HIMR2_8197F 0x10B0 90 #define REG_HISR2_8197F 0x10B4 91 #define REG_HIMR3_8197F 0x10B8 92 #define REG_HISR3_8197F 0x10BC 93 #define REG_SW_MDIO_8197F 0x10C0 94 #define REG_SW_FLUSH_8197F 0x10C4 95 #define REG_DBG_GPIO_BMUX_8197F 0x10C8 96 #define REG_FPGA_TAG_8197F 0x10CC 97 #define REG_WL_DSS_CTRL0_8197F 0x10D0 98 #define REG_WL_DSS_CTRL1_8197F 0x10D8 99 #define REG_WL_DSS_STATUS1_8197F 0x10DC 100 #define REG_FW_DBG0_8197F 0x10E0 101 #define REG_FW_DBG1_8197F 0x10E4 102 #define REG_FW_DBG2_8197F 0x10E8 103 #define REG_FW_DBG3_8197F 0x10EC 104 #define REG_FW_DBG4_8197F 0x10F0 105 #define REG_FW_DBG5_8197F 0x10F4 106 #define REG_FW_DBG6_8197F 0x10F8 107 #define REG_FW_DBG7_8197F 0x10FC 108 #define REG_CR_8197F 0x0100 109 #define REG_TSF_CLK_STATE_8197F 0x0108 110 #define REG_TXDMA_PQ_MAP_8197F 0x010C 111 #define REG_TRXFF_BNDY_8197F 0x0114 112 #define REG_PTA_I2C_MBOX_8197F 0x0118 113 #define REG_RXFF_BNDY_8197F 0x011C 114 #define REG_FE1IMR_8197F 0x0120 115 #define REG_FE1ISR_8197F 0x0124 116 #define REG_CPWM_8197F 0x012C 117 #define REG_FWIMR_8197F 0x0130 118 #define REG_FWISR_8197F 0x0134 119 #define REG_FTIMR_8197F 0x0138 120 #define REG_FTISR_8197F 0x013C 121 #define REG_PKTBUF_DBG_CTRL_8197F 0x0140 122 #define REG_PKTBUF_DBG_DATA_L_8197F 0x0144 123 #define REG_PKTBUF_DBG_DATA_H_8197F 0x0148 124 #define REG_CPWM2_8197F 0x014C 125 #define REG_TC0_CTRL_8197F 0x0150 126 #define REG_TC1_CTRL_8197F 0x0154 127 #define REG_TC2_CTRL_8197F 0x0158 128 #define REG_TC3_CTRL_8197F 0x015C 129 #define REG_TC4_CTRL_8197F 0x0160 130 #define REG_TCUNIT_BASE_8197F 0x0164 131 #define REG_TC5_CTRL_8197F 0x0168 132 #define REG_TC6_CTRL_8197F 0x016C 133 #define REG_MBIST_FAIL_8197F 0x0170 134 #define REG_MBIST_START_PAUSE_8197F 0x0174 135 #define REG_MBIST_DONE_8197F 0x0178 136 #define REG_MBIST_FAIL_NRML_8197F 0x017C 137 #define REG_AES_DECRPT_DATA_8197F 0x0180 138 #define REG_AES_DECRPT_CFG_8197F 0x0184 139 #define REG_MACCLKFRQ_8197F 0x018C 140 #define REG_TMETER_8197F 0x0190 141 #define REG_OSC_32K_CTRL_8197F 0x0194 142 #define REG_32K_CAL_REG1_8197F 0x0198 143 #define REG_C2HEVT_8197F 0x01A0 144 #define REG_SW_DEFINED_PAGE1_8197F 0x01B8 145 #define REG_MCUTST_I_8197F 0x01C0 146 #define REG_MCUTST_II_8197F 0x01C4 147 #define REG_FMETHR_8197F 0x01C8 148 #define REG_HMETFR_8197F 0x01CC 149 #define REG_HMEBOX0_8197F 0x01D0 150 #define REG_HMEBOX1_8197F 0x01D4 151 #define REG_HMEBOX2_8197F 0x01D8 152 #define REG_HMEBOX3_8197F 0x01DC 153 #define REG_LLT_INIT_8197F 0x01E0 154 #define REG_LLT_INIT_ADDR_8197F 0x01E4 155 #define REG_BB_ACCESS_CTRL_8197F 0x01E8 156 #define REG_BB_ACCESS_DATA_8197F 0x01EC 157 #define REG_HMEBOX_E0_8197F 0x01F0 158 #define REG_HMEBOX_E1_8197F 0x01F4 159 #define REG_HMEBOX_E2_8197F 0x01F8 160 #define REG_HMEBOX_E3_8197F 0x01FC 161 #define REG_CR_EXT_8197F 0x1100 162 #define REG_FWFF_8197F 0x1114 163 #define REG_RXFF_PTR_V1_8197F 0x1118 164 #define REG_RXFF_WTR_V1_8197F 0x111C 165 #define REG_FE2IMR_8197F 0x1120 166 #define REG_FE2ISR_8197F 0x1124 167 #define REG_FE3IMR_8197F 0x1128 168 #define REG_FE3ISR_8197F 0x112C 169 #define REG_FE4IMR_8197F 0x1130 170 #define REG_FE4ISR_8197F 0x1134 171 #define REG_FT1IMR_8197F 0x1138 172 #define REG_FT1ISR_8197F 0x113C 173 #define REG_SPWR0_8197F 0x1140 174 #define REG_SPWR1_8197F 0x1144 175 #define REG_SPWR2_8197F 0x1148 176 #define REG_SPWR3_8197F 0x114C 177 #define REG_POWSEQ_8197F 0x1150 178 #define REG_TC7_CTRL_V1_8197F 0x1158 179 #define REG_TC8_CTRL_V1_8197F 0x115C 180 #define REG_RXBCN_TBTT_INTERVAL_PORT0TO3_8197F 0x1160 181 #define REG_RXBCN_TBTT_INTERVAL_PORT4_8197F 0x1164 182 #define REG_EXT_QUEUE_REG_8197F 0x11C0 183 #define REG_COUNTER_CONTROL_8197F 0x11C4 184 #define REG_COUNTER_TH_8197F 0x11C8 185 #define REG_COUNTER_SET_8197F 0x11CC 186 #define REG_COUNTER_OVERFLOW_8197F 0x11D0 187 #define REG_TDE_LEN_TH_8197F 0x11D4 188 #define REG_RDE_LEN_TH_8197F 0x11D8 189 #define REG_PCIE_EXEC_TIME_8197F 0x11DC 190 #define REG_FT2IMR_8197F 0x11E0 191 #define REG_FT2ISR_8197F 0x11E4 192 #define REG_MSG2_8197F 0x11F0 193 #define REG_MSG3_8197F 0x11F4 194 #define REG_MSG4_8197F 0x11F8 195 #define REG_MSG5_8197F 0x11FC 196 #define REG_FIFOPAGE_CTRL_1_8197F 0x0200 197 #define REG_FIFOPAGE_CTRL_2_8197F 0x0204 198 #define REG_AUTO_LLT_V1_8197F 0x0208 199 #define REG_TXDMA_OFFSET_CHK_8197F 0x020C 200 #define REG_TXDMA_STATUS_8197F 0x0210 201 #define REG_TX_DMA_DBG_8197F 0x0214 202 #define REG_TQPNT1_8197F 0x0218 203 #define REG_TQPNT2_8197F 0x021C 204 #define REG_TQPNT3_8197F 0x0220 205 #define REG_TQPNT4_8197F 0x0224 206 #define REG_RQPN_CTRL_1_8197F 0x0228 207 #define REG_RQPN_CTRL_2_8197F 0x022C 208 #define REG_FIFOPAGE_INFO_1_8197F 0x0230 209 #define REG_FIFOPAGE_INFO_2_8197F 0x0234 210 #define REG_FIFOPAGE_INFO_3_8197F 0x0238 211 #define REG_FIFOPAGE_INFO_4_8197F 0x023C 212 #define REG_FIFOPAGE_INFO_5_8197F 0x0240 213 #define REG_H2C_HEAD_8197F 0x0244 214 #define REG_H2C_TAIL_8197F 0x0248 215 #define REG_H2C_READ_ADDR_8197F 0x024C 216 #define REG_H2C_WR_ADDR_8197F 0x0250 217 #define REG_H2C_INFO_8197F 0x0254 218 #define REG_RXDMA_AGG_PG_TH_8197F 0x0280 219 #define REG_RXPKT_NUM_8197F 0x0284 220 #define REG_RXDMA_STATUS_8197F 0x0288 221 #define REG_RXDMA_DPR_8197F 0x028C 222 #define REG_RXDMA_MODE_8197F 0x0290 223 #define REG_C2H_PKT_8197F 0x0294 224 #define REG_FWFF_C2H_8197F 0x0298 225 #define REG_FWFF_CTRL_8197F 0x029C 226 #define REG_FWFF_PKT_INFO_8197F 0x02A0 227 #define REG_FC2H_INFO_8197F 0x02A4 228 #define REG_DDMA_CH0SA_8197F 0x1200 229 #define REG_DDMA_CH0DA_8197F 0x1204 230 #define REG_DDMA_CH0CTRL_8197F 0x1208 231 #define REG_DDMA_CH1SA_8197F 0x1210 232 #define REG_DDMA_CH1DA_8197F 0x1214 233 #define REG_DDMA_CH1CTRL_8197F 0x1218 234 #define REG_DDMA_CH2SA_8197F 0x1220 235 #define REG_DDMA_CH2DA_8197F 0x1224 236 #define REG_DDMA_CH2CTRL_8197F 0x1228 237 #define REG_DDMA_CH3SA_8197F 0x1230 238 #define REG_DDMA_CH3DA_8197F 0x1234 239 #define REG_DDMA_CH3CTRL_8197F 0x1238 240 #define REG_DDMA_CH4SA_8197F 0x1240 241 #define REG_DDMA_CH4DA_8197F 0x1244 242 #define REG_DDMA_CH4CTRL_8197F 0x1248 243 #define REG_DDMA_CH5SA_8197F 0x1250 244 #define REG_DDMA_CH5DA_8197F 0x1254 245 #define REG_REG_DDMA_CH5CTRL_8197F 0x1258 246 #define REG_DDMA_INT_MSK_8197F 0x12E0 247 #define REG_DDMA_CHSTATUS_8197F 0x12E8 248 #define REG_DDMA_CHKSUM_8197F 0x12F0 249 #define REG_DDMA_MONITOR_8197F 0x12FC 250 #define REG_HCI_CTRL_8197F 0x0300 251 #define REG_INT_MIG_8197F 0x0304 252 #define REG_BCNQ_TXBD_DESA_8197F 0x0308 253 #define REG_MGQ_TXBD_DESA_8197F 0x0310 254 #define REG_VOQ_TXBD_DESA_8197F 0x0318 255 #define REG_VIQ_TXBD_DESA_8197F 0x0320 256 #define REG_BEQ_TXBD_DESA_8197F 0x0328 257 #define REG_BKQ_TXBD_DESA_8197F 0x0330 258 #define REG_RXQ_RXBD_DESA_8197F 0x0338 259 #define REG_HI0Q_TXBD_DESA_8197F 0x0340 260 #define REG_HI1Q_TXBD_DESA_8197F 0x0348 261 #define REG_HI2Q_TXBD_DESA_8197F 0x0350 262 #define REG_HI3Q_TXBD_DESA_8197F 0x0358 263 #define REG_HI4Q_TXBD_DESA_8197F 0x0360 264 #define REG_HI5Q_TXBD_DESA_8197F 0x0368 265 #define REG_HI6Q_TXBD_DESA_8197F 0x0370 266 #define REG_HI7Q_TXBD_DESA_8197F 0x0378 267 #define REG_MGQ_TXBD_NUM_8197F 0x0380 268 #define REG_RX_RXBD_NUM_8197F 0x0382 269 #define REG_VOQ_TXBD_NUM_8197F 0x0384 270 #define REG_VIQ_TXBD_NUM_8197F 0x0386 271 #define REG_BEQ_TXBD_NUM_8197F 0x0388 272 #define REG_BKQ_TXBD_NUM_8197F 0x038A 273 #define REG_HI0Q_TXBD_NUM_8197F 0x038C 274 #define REG_HI1Q_TXBD_NUM_8197F 0x038E 275 #define REG_HI2Q_TXBD_NUM_8197F 0x0390 276 #define REG_HI3Q_TXBD_NUM_8197F 0x0392 277 #define REG_HI4Q_TXBD_NUM_8197F 0x0394 278 #define REG_HI5Q_TXBD_NUM_8197F 0x0396 279 #define REG_HI6Q_TXBD_NUM_8197F 0x0398 280 #define REG_HI7Q_TXBD_NUM_8197F 0x039A 281 #define REG_TSFTIMER_HCI_8197F 0x039C 282 #define REG_BD_RWPTR_CLR_8197F 0x039C 283 #define REG_VOQ_TXBD_IDX_8197F 0x03A0 284 #define REG_VIQ_TXBD_IDX_8197F 0x03A4 285 #define REG_BEQ_TXBD_IDX_8197F 0x03A8 286 #define REG_BKQ_TXBD_IDX_8197F 0x03AC 287 #define REG_MGQ_TXBD_IDX_8197F 0x03B0 288 #define REG_RXQ_RXBD_IDX_8197F 0x03B4 289 #define REG_HI0Q_TXBD_IDX_8197F 0x03B8 290 #define REG_HI1Q_TXBD_IDX_8197F 0x03BC 291 #define REG_HI2Q_TXBD_IDX_8197F 0x03C0 292 #define REG_HI3Q_TXBD_IDX_8197F 0x03C4 293 #define REG_HI4Q_TXBD_IDX_8197F 0x03C8 294 #define REG_HI5Q_TXBD_IDX_8197F 0x03CC 295 #define REG_HI6Q_TXBD_IDX_8197F 0x03D0 296 #define REG_HI7Q_TXBD_IDX_8197F 0x03D4 297 #define REG_DBG_SEL_V1_8197F 0x03D8 298 #define REG_HCI_HRPWM1_V1_8197F 0x03D9 299 #define REG_HCI_HCPWM1_V1_8197F 0x03DA 300 #define REG_HCI_CTRL2_8197F 0x03DB 301 #define REG_HCI_HRPWM2_V1_8197F 0x03DC 302 #define REG_HCI_HCPWM2_V1_8197F 0x03DE 303 #define REG_HCI_H2C_MSG_V1_8197F 0x03E0 304 #define REG_HCI_C2H_MSG_V1_8197F 0x03E4 305 #define REG_DBI_WDATA_V1_8197F 0x03E8 306 #define REG_DBI_RDATA_V1_8197F 0x03EC 307 #define REG_STUCK_FLAG_V1_8197F 0x03F0 308 #define REG_MDIO_V1_8197F 0x03F4 309 #define REG_WDT_CFG_8197F 0x03F8 310 #define REG_HCI_MIX_CFG_8197F 0x03FC 311 #define REG_STC_INT_CS_8197F 0x1300 312 #define REG_ST_INT_CFG_8197F 0x1304 313 #define REG_CMU_DLY_CTRL_8197F 0x1310 314 #define REG_CMU_DLY_CFG_8197F 0x1314 315 #define REG_H2CQ_TXBD_DESA_8197F 0x1320 316 #define REG_H2CQ_TXBD_NUM_8197F 0x1328 317 #define REG_H2CQ_TXBD_IDX_8197F 0x132C 318 #define REG_H2CQ_CSR_8197F 0x1330 319 #define REG_AXI_EXCEPT_CS_8197F 0x1350 320 #define REG_AXI_EXCEPT_TIME_8197F 0x1354 321 #define REG_Q0_INFO_8197F 0x0400 322 #define REG_Q1_INFO_8197F 0x0404 323 #define REG_Q2_INFO_8197F 0x0408 324 #define REG_Q3_INFO_8197F 0x040C 325 #define REG_MGQ_INFO_8197F 0x0410 326 #define REG_HIQ_INFO_8197F 0x0414 327 #define REG_BCNQ_INFO_8197F 0x0418 328 #define REG_TXPKT_EMPTY_8197F 0x041A 329 #define REG_CPU_MGQ_INFO_8197F 0x041C 330 #define REG_FWHW_TXQ_CTRL_8197F 0x0420 331 #define REG_BCNQ_BDNY_V1_8197F 0x0424 332 #define REG_LIFETIME_EN_8197F 0x0426 333 #define REG_SPEC_SIFS_8197F 0x0428 334 #define REG_RETRY_LIMIT_8197F 0x042A 335 #define REG_TXBF_CTRL_8197F 0x042C 336 #define REG_DARFRC_8197F 0x0430 337 #define REG_RARFRC_8197F 0x0438 338 #define REG_RRSR_8197F 0x0440 339 #define REG_ARFR0_8197F 0x0444 340 #define REG_ARFR1_V1_8197F 0x044C 341 #define REG_CCK_CHECK_8197F 0x0454 342 #define REG_AMPDU_MAX_TIME_V1_8197F 0x0455 343 #define REG_BCNQ1_BDNY_V1_8197F 0x0456 344 #define REG_AMPDU_MAX_LENGTH_8197F 0x0458 345 #define REG_ACQ_STOP_8197F 0x045C 346 #define REG_NDPA_RATE_8197F 0x045D 347 #define REG_TX_HANG_CTRL_8197F 0x045E 348 #define REG_NDPA_OPT_CTRL_8197F 0x045F 349 #define REG_RD_RESP_PKT_TH_8197F 0x0463 350 #define REG_CMDQ_INFO_8197F 0x0464 351 #define REG_Q4_INFO_8197F 0x0468 352 #define REG_Q5_INFO_8197F 0x046C 353 #define REG_Q6_INFO_8197F 0x0470 354 #define REG_Q7_INFO_8197F 0x0474 355 #define REG_WMAC_LBK_BUF_HD_V1_8197F 0x0478 356 #define REG_MGQ_BDNY_V1_8197F 0x047A 357 #define REG_TXRPT_CTRL_8197F 0x047C 358 #define REG_INIRTS_RATE_SEL_8197F 0x0480 359 #define REG_BASIC_CFEND_RATE_8197F 0x0481 360 #define REG_STBC_CFEND_RATE_8197F 0x0482 361 #define REG_DATA_SC_8197F 0x0483 362 #define REG_MACID_SLEEP3_8197F 0x0484 363 #define REG_MACID_SLEEP1_8197F 0x0488 364 #define REG_ARFR2_V1_8197F 0x048C 365 #define REG_ARFR3_V1_8197F 0x0494 366 #define REG_ARFR4_8197F 0x049C 367 #define REG_ARFR5_8197F 0x04A4 368 #define REG_TXRPT_START_OFFSET_8197F 0x04AC 369 #define REG_POWER_STAGE1_8197F 0x04B4 370 #define REG_POWER_STAGE2_8197F 0x04B8 371 #define REG_SW_AMPDU_BURST_MODE_CTRL_8197F 0x04BC 372 #define REG_PKT_LIFE_TIME_8197F 0x04C0 373 #define REG_STBC_SETTING_8197F 0x04C4 374 #define REG_STBC_SETTING2_8197F 0x04C5 375 #define REG_QUEUE_CTRL_8197F 0x04C6 376 #define REG_SINGLE_AMPDU_CTRL_8197F 0x04C7 377 #define REG_PROT_MODE_CTRL_8197F 0x04C8 378 #define REG_BAR_MODE_CTRL_8197F 0x04CC 379 #define REG_RA_TRY_RATE_AGG_LMT_8197F 0x04CF 380 #define REG_MACID_SLEEP2_8197F 0x04D0 381 #define REG_MACID_SLEEP_8197F 0x04D4 382 #define REG_HW_SEQ0_8197F 0x04D8 383 #define REG_HW_SEQ1_8197F 0x04DA 384 #define REG_HW_SEQ2_8197F 0x04DC 385 #define REG_HW_SEQ3_8197F 0x04DE 386 #define REG_NULL_PKT_STATUS_V1_8197F 0x04E0 387 #define REG_PTCL_ERR_STATUS_8197F 0x04E2 388 #define REG_NULL_PKT_STATUS_EXTEND_8197F 0x04E3 389 #define REG_VIDEO_ENHANCEMENT_FUN_8197F 0x04E4 390 #define REG_BT_POLLUTE_PKT_CNT_8197F 0x04E8 391 #define REG_PTCL_DBG_8197F 0x04EC 392 #define REG_TXOP_EXTRA_CTRL_8197F 0x04F0 393 #define REG_CPUMGQ_TIMER_CTRL2_8197F 0x04F4 394 #define REG_DUMMY_PAGE4_8197F 0x04FC 395 #define REG_Q0_Q1_INFO_8197F 0x1400 396 #define REG_Q2_Q3_INFO_8197F 0x1404 397 #define REG_Q4_Q5_INFO_8197F 0x1408 398 #define REG_Q6_Q7_INFO_8197F 0x140C 399 #define REG_MGQ_HIQ_INFO_8197F 0x1410 400 #define REG_CMDQ_BCNQ_INFO_8197F 0x1414 401 #define REG_USEREG_SETTING_8197F 0x1420 402 #define REG_AESIV_SETTING_8197F 0x1424 403 #define REG_BF0_TIME_SETTING_8197F 0x1428 404 #define REG_BF1_TIME_SETTING_8197F 0x142C 405 #define REG_BF_TIMEOUT_EN_8197F 0x1430 406 #define REG_MACID_RELEASE0_8197F 0x1434 407 #define REG_MACID_RELEASE1_8197F 0x1438 408 #define REG_MACID_RELEASE2_8197F 0x143C 409 #define REG_MACID_RELEASE3_8197F 0x1440 410 #define REG_MACID_RELEASE_SETTING_8197F 0x1444 411 #define REG_FAST_EDCA_VOVI_SETTING_8197F 0x1448 412 #define REG_FAST_EDCA_BEBK_SETTING_8197F 0x144C 413 #define REG_MACID_DROP0_8197F 0x1450 414 #define REG_MACID_DROP1_8197F 0x1454 415 #define REG_MACID_DROP2_8197F 0x1458 416 #define REG_MACID_DROP3_8197F 0x145C 417 #define REG_R_MACID_RELEASE_SUCCESS_0_8197F 0x1460 418 #define REG_R_MACID_RELEASE_SUCCESS_1_8197F 0x1464 419 #define REG_R_MACID_RELEASE_SUCCESS_2_8197F 0x1468 420 #define REG_R_MACID_RELEASE_SUCCESS_3_8197F 0x146C 421 #define REG_MGG_FIFO_CRTL_8197F 0x1470 422 #define REG_MGG_FIFO_INT_8197F 0x1474 423 #define REG_MGG_FIFO_LIFETIME_8197F 0x1478 424 #define REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET_8197F 0x147C 425 #define REG_SHCUT_SETTING_8197F 0x1480 426 #define REG_SHCUT_LLC_ETH_TYPE0_8197F 0x1484 427 #define REG_SHCUT_LLC_ETH_TYPE1_8197F 0x1488 428 #define REG_SHCUT_LLC_OUI0_8197F 0x148C 429 #define REG_SHCUT_LLC_OUI1_8197F 0x1490 430 #define REG_SHCUT_LLC_OUI2_8197F 0x1494 431 #define REG_SHCUT_LLC_OUI3_8197F 0x1498 432 #define REG_CHNL_INFO_CTRL_8197F 0x14D0 433 #define REG_CHNL_IDLE_TIME_8197F 0x14D4 434 #define REG_CHNL_BUSY_TIME_8197F 0x14D8 435 #define REG_EDCA_VO_PARAM_8197F 0x0500 436 #define REG_EDCA_VI_PARAM_8197F 0x0504 437 #define REG_EDCA_BE_PARAM_8197F 0x0508 438 #define REG_EDCA_BK_PARAM_8197F 0x050C 439 #define REG_BCNTCFG_8197F 0x0510 440 #define REG_PIFS_8197F 0x0512 441 #define REG_RDG_PIFS_8197F 0x0513 442 #define REG_SIFS_8197F 0x0514 443 #define REG_TSFTR_SYN_OFFSET_8197F 0x0518 444 #define REG_AGGR_BREAK_TIME_8197F 0x051A 445 #define REG_SLOT_8197F 0x051B 446 #define REG_TX_PTCL_CTRL_8197F 0x0520 447 #define REG_TXPAUSE_8197F 0x0522 448 #define REG_DIS_TXREQ_CLR_8197F 0x0523 449 #define REG_RD_CTRL_8197F 0x0524 450 #define REG_MBSSID_CTRL_8197F 0x0526 451 #define REG_P2PPS_CTRL_8197F 0x0527 452 #define REG_PKT_LIFETIME_CTRL_8197F 0x0528 453 #define REG_P2PPS_SPEC_STATE_8197F 0x052B 454 #define REG_QUEUE_INCOL_THR_8197F 0x0538 455 #define REG_QUEUE_INCOL_EN_8197F 0x053C 456 #define REG_TBTT_PROHIBIT_8197F 0x0540 457 #define REG_P2PPS_STATE_8197F 0x0543 458 #define REG_RD_NAV_NXT_8197F 0x0544 459 #define REG_NAV_PROT_LEN_8197F 0x0546 460 #define REG_FTM_CTRL_8197F 0x0548 461 #define REG_FTM_TSF_CNT_8197F 0x054C 462 #define REG_BCN_CTRL_8197F 0x0550 463 #define REG_BCN_CTRL_CLINT0_8197F 0x0551 464 #define REG_MBID_NUM_8197F 0x0552 465 #define REG_DUAL_TSF_RST_8197F 0x0553 466 #define REG_MBSSID_BCN_SPACE_8197F 0x0554 467 #define REG_DRVERLYINT_8197F 0x0558 468 #define REG_BCNDMATIM_8197F 0x0559 469 #define REG_ATIMWND_8197F 0x055A 470 #define REG_USTIME_TSF_8197F 0x055C 471 #define REG_BCN_MAX_ERR_8197F 0x055D 472 #define REG_RXTSF_OFFSET_CCK_8197F 0x055E 473 #define REG_RXTSF_OFFSET_OFDM_8197F 0x055F 474 #define REG_TSFTR_8197F 0x0560 475 #define REG_FREERUN_CNT_8197F 0x0568 476 #define REG_ATIMWND1_8197F 0x0570 477 #define REG_TBTT_PROHIBIT_INFRA_8197F 0x0571 478 #define REG_CTWND_8197F 0x0572 479 #define REG_BCNIVLCUNT_8197F 0x0573 480 #define REG_BCNDROPCTRL_8197F 0x0574 481 #define REG_HGQ_TIMEOUT_PERIOD_8197F 0x0575 482 #define REG_TXCMD_TIMEOUT_PERIOD_8197F 0x0576 483 #define REG_MISC_CTRL_8197F 0x0577 484 #define REG_BCN_CTRL_CLINT1_8197F 0x0578 485 #define REG_BCN_CTRL_CLINT2_8197F 0x0579 486 #define REG_BCN_CTRL_CLINT3_8197F 0x057A 487 #define REG_EXTEND_CTRL_8197F 0x057B 488 #define REG_P2PPS1_SPEC_STATE_8197F 0x057C 489 #define REG_P2PPS1_STATE_8197F 0x057D 490 #define REG_P2PPS2_SPEC_STATE_8197F 0x057E 491 #define REG_P2PPS2_STATE_8197F 0x057F 492 #define REG_PS_TIMER0_8197F 0x0580 493 #define REG_PS_TIMER1_8197F 0x0584 494 #define REG_PS_TIMER2_8197F 0x0588 495 #define REG_TBTT_CTN_AREA_8197F 0x058C 496 #define REG_FORCE_BCN_IFS_8197F 0x058E 497 #define REG_TXOP_MIN_8197F 0x0590 498 #define REG_PRE_BKF_TIME_8197F 0x0592 499 #define REG_CROSS_TXOP_CTRL_8197F 0x0593 500 #define REG_TBTT_INT_SHIFT_CLI0_8197F 0x0594 501 #define REG_TBTT_INT_SHIFT_CLI1_8197F 0x0595 502 #define REG_TBTT_INT_SHIFT_CLI2_8197F 0x0596 503 #define REG_TBTT_INT_SHIFT_CLI3_8197F 0x0597 504 #define REG_TBTT_INT_SHIFT_ENABLE_8197F 0x0598 505 #define REG_ATIMWND2_8197F 0x05A0 506 #define REG_ATIMWND3_8197F 0x05A1 507 #define REG_ATIMWND4_8197F 0x05A2 508 #define REG_ATIMWND5_8197F 0x05A3 509 #define REG_ATIMWND6_8197F 0x05A4 510 #define REG_ATIMWND7_8197F 0x05A5 511 #define REG_ATIMUGT_8197F 0x05A6 512 #define REG_HIQ_NO_LMT_EN_8197F 0x05A7 513 #define REG_DTIM_COUNTER_ROOT_8197F 0x05A8 514 #define REG_DTIM_COUNTER_VAP1_8197F 0x05A9 515 #define REG_DTIM_COUNTER_VAP2_8197F 0x05AA 516 #define REG_DTIM_COUNTER_VAP3_8197F 0x05AB 517 #define REG_DTIM_COUNTER_VAP4_8197F 0x05AC 518 #define REG_DTIM_COUNTER_VAP5_8197F 0x05AD 519 #define REG_DTIM_COUNTER_VAP6_8197F 0x05AE 520 #define REG_DTIM_COUNTER_VAP7_8197F 0x05AF 521 #define REG_DIS_ATIM_8197F 0x05B0 522 #define REG_EARLY_128US_8197F 0x05B1 523 #define REG_P2PPS1_CTRL_8197F 0x05B2 524 #define REG_P2PPS2_CTRL_8197F 0x05B3 525 #define REG_TIMER0_SRC_SEL_8197F 0x05B4 526 #define REG_NOA_UNIT_SEL_8197F 0x05B5 527 #define REG_P2POFF_DIS_TXTIME_8197F 0x05B7 528 #define REG_MBSSID_BCN_SPACE2_8197F 0x05B8 529 #define REG_MBSSID_BCN_SPACE3_8197F 0x05BC 530 #define REG_ACMHWCTRL_8197F 0x05C0 531 #define REG_ACMRSTCTRL_8197F 0x05C1 532 #define REG_ACMAVG_8197F 0x05C2 533 #define REG_VO_ADMTIME_8197F 0x05C4 534 #define REG_VI_ADMTIME_8197F 0x05C6 535 #define REG_BE_ADMTIME_8197F 0x05C8 536 #define REG_EDCA_RANDOM_GEN_8197F 0x05CC 537 #define REG_TXCMD_NOA_SEL_8197F 0x05CF 538 #define REG_NOA_PARAM_8197F 0x05E0 539 #define REG_P2P_RST_8197F 0x05F0 540 #define REG_SCHEDULER_RST_8197F 0x05F1 541 #define REG_SCH_TXCMD_8197F 0x05F8 542 #define REG_PAGE5_DUMMY_8197F 0x05FC 543 #define REG_CPUMGQ_TX_TIMER_8197F 0x1500 544 #define REG_PS_TIMER_A_8197F 0x1504 545 #define REG_PS_TIMER_B_8197F 0x1508 546 #define REG_PS_TIMER_C_8197F 0x150C 547 #define REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL_8197F 0x1510 548 #define REG_CPUMGQ_TX_TIMER_EARLY_8197F 0x1514 549 #define REG_PS_TIMER_A_EARLY_8197F 0x1515 550 #define REG_PS_TIMER_B_EARLY_8197F 0x1516 551 #define REG_PS_TIMER_C_EARLY_8197F 0x1517 552 #define REG_WMAC_CR_8197F 0x0600 553 #define REG_WMAC_FWPKT_CR_8197F 0x0601 554 #define REG_BWOPMODE_8197F 0x0603 555 #define REG_TCR_8197F 0x0604 556 #define REG_RCR_8197F 0x0608 557 #define REG_RX_PKT_LIMIT_8197F 0x060C 558 #define REG_RX_DLK_TIME_8197F 0x060D 559 #define REG_RX_DRVINFO_SZ_8197F 0x060F 560 #define REG_MACID_8197F 0x0610 561 #define REG_BSSID_8197F 0x0618 562 #define REG_MAR_8197F 0x0620 563 #define REG_MBIDCAMCFG_1_8197F 0x0628 564 #define REG_MBIDCAMCFG_2_8197F 0x062C 565 #define REG_WMAC_TCR_TSFT_OFS_8197F 0x0630 566 #define REG_UDF_THSD_8197F 0x0632 567 #define REG_ZLD_NUM_8197F 0x0633 568 #define REG_STMP_THSD_8197F 0x0634 569 #define REG_WMAC_TXTIMEOUT_8197F 0x0635 570 #define REG_MCU_TEST_2_V1_8197F 0x0636 571 #define REG_USTIME_EDCA_8197F 0x0638 572 #define REG_MAC_SPEC_SIFS_8197F 0x063A 573 #define REG_RESP_SIFS_CCK_8197F 0x063C 574 #define REG_RESP_SIFS_OFDM_8197F 0x063E 575 #define REG_ACKTO_8197F 0x0640 576 #define REG_CTS2TO_8197F 0x0641 577 #define REG_EIFS_8197F 0x0642 578 #define REG_NAV_CTRL_8197F 0x0650 579 #define REG_BACAMCMD_8197F 0x0654 580 #define REG_BACAMCONTENT_8197F 0x0658 581 #define REG_LBDLY_8197F 0x0660 582 #define REG_WMAC_BACAM_RPMEN_8197F 0x0661 583 #define REG_WMAC_BITMAP_CTL_8197F 0x0663 584 #define REG_RXERR_RPT_8197F 0x0664 585 #define REG_WMAC_TRXPTCL_CTL_8197F 0x0668 586 #define REG_CAMCMD_8197F 0x0670 587 #define REG_CAMWRITE_8197F 0x0674 588 #define REG_CAMREAD_8197F 0x0678 589 #define REG_CAMDBG_8197F 0x067C 590 #define REG_SECCFG_8197F 0x0680 591 #define REG_RXFILTER_CATEGORY_1_8197F 0x0682 592 #define REG_RXFILTER_ACTION_1_8197F 0x0683 593 #define REG_RXFILTER_CATEGORY_2_8197F 0x0684 594 #define REG_RXFILTER_ACTION_2_8197F 0x0685 595 #define REG_RXFILTER_CATEGORY_3_8197F 0x0686 596 #define REG_RXFILTER_ACTION_3_8197F 0x0687 597 #define REG_RXFLTMAP3_8197F 0x0688 598 #define REG_RXFLTMAP4_8197F 0x068A 599 #define REG_RXFLTMAP5_8197F 0x068C 600 #define REG_RXFLTMAP6_8197F 0x068E 601 #define REG_WOW_CTRL_8197F 0x0690 602 #define REG_PS_RX_INFO_8197F 0x0692 603 #define REG_WMMPS_UAPSD_TID_8197F 0x0693 604 #define REG_LPNAV_CTRL_8197F 0x0694 605 #define REG_WKFMCAM_CMD_8197F 0x0698 606 #define REG_WKFMCAM_RWD_8197F 0x069C 607 #define REG_RXFLTMAP0_8197F 0x06A0 608 #define REG_RXFLTMAP1_8197F 0x06A2 609 #define REG_RXFLTMAP_8197F 0x06A4 610 #define REG_BCN_PSR_RPT_8197F 0x06A8 611 #define REG_RXPKTMON_CTRL_8197F 0x06B0 612 #define REG_STATE_MON_8197F 0x06B4 613 #define REG_ERROR_MON_8197F 0x06B8 614 #define REG_SEARCH_MACID_8197F 0x06BC 615 #define REG_BT_COEX_TABLE_8197F 0x06C0 616 #define REG_RXCMD_0_8197F 0x06D0 617 #define REG_RXCMD_1_8197F 0x06D4 618 #define REG_WMAC_RESP_TXINFO_8197F 0x06D8 619 #define REG_BBPSF_CTRL_8197F 0x06DC 620 #define REG_P2P_RX_BCN_NOA_8197F 0x06E0 621 #define REG_ASSOCIATED_BFMER0_INFO_8197F 0x06E4 622 #define REG_ASSOCIATED_BFMER1_INFO_8197F 0x06EC 623 #define REG_TX_CSI_RPT_PARAM_BW20_8197F 0x06F4 624 #define REG_TX_CSI_RPT_PARAM_BW40_8197F 0x06F8 625 #define REG_TX_CSI_RPT_PARAM_BW80_8197F 0x06FC 626 #define REG_BCN_PSR_RPT2_8197F 0x1600 627 #define REG_BCN_PSR_RPT3_8197F 0x1604 628 #define REG_BCN_PSR_RPT4_8197F 0x1608 629 #define REG_A1_ADDR_MASK_8197F 0x160C 630 #define REG_MACID2_8197F 0x1620 631 #define REG_BSSID2_8197F 0x1628 632 #define REG_MACID3_8197F 0x1630 633 #define REG_BSSID3_8197F 0x1638 634 #define REG_MACID4_8197F 0x1640 635 #define REG_BSSID4_8197F 0x1648 636 #define REG_NOA_REPORT_8197F 0x1650 637 #define REG_PWRBIT_SETTING_8197F 0x1660 638 #define REG_WMAC_MU_BF_OPTION_8197F 0x167C 639 #define REG_WMAC_PAUSE_BB_CLR_TH_8197F 0x167D 640 #define REG_WMAC_MU_ARB_8197F 0x167E 641 #define REG_WMAC_MU_OPTION_8197F 0x167F 642 #define REG_WMAC_MU_BF_CTL_8197F 0x1680 643 #define REG_WMAC_MU_BFRPT_PARA_8197F 0x1682 644 #define REG_WMAC_ASSOCIATED_MU_BFMEE2_8197F 0x1684 645 #define REG_WMAC_ASSOCIATED_MU_BFMEE3_8197F 0x1686 646 #define REG_WMAC_ASSOCIATED_MU_BFMEE4_8197F 0x1688 647 #define REG_WMAC_ASSOCIATED_MU_BFMEE5_8197F 0x168A 648 #define REG_WMAC_ASSOCIATED_MU_BFMEE6_8197F 0x168C 649 #define REG_WMAC_ASSOCIATED_MU_BFMEE7_8197F 0x168E 650 #define REG_TRANSMIT_ADDRSS_0_8197F 0x16A0 651 #define REG_TRANSMIT_ADDRSS_1_8197F 0x16A8 652 #define REG_TRANSMIT_ADDRSS_2_8197F 0x16B0 653 #define REG_TRANSMIT_ADDRSS_3_8197F 0x16B8 654 #define REG_TRANSMIT_ADDRSS_4_8197F 0x16C0 655 #define REG_MACID1_8197F 0x0700 656 #define REG_BSSID1_8197F 0x0708 657 #define REG_BCN_PSR_RPT1_8197F 0x0710 658 #define REG_ASSOCIATED_BFMEE_SEL_8197F 0x0714 659 #define REG_SND_PTCL_CTRL_8197F 0x0718 660 #define REG_RX_CSI_RPT_INFO_8197F 0x071C 661 #define REG_NS_ARP_CTRL_8197F 0x0720 662 #define REG_NS_ARP_INFO_8197F 0x0724 663 #define REG_BEAMFORMING_INFO_NSARP_V1_8197F 0x0728 664 #define REG_BEAMFORMING_INFO_NSARP_8197F 0x072C 665 #define REG_WMAC_RTX_CTX_SUBTYPE_CFG_8197F 0x0750 666 #define REG_WMAC_SWAES_CFG_8197F 0x0760 667 #define REG_BT_COEX_V2_8197F 0x0762 668 #define REG_BT_COEX_8197F 0x0764 669 #define REG_WLAN_ACT_MASK_CTRL_8197F 0x0768 670 #define REG_BT_COEX_ENHANCED_INTR_CTRL_8197F 0x076E 671 #define REG_BT_ACT_STATISTICS_8197F 0x0770 672 #define REG_BT_STATISTICS_CONTROL_REGISTER_8197F 0x0778 673 #define REG_BT_STATUS_REPORT_REGISTER_8197F 0x077C 674 #define REG_BT_INTERRUPT_CONTROL_REGISTER_8197F 0x0780 675 #define REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER_8197F 0x0784 676 #define REG_BT_ISOLATION_TABLE_REGISTER_REGISTER_8197F 0x0785 677 #define REG_BT_INTERRUPT_STATUS_REGISTER_8197F 0x078F 678 #define REG_BT_TDMA_TIME_REGISTER_8197F 0x0790 679 #define REG_BT_ACT_REGISTER_8197F 0x0794 680 #define REG_OBFF_CTRL_BASIC_8197F 0x0798 681 #define REG_OBFF_CTRL2_TIMER_8197F 0x079C 682 #define REG_LTR_CTRL_BASIC_8197F 0x07A0 683 #define REG_LTR_CTRL2_TIMER_THRESHOLD_8197F 0x07A4 684 #define REG_LTR_IDLE_LATENCY_V1_8197F 0x07A8 685 #define REG_LTR_ACTIVE_LATENCY_V1_8197F 0x07AC 686 #define REG_ANTENNA_TRAINING_CONTROL_REGISTER_8197F 0x07B0 687 #define REG_WMAC_PKTCNT_RWD_8197F 0x07B8 688 #define REG_WMAC_PKTCNT_CTRL_8197F 0x07BC 689 #define REG_IQ_DUMP_8197F 0x07C0 690 #define REG_WMAC_FTM_CTL_8197F 0x07CC 691 #define REG_IQ_DUMP_EXT_8197F 0x07CF 692 #define REG_OFDM_CCK_LEN_MASK_8197F 0x07D0 693 #define REG_RX_FILTER_FUNCTION_8197F 0x07DA 694 #define REG_NDP_SIG_8197F 0x07E0 695 #define REG_TXCMD_INFO_FOR_RSP_PKT_8197F 0x07E4 696 #define REG_SEC_OPT_V2_8197F 0x07EC 697 #define REG_RTS_ADDRESS_0_8197F 0x07F0 698 #define REG_RTS_ADDRESS_1_8197F 0x07F8 699 #define REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1_8197F 0x1700 700 #define REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1_8197F 0x1704 701 #define REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1_8197F 0x1708 702 703 #endif 704