xref: /OK3568_Linux_fs/external/rkwifibt/drivers/rtl8821cs/include/rtl8812a_xmit.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /******************************************************************************
2*4882a593Smuzhiyun  *
3*4882a593Smuzhiyun  * Copyright(c) 2007 - 2017 Realtek Corporation.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify it
6*4882a593Smuzhiyun  * under the terms of version 2 of the GNU General Public License as
7*4882a593Smuzhiyun  * published by the Free Software Foundation.
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but WITHOUT
10*4882a593Smuzhiyun  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12*4882a593Smuzhiyun  * more details.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *****************************************************************************/
15*4882a593Smuzhiyun #ifndef __RTL8812A_XMIT_H__
16*4882a593Smuzhiyun #define __RTL8812A_XMIT_H__
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun /* For 88e early mode */
20*4882a593Smuzhiyun #define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
21*4882a593Smuzhiyun #define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
22*4882a593Smuzhiyun #define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
23*4882a593Smuzhiyun #define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
24*4882a593Smuzhiyun #define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value)
25*4882a593Smuzhiyun #define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value)
26*4882a593Smuzhiyun #define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value)
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun  * defined for TX DESC Operation
30*4882a593Smuzhiyun  *   */
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define MAX_TID (15)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* OFFSET 0 */
35*4882a593Smuzhiyun #define OFFSET_SZ	0
36*4882a593Smuzhiyun #define OFFSET_SHT	16
37*4882a593Smuzhiyun #define BMC			BIT(24)
38*4882a593Smuzhiyun #define LSG			BIT(26)
39*4882a593Smuzhiyun #define FSG			BIT(27)
40*4882a593Smuzhiyun #define OWN		BIT(31)
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun /* OFFSET 4 */
44*4882a593Smuzhiyun #define PKT_OFFSET_SZ		0
45*4882a593Smuzhiyun #define QSEL_SHT			8
46*4882a593Smuzhiyun #define RATE_ID_SHT			16
47*4882a593Smuzhiyun #define NAVUSEHDR			BIT(20)
48*4882a593Smuzhiyun #define SEC_TYPE_SHT		22
49*4882a593Smuzhiyun #define PKT_OFFSET_SHT		26
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* OFFSET 8 */
52*4882a593Smuzhiyun #define AGG_EN				BIT(12)
53*4882a593Smuzhiyun #define AGG_BK				BIT(16)
54*4882a593Smuzhiyun #define AMPDU_DENSITY_SHT	20
55*4882a593Smuzhiyun #define ANTSEL_A			BIT(24)
56*4882a593Smuzhiyun #define ANTSEL_B			BIT(25)
57*4882a593Smuzhiyun #define TX_ANT_CCK_SHT		26
58*4882a593Smuzhiyun #define TX_ANTL_SHT			28
59*4882a593Smuzhiyun #define TX_ANT_HT_SHT		30
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun /* OFFSET 12 */
62*4882a593Smuzhiyun #define SEQ_SHT				16
63*4882a593Smuzhiyun #define EN_HWSEQ			BIT(31)
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun /* OFFSET 16 */
66*4882a593Smuzhiyun #define QOS					BIT(6)
67*4882a593Smuzhiyun #define	HW_SSN				BIT(7)
68*4882a593Smuzhiyun #define USERATE				BIT(8)
69*4882a593Smuzhiyun #define DISDATAFB			BIT(10)
70*4882a593Smuzhiyun #define CTS_2_SELF			BIT(11)
71*4882a593Smuzhiyun #define	RTS_EN				BIT(12)
72*4882a593Smuzhiyun #define	HW_RTS_EN			BIT(13)
73*4882a593Smuzhiyun #define DATA_SHORT			BIT(24)
74*4882a593Smuzhiyun #define PWR_STATUS_SHT	15
75*4882a593Smuzhiyun #define DATA_SC_SHT		20
76*4882a593Smuzhiyun #define DATA_BW				BIT(25)
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /* OFFSET 20 */
79*4882a593Smuzhiyun #define	RTY_LMT_EN			BIT(17)
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* OFFSET 20 */
82*4882a593Smuzhiyun #define SGI					BIT(6)
83*4882a593Smuzhiyun #define USB_TXAGG_NUM_SHT	24
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun typedef struct txdescriptor_8812 {
86*4882a593Smuzhiyun 	/* Offset 0 */
87*4882a593Smuzhiyun 	u32 pktlen:16;
88*4882a593Smuzhiyun 	u32 offset:8;
89*4882a593Smuzhiyun 	u32 bmc:1;
90*4882a593Smuzhiyun 	u32 htc:1;
91*4882a593Smuzhiyun 	u32 ls:1;
92*4882a593Smuzhiyun 	u32 fs:1;
93*4882a593Smuzhiyun 	u32 linip:1;
94*4882a593Smuzhiyun 	u32 noacm:1;
95*4882a593Smuzhiyun 	u32 gf:1;
96*4882a593Smuzhiyun 	u32 own:1;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/* Offset 4 */
99*4882a593Smuzhiyun 	u32 macid:6;
100*4882a593Smuzhiyun 	u32 rsvd0406:2;
101*4882a593Smuzhiyun 	u32 qsel:5;
102*4882a593Smuzhiyun 	u32 rd_nav_ext:1;
103*4882a593Smuzhiyun 	u32 lsig_txop_en:1;
104*4882a593Smuzhiyun 	u32 pifs:1;
105*4882a593Smuzhiyun 	u32 rate_id:4;
106*4882a593Smuzhiyun 	u32 navusehdr:1;
107*4882a593Smuzhiyun 	u32 en_desc_id:1;
108*4882a593Smuzhiyun 	u32 sectype:2;
109*4882a593Smuzhiyun 	u32 rsvd0424:2;
110*4882a593Smuzhiyun 	u32 pkt_offset:5;	/* unit: 8 bytes */
111*4882a593Smuzhiyun 	u32 rsvd0431:1;
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	/* Offset 8 */
114*4882a593Smuzhiyun 	u32 rts_rc:6;
115*4882a593Smuzhiyun 	u32 data_rc:6;
116*4882a593Smuzhiyun 	u32 agg_en:1;
117*4882a593Smuzhiyun 	u32 rd_en:1;
118*4882a593Smuzhiyun 	u32 bar_rty_th:2;
119*4882a593Smuzhiyun 	u32 bk:1;
120*4882a593Smuzhiyun 	u32 morefrag:1;
121*4882a593Smuzhiyun 	u32 raw:1;
122*4882a593Smuzhiyun 	u32 ccx:1;
123*4882a593Smuzhiyun 	u32 ampdu_density:3;
124*4882a593Smuzhiyun 	u32 bt_null:1;
125*4882a593Smuzhiyun 	u32 ant_sel_a:1;
126*4882a593Smuzhiyun 	u32 ant_sel_b:1;
127*4882a593Smuzhiyun 	u32 tx_ant_cck:2;
128*4882a593Smuzhiyun 	u32 tx_antl:2;
129*4882a593Smuzhiyun 	u32 tx_ant_ht:2;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	/* Offset 12 */
132*4882a593Smuzhiyun 	u32 nextheadpage:8;
133*4882a593Smuzhiyun 	u32 tailpage:8;
134*4882a593Smuzhiyun 	u32 seq:12;
135*4882a593Smuzhiyun 	u32 cpu_handle:1;
136*4882a593Smuzhiyun 	u32 tag1:1;
137*4882a593Smuzhiyun 	u32 trigger_int:1;
138*4882a593Smuzhiyun 	u32 hwseq_en:1;
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun 	/* Offset 16 */
141*4882a593Smuzhiyun 	u32 rtsrate:5;
142*4882a593Smuzhiyun 	u32 ap_dcfe:1;
143*4882a593Smuzhiyun 	u32 hwseq_sel:2;
144*4882a593Smuzhiyun 	u32 userate:1;
145*4882a593Smuzhiyun 	u32 disrtsfb:1;
146*4882a593Smuzhiyun 	u32 disdatafb:1;
147*4882a593Smuzhiyun 	u32 cts2self:1;
148*4882a593Smuzhiyun 	u32 rtsen:1;
149*4882a593Smuzhiyun 	u32 hw_rts_en:1;
150*4882a593Smuzhiyun 	u32 port_id:1;
151*4882a593Smuzhiyun 	u32 pwr_status:3;
152*4882a593Smuzhiyun 	u32 wait_dcts:1;
153*4882a593Smuzhiyun 	u32 cts2ap_en:1;
154*4882a593Smuzhiyun 	u32 data_sc:2;
155*4882a593Smuzhiyun 	u32 data_stbc:2;
156*4882a593Smuzhiyun 	u32 data_short:1;
157*4882a593Smuzhiyun 	u32 data_bw:1;
158*4882a593Smuzhiyun 	u32 rts_short:1;
159*4882a593Smuzhiyun 	u32 rts_bw:1;
160*4882a593Smuzhiyun 	u32 rts_sc:2;
161*4882a593Smuzhiyun 	u32 vcs_stbc:2;
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun 	/* Offset 20 */
164*4882a593Smuzhiyun 	u32 datarate:6;
165*4882a593Smuzhiyun 	u32 sgi:1;
166*4882a593Smuzhiyun 	u32 try_rate:1;
167*4882a593Smuzhiyun 	u32 data_ratefb_lmt:5;
168*4882a593Smuzhiyun 	u32 rts_ratefb_lmt:4;
169*4882a593Smuzhiyun 	u32 rty_lmt_en:1;
170*4882a593Smuzhiyun 	u32 data_rt_lmt:6;
171*4882a593Smuzhiyun 	u32 usb_txagg_num:8;
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun 	/* Offset 24 */
174*4882a593Smuzhiyun 	u32 txagg_a:5;
175*4882a593Smuzhiyun 	u32 txagg_b:5;
176*4882a593Smuzhiyun 	u32 use_max_len:1;
177*4882a593Smuzhiyun 	u32 max_agg_num:5;
178*4882a593Smuzhiyun 	u32 mcsg1_max_len:4;
179*4882a593Smuzhiyun 	u32 mcsg2_max_len:4;
180*4882a593Smuzhiyun 	u32 mcsg3_max_len:4;
181*4882a593Smuzhiyun 	u32 mcs7_sgi_max_len:4;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 	/* Offset 28 */
184*4882a593Smuzhiyun 	u32 checksum:16;	/* TxBuffSize(PCIe)/CheckSum(USB) */
185*4882a593Smuzhiyun 	u32 mcsg4_max_len:4;
186*4882a593Smuzhiyun 	u32 mcsg5_max_len:4;
187*4882a593Smuzhiyun 	u32 mcsg6_max_len:4;
188*4882a593Smuzhiyun 	u32 mcs15_sgi_max_len:4;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	/* Offset 32 */
191*4882a593Smuzhiyun 	u32 rsvd32;
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun 	/* Offset 36 */
194*4882a593Smuzhiyun 	u32 rsvd36;
195*4882a593Smuzhiyun } TXDESC_8812, *PTXDESC_8812;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun /* Dword 0 */
199*4882a593Smuzhiyun #define GET_TX_DESC_OWN_8812(__pTxDesc)				LE_BITS_TO_4BYTE(__pTxDesc, 31, 1)
200*4882a593Smuzhiyun #define SET_TX_DESC_PKT_SIZE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 0, 16, __Value)
201*4882a593Smuzhiyun #define SET_TX_DESC_OFFSET_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 16, 8, __Value)
202*4882a593Smuzhiyun #define SET_TX_DESC_BMC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 24, 1, __Value)
203*4882a593Smuzhiyun #define SET_TX_DESC_HTC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 25, 1, __Value)
204*4882a593Smuzhiyun #define SET_TX_DESC_LAST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 26, 1, __Value)
205*4882a593Smuzhiyun #define SET_TX_DESC_FIRST_SEG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 27, 1, __Value)
206*4882a593Smuzhiyun #define SET_TX_DESC_LINIP_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 28, 1, __Value)
207*4882a593Smuzhiyun #define SET_TX_DESC_NO_ACM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 29, 1, __Value)
208*4882a593Smuzhiyun #define SET_TX_DESC_GF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 30, 1, __Value)
209*4882a593Smuzhiyun #define SET_TX_DESC_OWN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc, 31, 1, __Value)
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* Dword 1 */
212*4882a593Smuzhiyun #define SET_TX_DESC_MACID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 0, 7, __Value)
213*4882a593Smuzhiyun #define SET_TX_DESC_QUEUE_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 8, 5, __Value)
214*4882a593Smuzhiyun #define SET_TX_DESC_RDG_NAV_EXT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 13, 1, __Value)
215*4882a593Smuzhiyun #define SET_TX_DESC_LSIG_TXOP_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 14, 1, __Value)
216*4882a593Smuzhiyun #define SET_TX_DESC_PIFS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 15, 1, __Value)
217*4882a593Smuzhiyun #define SET_TX_DESC_RATE_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 16, 5, __Value)
218*4882a593Smuzhiyun #define SET_TX_DESC_EN_DESC_ID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 21, 1, __Value)
219*4882a593Smuzhiyun #define SET_TX_DESC_SEC_TYPE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 22, 2, __Value)
220*4882a593Smuzhiyun #define SET_TX_DESC_PKT_OFFSET_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+4, 24, 5, __Value)
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun /* Dword 2 */
223*4882a593Smuzhiyun #define SET_TX_DESC_PAID_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 0,  9, __Value)
224*4882a593Smuzhiyun #define SET_TX_DESC_CCA_RTS_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 10, 2, __Value)
225*4882a593Smuzhiyun #define SET_TX_DESC_AGG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 12, 1, __Value)
226*4882a593Smuzhiyun #define SET_TX_DESC_RDG_ENABLE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 13, 1, __Value)
227*4882a593Smuzhiyun #define SET_TX_DESC_AGG_BREAK_8812(__pTxDesc, __Value)				SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 16, 1, __Value)
228*4882a593Smuzhiyun #define SET_TX_DESC_MORE_FRAG_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 17, 1, __Value)
229*4882a593Smuzhiyun #define SET_TX_DESC_RAW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 18, 1, __Value)
230*4882a593Smuzhiyun #define SET_TX_DESC_SPE_RPT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 19, 1, __Value)
231*4882a593Smuzhiyun #define SET_TX_DESC_AMPDU_DENSITY_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 20, 3, __Value)
232*4882a593Smuzhiyun #define SET_TX_DESC_BT_INT_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 23, 1, __Value)
233*4882a593Smuzhiyun #define SET_TX_DESC_GID_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+8, 24, 6, __Value)
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun /* Dword 3 */
236*4882a593Smuzhiyun #define SET_TX_DESC_WHEADER_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 0, 4, __Value)
237*4882a593Smuzhiyun #define SET_TX_DESC_CHK_EN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 4, 1, __Value)
238*4882a593Smuzhiyun #define SET_TX_DESC_EARLY_MODE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 5, 1, __Value)
239*4882a593Smuzhiyun #define SET_TX_DESC_HWSEQ_SEL_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 6, 2, __Value)
240*4882a593Smuzhiyun #define SET_TX_DESC_USE_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 8, 1, __Value)
241*4882a593Smuzhiyun #define SET_TX_DESC_DISABLE_RTS_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 9, 1, __Value)
242*4882a593Smuzhiyun #define SET_TX_DESC_DISABLE_FB_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 10, 1, __Value)
243*4882a593Smuzhiyun #define SET_TX_DESC_CTS2SELF_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 11, 1, __Value)
244*4882a593Smuzhiyun #define SET_TX_DESC_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 12, 1, __Value)
245*4882a593Smuzhiyun #define SET_TX_DESC_HW_RTS_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 13, 1, __Value)
246*4882a593Smuzhiyun #define SET_TX_DESC_NAV_USE_HDR_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 15, 1, __Value)
247*4882a593Smuzhiyun #define SET_TX_DESC_USE_MAX_LEN_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 16, 1, __Value)
248*4882a593Smuzhiyun #define SET_TX_DESC_MAX_AGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 17, 5, __Value)
249*4882a593Smuzhiyun #define SET_TX_DESC_NDPA_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 22, 2, __Value)
250*4882a593Smuzhiyun #define SET_TX_DESC_AMPDU_MAX_TIME_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+12, 24, 8, __Value)
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun /* Dword 4 */
253*4882a593Smuzhiyun #define SET_TX_DESC_TX_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 0, 7, __Value)
254*4882a593Smuzhiyun #define SET_TX_DESC_DATA_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 8, 5, __Value)
255*4882a593Smuzhiyun #define SET_TX_DESC_RTS_RATE_FB_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 13, 4, __Value)
256*4882a593Smuzhiyun #define SET_TX_DESC_RETRY_LIMIT_ENABLE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 17, 1, __Value)
257*4882a593Smuzhiyun #define SET_TX_DESC_DATA_RETRY_LIMIT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 18, 6, __Value)
258*4882a593Smuzhiyun #define SET_TX_DESC_RTS_RATE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+16, 24, 5, __Value)
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun /* Dword 5 */
261*4882a593Smuzhiyun #define SET_TX_DESC_DATA_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 0, 4, __Value)
262*4882a593Smuzhiyun #define SET_TX_DESC_DATA_SHORT_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 4, 1, __Value)
263*4882a593Smuzhiyun #define SET_TX_DESC_DATA_BW_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 5, 2, __Value)
264*4882a593Smuzhiyun #define SET_TX_DESC_DATA_LDPC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 7, 1, __Value)
265*4882a593Smuzhiyun #define SET_TX_DESC_DATA_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 8, 2, __Value)
266*4882a593Smuzhiyun #define SET_TX_DESC_CTROL_STBC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 10, 2, __Value)
267*4882a593Smuzhiyun #define SET_TX_DESC_RTS_SHORT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 12, 1, __Value)
268*4882a593Smuzhiyun #define SET_TX_DESC_RTS_SC_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 13, 4, __Value)
269*4882a593Smuzhiyun #define SET_TX_DESC_TX_ANT_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+20, 24, 4, __Value)
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun /* Dword 6 */
272*4882a593Smuzhiyun #define SET_TX_DESC_SW_DEFINE_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 0, 12, __Value)
273*4882a593Smuzhiyun #define SET_TX_DESC_ANTSEL_A_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 16, 3, __Value)
274*4882a593Smuzhiyun #define SET_TX_DESC_ANTSEL_B_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 19, 3, __Value)
275*4882a593Smuzhiyun #define SET_TX_DESC_ANTSEL_C_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 22, 3, __Value)
276*4882a593Smuzhiyun #define SET_TX_DESC_ANTSEL_D_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 25, 3, __Value)
277*4882a593Smuzhiyun #define SET_TX_DESC_MBSSID_8821(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+24, 12, 4, __Value)
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun /* Dword 7 */
280*4882a593Smuzhiyun #define SET_TX_DESC_TX_BUFFER_SIZE_8812(__pTxDesc, __Value)		SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
281*4882a593Smuzhiyun #define SET_TX_DESC_TX_DESC_CHECKSUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 0, 16, __Value)
282*4882a593Smuzhiyun #define SET_TX_DESC_USB_TXAGG_NUM_8812(__pTxDesc, __Value) SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 24, 8, __Value)
283*4882a593Smuzhiyun #ifdef CONFIG_SDIO_HCI
284*4882a593Smuzhiyun #define SET_TX_DESC_SDIO_TXSEQ_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+28, 16, 8, __Value)
285*4882a593Smuzhiyun #endif
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun /* Dword 8 */
288*4882a593Smuzhiyun #define SET_TX_DESC_HWSEQ_EN_8812(__pTxDesc, __Value)			SET_BITS_TO_LE_4BYTE(__pTxDesc+32, 15, 1, __Value)
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun /* Dword 9 */
291*4882a593Smuzhiyun #define SET_TX_DESC_SEQ_8812(__pTxDesc, __Value)					SET_BITS_TO_LE_4BYTE(__pTxDesc+36, 12, 12, __Value)
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun /* Dword 10 */
294*4882a593Smuzhiyun #define SET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+40, 0, 32, __Value)
295*4882a593Smuzhiyun #define GET_TX_DESC_TX_BUFFER_ADDRESS_8812(__pTxDesc)	LE_BITS_TO_4BYTE(__pTxDesc+40, 0, 32)
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun /* Dword 11 */
298*4882a593Smuzhiyun #define SET_TX_DESC_NEXT_DESC_ADDRESS_8812(__pTxDesc, __Value)	SET_BITS_TO_LE_4BYTE(__pTxDesc+48, 0, 32, __Value)
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun #define SET_EARLYMODE_PKTNUM_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 0, 4, __Value)
302*4882a593Smuzhiyun #define SET_EARLYMODE_LEN0_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 4, 15, __Value)
303*4882a593Smuzhiyun #define SET_EARLYMODE_LEN1_1_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr, 19, 13, __Value)
304*4882a593Smuzhiyun #define SET_EARLYMODE_LEN1_2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 2, __Value)
305*4882a593Smuzhiyun #define SET_EARLYMODE_LEN2_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 2, 15,  __Value)
306*4882a593Smuzhiyun #define SET_EARLYMODE_LEN3_8812(__pAddr, __Value)					SET_BITS_TO_LE_4BYTE(__pAddr+4, 17, 15, __Value)
307*4882a593Smuzhiyun 
308*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE
309*4882a593Smuzhiyun 	#define USB_DUMMY_OFFSET		2
310*4882a593Smuzhiyun #else
311*4882a593Smuzhiyun 	#define USB_DUMMY_OFFSET		1
312*4882a593Smuzhiyun #endif
313*4882a593Smuzhiyun #define USB_DUMMY_LENGTH		(USB_DUMMY_OFFSET * PACKET_OFFSET_SZ)
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun void rtl8812a_cal_txdesc_chksum(u8 *ptxdesc);
317*4882a593Smuzhiyun void rtl8812a_fill_fake_txdesc(PADAPTER	padapter, u8 *pDesc, u32 BufferLen, u8 IsPsPoll, u8	IsBTQosNull, u8 bDataFrame);
318*4882a593Smuzhiyun void rtl8812a_fill_txdesc_sectype(struct pkt_attrib *pattrib, u8 *ptxdesc);
319*4882a593Smuzhiyun void rtl8812a_fill_txdesc_vcs(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
320*4882a593Smuzhiyun void rtl8812a_fill_txdesc_phy(PADAPTER padapter, struct pkt_attrib *pattrib, u8 *ptxdesc);
321*4882a593Smuzhiyun void fill_txdesc_force_bmc_camid(struct pkt_attrib *pattrib, u8 *ptxdesc);
322*4882a593Smuzhiyun void fill_txdesc_bmc_tx_rate(struct pkt_attrib *pattrib, u8 *ptxdesc);
323*4882a593Smuzhiyun 
324*4882a593Smuzhiyun #ifdef CONFIG_USB_HCI
325*4882a593Smuzhiyun s32 rtl8812au_init_xmit_priv(PADAPTER padapter);
326*4882a593Smuzhiyun void rtl8812au_free_xmit_priv(PADAPTER padapter);
327*4882a593Smuzhiyun s32 rtl8812au_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
328*4882a593Smuzhiyun s32 rtl8812au_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
329*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
330*4882a593Smuzhiyun s32 rtl8812au_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
331*4882a593Smuzhiyun #endif
332*4882a593Smuzhiyun s32	 rtl8812au_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
333*4882a593Smuzhiyun s32 rtl8812au_xmit_buf_handler(PADAPTER padapter);
334*4882a593Smuzhiyun void rtl8812au_xmit_tasklet(unsigned long priv);
335*4882a593Smuzhiyun s32 rtl8812au_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
336*4882a593Smuzhiyun #endif
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun #ifdef CONFIG_PCI_HCI
339*4882a593Smuzhiyun s32 rtl8812ae_init_xmit_priv(PADAPTER padapter);
340*4882a593Smuzhiyun void rtl8812ae_free_xmit_priv(PADAPTER padapter);
341*4882a593Smuzhiyun struct xmit_buf *rtl8812ae_dequeue_xmitbuf(struct rtw_tx_ring *ring);
342*4882a593Smuzhiyun void	rtl8812ae_xmitframe_resume(_adapter *padapter);
343*4882a593Smuzhiyun s32 rtl8812ae_hal_xmit(PADAPTER padapter, struct xmit_frame *pxmitframe);
344*4882a593Smuzhiyun s32 rtl8812ae_mgnt_xmit(PADAPTER padapter, struct xmit_frame *pmgntframe);
345*4882a593Smuzhiyun #ifdef CONFIG_RTW_MGMT_QUEUE
346*4882a593Smuzhiyun s32 rtl8812ae_hal_mgmt_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
347*4882a593Smuzhiyun #endif
348*4882a593Smuzhiyun s32	rtl8812ae_hal_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe);
349*4882a593Smuzhiyun void rtl8812ae_xmit_tasklet(void *priv);
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun #ifdef CONFIG_XMIT_THREAD_MODE
352*4882a593Smuzhiyun s32 rtl8812ae_xmit_buf_handler(_adapter *padapter);
353*4882a593Smuzhiyun #endif
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun #endif
356*4882a593Smuzhiyun 
357*4882a593Smuzhiyun #ifdef CONFIG_TX_EARLY_MODE
358*4882a593Smuzhiyun void UpdateEarlyModeInfo8812(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf);
359*4882a593Smuzhiyun #endif
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun void _dbg_dump_tx_info(_adapter	*padapter, int frame_tag, u8 *ptxdesc);
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun u8	BWMapping_8812(PADAPTER Adapter, struct pkt_attrib *pattrib);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun u8	SCMapping_8812(PADAPTER Adapter, struct pkt_attrib	*pattrib);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun #endif /* __RTL8812_XMIT_H__ */
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun #ifdef CONFIG_RTL8821A
370*4882a593Smuzhiyun #include "rtl8821a_xmit.h"
371*4882a593Smuzhiyun #endif /* CONFIG_RTL8821A */
372